Altium

Design Rule Verification Report

Date:		12/16/2019
Time:		3:21:47 PM
Elapsed Time:		00:00:02
Filename:		D:\AMC13projects\T2New2FLASH\T2New2019.PcbDoc

Warnings:		0
Rule Violations:		1

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.394mm) ((InPolygon)),((InPadClass('diffpads')))	0
Clearance Constraint (Gap=0.127mm) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=0.1mm) (Max=1mm) (Preferred=0.178mm) (All)	0
Routing Via (MinHoleWidth=0.3mm) (MaxHoleWidth=0.711mm) (PreferredHoleWidth=0.3mm) (MinWidth=0.559mm) (MaxWidth=1.27mm) (PreferedWidth=0.6mm) (All)	0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.127mm) (Max=1.27mm) (Prefered=0.305mm) and Width Constraints (Min=0.127mm) (Max=0.381mm) (Prefered=0.127mm) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.127mm) (Conductor Width=0.254mm) (Air Gap=0.127mm) (Entries=4) ((InPadClass('All Pads')))	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.203mm) (Conductor Width=0.254mm) (Air Gap=0.152mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=12mm) (All)	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.254mm) (Disabled)(All),(All)	0
Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All)	0
Silk to Silk (Clearance=0.127mm) (All),(All)	0
Net Antennae (Tolerance=0mm) (All)	0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (All),(All)	1
Total	1

Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (All),(All)
Component Clearance Constraint: (Collision < 0.254mm) Between Component SN1-SN8 (58mm,55.9mm) on Top Layer And SMT Small Component C4-GRM32ER60J107ME20L (63.8mm,53.7mm) on Top Layer