July 13 2015 T1 version 0x8124 and T2 version 0x29 New T2 firmware supports LUT trigger for DT people It is probably unrelated to G-2 application July 9 2015 T1 version 0x8124 and T2 version 0x28 Link version set to the correct value of 0x10 July 6 2015 T1 version 0x8123 and T2 version 0x28 New T2 firmware supports both 8 bit and 9 bit SN July 2 2015 T1 version 0x8123 and T2 version 0x27 From this version on, it has one more SN bit(SN8) It works with T2 firmware supporting both 8 or 9 bit SN June 25 2015 T1 version 0x8122 and T2 version 0x27 Fixed a bug in AMC_DATA_FIFO.vhd(built-in FIFO of 18K has a maximum length of 4K even when width is only 1), i_FIFO63 changed from 18K to 36K Added registers in AMC status to monitor AMC_DATA_FIFO WRERR/RDERR June 11 2015 T1 version 0x8120 and T2 version 0x27 Fixed a bug with internally generated TTC command, it required use of internally generated L1A must be set at the same time. May 7 2015 T1 version 0x811f and T2 version 0x27 fixed a bug in random trigger and added reg 0x2c which shows L1A rate in Herz May 4 2015 T1 version 0x811e and T2 version 0x27 random trigger modified. Apr. 27 2015 T1 version 0x811d and T2 version 0x27 Fixed a bug in the eventinfo FIFO output register in AMC_LINK Added reg 0xe30-e3b to count total event word of each AMC module read by event builder(only 6 LSBs are kept) bit 30 added to TTC configuration registers 0x24-0x27 to enable sending single TTC command by writing bit 8 of reg 0x0 Added reg 0xe49, 0xe59 ... to record the event number, TTS and error type added counters 0x52-57 to monitor L1A throttling For DAQLINK version16 Mar. 30 2015 T1 version 0x811c and T2 version 0x27 vivado compiling problem found. Recompiled Mar. 29 2015 T1 version 0x811b and T2 version 0x27 For DAQLINK version v0xb(fixed a bug in TTS_TRIG_IF) Fixed a bug in amc_data_fifo in amc_link Fixed a bug of SendTTS handling in amc_link Mar. 18 2015 T1 version 0x8119 and T2 version 0x27 For DAQLINK version9 Added AMC counters of offset 0x30-0x3d Mar. 14 2015 T1 version 0x8118 and T2 version 0x27 fixed several problems: Faked AMC modules will cause BUSY TTS states When no AMC module is enabled, events can't be built Mar. 4 2015 T1 version 0x8117 and T2 version 0x27 DAQ_link for AMC modules now has version 7, AMC13 firmware must update to it too. Mar. 2 2015 T1 version 0x8116 and T2 version 0x27 T2 register 0x3 added bits 28-26 for diagnose purposes Feb. 24 2015 T1 version 0x8116 and T2 version 0x26 AMC TTS state when not enabled changed to Ready Feb. 20 2015 T1 version 0x8115 and T2 version 0x26 TTC ReSync command will reset AMC13 TTS state to busy register 0x2b added which can be used to define the ReSync command(default is current value) registers 0xe1a, 0xe1b and 0xe1c added bits to record AMC TTS critical states Feb. 12 2015 T1 version 0x8114 and T2 version 0x26 mask added to register 0x2a Jan. 31 2014 T1 version 0x8113 and T2 version 0x26 TTC command history added to T2, following registers have been changed/added: 0x0, 0xd, 0x20-0x30 and 0x800-0xfff Jan. 25 2014 T1 version 0x8113 and T2 version 0x25 problem with Vivado constraints set_input_delay and set_output_delay fixed New T2 firmware 0x25 for both 6Slx45 and 6Slx25 which fixed a timing problem for 6Slx25 flavor New T2 firmware also added new counters for counting TTC commands received, please refer to the updated T2 memory map Jan. 15 2014 T1 version 0x8112 and T2 version 0x21 found a problem with Vivado time constraint set_output_delay used a workaround to fix the timing problem shown in 0x4012 Modified response to event counter reset broadcast command to make it resync compatible Dec. 10 2014 T1 version 0x8111 and T2 version 0x24 fixed a BX gap L1A rule problem Dec. 10 2014 T1 version 0x8110 and T2 version 0x24 fixed a per BX L1A rule problem Dec. 9 2014 T1 version 0x810f and T2 version 0x24 fixed a local random L1A rule problem Dec. 8 2014 T1 version 0x810e and T2 version 0x24 added register 0x2a for Orbit counter reset command. Its default value remains the same as currently defined command, so no software changes needed. Another change is that the general reset will not reset OcN now. Dec. 4 2014 T1 version 0x810d and T2 version 0x24 in reg 0x1, enable T3 trigger bit moved to bit 13, because bit 5 is now used for enabling locally generated TTC commands. v0x810c does not support T3 trigger. Dec. 1 2014 T1 version 0x810c and T2 version 0x24 Added filter for TTS from AMC modules: if the TTS is disconnect, out of sync or error, it has to be repeated four times to accept these states. AMC TTS state can be read at 0xe47, 0xe57, ... , 0xef7 now bit 5 of reg 0x1 added to enable AMC13 generated TTC command added AMC_link counters to monitor AMC TTS signal at offset 0x7a-0x7f bad AMC event CRC counter added TTS from AMCs is used to throttle locally generated L1As registers 0x20 thru 0x29 added July 30 2014 T1 version 0x810b and T2 version 0x24 This new version fixed many potential problems and it also implemented new TTS transmission scheme. July 9 2014 T1 version 0x810a and T2 version 0x24 T1 v0x810a should work with T3_TCDS_aux1 trigger T2 v0x24 added a counter for T3_TCDS_aux1 signal. The counter can be read at bits 15-0 of register 0xb June 24 2014 T1 version 0x8109 and T2 version 0x23 0x8109 added external trigger from T3, which can be enabled by setting bit 5 and 2 of register 0x1 T2 version 0x23 forwards T3_TCDS_aux1 signal to T1. So to make it work, both T1 and T2 need be updated June 14 2014 T1 version 0x8108 and T2 version 0x21 Finally fixed block CRC problem June 11 2014 T1 version 0x8107 and T2 version 0x21 Fixed a typo in the block CRC(CRC32D64) module and also fixed a problem with faked event CRC (per AMC) insertion added counters 0x1c0d-0x1c0f which counts event cmsCRC errors This version is compiled with Vivado 2014.2 June 2 2014 T1 version 0x8106 and T2 version 0x21 To match AMC daq_link updated version May 31 2014 T1 version 0x8105 and T2 version 0x21 added TTS_coded and state to register 0x19 read back fixed TTS from AMC to AMC13 initialization problem fixed a bug with faked data May 28 2014 T1 version 0x8104 and T2 version 0x21 fixed a L1A buffer problem in amc_link fixed a DNA read out bug which missed bit 56 May 27 2014 T1 version 0x8103 and T2 version 0x21 fixed all known problems(AMC link and event building) May 15 2014 T1 version 0x8101 and T2 version 0x21 New T1 will have unused GTXs powered down to lower the chip temperature whenever possible. T2 version 0x21 will have correct MAC address for SN number >= 64 A bug in TCP buffer control is fixed in this version, users of 0x8100 must immediately upgrade to this version. This version also fixed a reset problem and simplified the initialization procedure: After setting up the setup registers, write 1 to register 0x0 and the system will be ready.(write 0x10 to register 0x0 is still available, but not needed any more) Known problem. Some time the Ethernet can get into a state where it does not ping and reset does not work. Only FPGA reconfiguration can fix it. May 13 2014 T1 version 0x8100 and T2 version 0x20 Starting fromv0x8100, event built uses new data format(multiblock event) Biggest change in T1's memory map is that the monitored event window has been moved from 0x4000 to 0x20000 and the window size changed from 0x4000 to 0x20000 32bit words The memory page address has reduced from 13 bits to 10 bits. If front panel output is enabled, monitoring buffer is used as TCP buffer and can not be accessed. Another function added is that if MMC sets IP address as all 0, RARP is enabled(T1 and T2 must be set independently) AMC modules TTS signal can be individually disabled by writing to register 0x1a(when it is not used or malfunctions) Mar. 27 2014 T1 version 0x800a and T2 version 0x1c ipbus interface code modified. transactor_sm.vhd changed back to module come with ipbus_2_0_v1.r27848 Mar. 19 2014 T1 version 0x8008 and T2 version 0x1b problem detected, replace transcator_sm.vhd with the home-modified version Mar. 18 2014 T1 version 0x8007 and T2 version 0x1a ipbus firmware updated to ipbus_2_0_v1.r27848 Mar. 18 2014 T1 version 0x8006 and T2 version 0x19 A lot of bugs have been fixed since 0x8003 Now it can work smoothly with mtu set to 1500. When set to higher mtu, TCP client lost too many packets and the congestion control could not avoiding a lot of timeouts, resulting in very low throughput. Mar. 4 2014 T1 version 0x8003 and T2 version 0x19 Fixed a TCP bug Mar. 3 2014 T1 version 0x8002 and T2 version 0x19 Fixed some TCPIP bugs Feb. 28 2014 T1 version 0x8001 and T2 version 0x19 All known bugs fixed. Feb. 24 2014 T1 version 0x8000 and T2 version 0x19 when only one SFP port is enabled, all AMC modules' data are output by that enabled SFP port. when two SFP ports are enabled, data from AMC modules 1 thru 6 are output by the SFP port which sits above the other port on the front panel. And when all three SFP ports are enabled, data from AMC modules 1 thru 4 are output by SFP0, data from AMC modules 5 thru 8 are output by SFP1 and the rest bu SFP2. SFP assignment from top to bottom on module's front panel: SFP0 10Gbase-R link SFP1 10Gbase-R link SFP2 10Gbase-R link TTC Spartan chip default IP address 192.168.1.(254 - 2*SN) kintex chip default IP address 192.168.1.(255 - 2*SN) SFP0 default IP address 192.168.1.32 SFP1 default IP address 192.168.1.33 SFP2 default IP address 192.168.1.34 SFP IP addresses can be set to any value using backplane ipbus commands. if the first byte of the IP address is set to 0, module will be in RARP mode. TCP server port number is fixed as 0x1234 Spartan chip default IP address 192.168.1.(254 - 2*SN) kintex chip default IP address 192.168.1.(255 - 2*SN) kintex chip memory map: 0x0 read/write write: bit 0 general reset(ddr3 memory controller not encluded) write: bit 1 counter reset write: bit 5 reset ddr3 memory controller write: bit 8 Send a single TTC command write: bit 10 if bit 10 reads '0', it sends a burst of local L1A if bit 10 reads '1', it only resets it to '0' write: bit 11 sends event number reset thru TTC when in local L1A mode write: bit 12 sends orbit number reset thru TTC when in local L1A mode write: bit 26 set continous local L1A(setup with register 0x1c) read: 0 reads '1' when any of the enabled SFP ports is down read: 1 monitor buffer overflow read: 2 monitor buffer full read: 3 monitor buffer empty read: 5 TTC not ready read: 6 TTC bcnt error read: 7 TTC single bit error read: 8 TTC multi-bit error read: 9 TTC sync lost(L1A buffer overflow) read: 10 continous local L1A on(setup with register 0x1c) read: 13 L1A overflow warning read: 15 if 1, DDR memory core initialization failed read: 23 SN[8] read: bit 31-24 T1 board SN 0x1 read/write bit 31-16 read only Virtex firmware version bit 15-14 not used bit 13 if '1', enable external trigger from T3, bit 2 must be set to '1' too bit 12 if '1', TTS outputs correspond to bits 11-8 of register 0x19 instead of TTS state (note : if run bit is set, this bit is ignored) bit 11-10 not used bit 9 if '1', SFP PRBS test is enabled bit 8 if '1', TTS output is TTC signal output(you have to set bit 2 also to use this feature) bit 7 if '1', generate fake event upon receiving L1A bit 6 if '0', memory test uses 64bit PRBS. If '1', uses 32 bit sequencial numbers. bit 5 if '1', TTC command is generated by AMC13 bit 4 '1' enables memory self test bit 3 if '1', pauses event building. For debugging only bit 2 if '1', uses internally generated L1A bit 1 '1' enables DAQLSC bit 0 run mode 0x2 monitoring event control R/W read: bit 31-24 Always 0 bit 23-16 read back what was written to. bit 15-0 scale factor write: bit 23 If set to '1', bit 22-19 determine which events will be saved bit 22-19 when x"0", only saves events which evn has lower 20 bits all 0 when x"1", only saves events which evn has lower 19 bits all 0 when x"2", only saves events which evn has lower 18 bits all 0 when x"3", only saves events which evn has lower 17 bits all 0 when x"4", only saves events which evn has lower 16 bits all 0 when x"5", only saves events which evn has lower 15 bits all 0 when x"6", only saves events which evn has lower 14 bits all 0 when x"7", only saves events which evn has lower 13 bits all 0 when x"8", only saves events which evn has lower 12 bits all 0 when x"9", only saves events which evn has lower 11 bits all 0 when x"a", only saves events which evn has lower 10 bits all 0 when x"b", only saves events which evn has lower 9 bits all 0 when x"c", only saves events which evn has lower 8 bits all 0 when x"d", only saves events which evn has lower 7 bits all 0 when x"e", only saves events which evn has lower 6 bits all 0 when x"f", only saves events which evn has lower 5 bits all 0 bit 18-16 not used bit 15-0 scale factor( = contents + 1). 0x3 SFP and AMC channel enable register R/w bit 31 always '0' bit 30 '1' when SFP2 is down bit 29 '1' when SFP1 is down bit 28 '1' when SFP0 is down bit 27 '1' indicates AMC12 Link Ready bit 26 '1' indicates AMC11 Link Ready bit 25 '1' indicates AMC10 Link Ready bit 24 '1' indicates AMC9 Link Ready bit 23 '1' indicates AMC8 Link Ready bit 22 '1' indicates AMC7 Link Ready bit 21 '1' indicates AMC6 Link Ready bit 20 '1' indicates AMC5 Link Ready bit 19 '1' indicates AMC4 Link Ready bit 18 '1' indicates AMC3 Link Ready bit 17 '1' indicates AMC2 Link Ready bit 16 '1' indicates AMC1 Link Ready bit 15 '1' indicates GTX power down disabled bit 14 '1' enables SFP2 bit 13 '1' enables SFP1 bit 12 '1' enables SFP0 bit 11 '1' enables AMC12 bit 10 '1' enables AMC11 bit 9 '1' enables AMC10 bit 8 '1' enables AMC9 bit 7 '1' enables AMC8 bit 6 '1' enables AMC7 bit 5 '1' enables AMC6 bit 4 '1' enables AMC5 bit 3 '1' enables AMC4 bit 2 '1' enables AMC3 bit 1 '1' enables AMC2 bit 0 '1' enables AMC1 0x4 SFP Control and Status register R/w read: bit 31-16 always 0 bit 15 '1' disables TTS transmitter bit 14 '1' disables SFP2 transmitter bit 13 '1' disables SFP1 transmitter bit 12 '1' disables SFP0 transmitter bit 11 '1' indicates TTS TxFault bit 10 '1' indicates SFP2 TxFault bit 9 '1' indicates SFP1 TxFault bit 8 '1' indicates SFP0 TxFault bit 7 '1' indicates TTC_LOS or TTC_LOL bit 6 '1' indicates SFP2 Receiver signal lost bit 5 '1' indicates SFP1 Receiver signal lost bit 4 '1' indicates SFP0 Receiver signal lost bit 3 '1' indicates TTC/TTS SFP absent bit 2 '1' indicates SFP2 absent bit 1 '1' indicates SFP1 absent bit 0 '1' indicates SFP0 absent write: bit 31-16 not used bit 15-12 write '1' to disable the transmitter other bits not writable 0x5 AMC-AMC13 link version check and loss of sync status Read only bit 31-28 always '0' bit 27-16 '0' indicates loss of sync for corresponding AMC port bit 15-12 always '0' bit 11 '1' AMC12 link version wrong bit 10 '1' AMC11 link version wrong bit 9 '1' AMC10 link version wrong bit 8 '1' AMC9 link version wrong bit 7 '1' AMC8 link version wrong bit 6 '1' AMC7 link version wrong bit 5 '1' AMC6 link version wrong bit 4 '1' AMC5 link version wrong bit 3 '1' AMC4 link version wrong bit 2 '1' AMC3 link version wrong bit 1 '1' AMC2 link version wrong bit 0 '1' AMC1 link version wrong 0x6 AMC trigger data BC0 compensation register Read/write bit 31-28 always '0' bit 27 '1' AMC12 BC0 locked (Read only) bit 26 '1' AMC11 BC0 locked (Read only) bit 25 '1' AMC10 BC0 locked (Read only) bit 24 '1' AMC9 BC0 locked (Read only) bit 23 '1' AMC8 BC0 locked (Read only) bit 22 '1' AMC7 BC0 locked (Read only) bit 21 '1' AMC6 BC0 locked (Read only) bit 20 '1' AMC5 BC0 locked (Read only) bit 19 '1' AMC4 BC0 locked (Read only) bit 18 '1' AMC3 BC0 locked (Read only) bit 17 '1' AMC2 BC0 locked (Read only) bit 16 '1' AMC1 BC0 locked (Read only) bit 15-5 always '0' bit 4-0 set BCo compensation, default to 0x18 0x7 DCC source ID register Read/write read: bit 31-12 always '0' bit 11-0 source ID write: bit 31-12 not used bit 11-0 source ID 0x8 OrN/BCNT offset register R/W read: bit 31-20 always '0' bit 19-16 OrN offset bit 15-13 always '0' bit 12 if '1', ttc_bcntres only works once after system reset bit 11-0 BCNT offset write: bit 31-20 always '0' bit 19-16 OrN offset bit 15-13 always '0' bit 12 ttc_bcntres control bit bit 11-0 BCNT offset 0x9 calibration window register R/W read: bit 31 if '1', calibration events enabled bit 30-28 always '0' bit 27-16 calibration window upper limit(included) bit 15-12 current Laser position bit 11-0 calibration window lower limit(not included) write: bit 31 default to '1', enabling calibration events bit 30-28 always '0' bit 27-22 fixed as "110110" bit 21-16 settable part of calibration window upper limit,3519 maximum(included), default to "100110" bit 15-12 read only bit 11-6 fixed as "110110" bit 5-0 settable part of calibration window upper limit,3456 minimum(not included), default to "011101" offset 0xa memory status register lower word Read only For debugging purposes only offset 0xb memory status register high word Read only For debugging purposes only offset 0xc SDRAM page register R/W read: bit 31-10 always '0' bit 9-0 SDRAM page number write: If run bit is '1', write '0' to bit 0 of this register increments page number by 1 bit 31-10 not used bit 9-0 SDRAM page number, each page is 512kbytes size offset 0xd monitoring event word count Read only read: bit 31-17 always '0' bit 16-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable word count for AMC1-12 when only one SFP enabled word count for AMC1-6 when two SFP enabled word count for AMC1-4 when all SFP enabled offset 0xe monitored event block count Read only read: bit 31-10 always '0' bit 9-0 number of unread event blocks captured by monitor offset 0xf monitoring event word count Read only read: bit 31-17 always '0' bit 16-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable not used when only one SFP enabled word count for AMC7-12 when two SFP enabled word count for AMC5-8 when all SFP enabled offset 0x10 Read only bit 31-18 always '0' bit 17 monitor buffer available bit 16 TCP buffer available bit 14-12 ddr3 event data write port input FIFO full bit 11 always '0' bit 10-8 ddr3 event data write port ready bit 7-3 always '0' bit 2-0 event data ready in event buffer of event builders offset 0x18 payload size in 64bit words of faked AMC event R/W read: bit 31-18 always '0' bit 17-0 faked AMC payload size in 64 bit words write: bit 31-18 not used bit 17-0 payload size in 16bit words of faked HTR event(default 0x400) offset 0x19 AMC Trigger Mask register R/W read: bit 31-12 always '0' bit 11-8 TTS test pattern bit 7-0 AMC Trigger Mask write: bit 31-12 always '0' bit 11-8 TTS test pattern bit 7-0 AMC Trigger Mask offset 0x1a TTS disable register R/W read: bit 31-12 always '0' bit 11-0 if set to 1, corresponding AMC's TTS signal ignored write: bit 31-12 always '0' bit 11-0 if set to 1, corresponding AMC's TTS signal ignored offset 0x1c Local L1A control register bit 31-30 type of L1A "00": L1A per Orbit "10": L1A per Bunch crossing "11": random L1A bit 29-28 trigger rules enforced "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A generated in a burst equals its contents N+1. One L1A if all zero bit 15-0 determines L1A rates generated if in per orbit mode, it generates a L1A every N+1 orbits at BCN = 0x1f4 if in per BX mode, it generates a L1A every N+1 Bx trigger rules are applied if in random mode, it generates a L1A at 2*N/s trigger rules are applied offset 0x1d monitoring event word count Read only read: bit 31-17 always '0' bit 16-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable not used when not all SFPs are enabled word count for AMC9-12 when all SFP enabled 0x1e read only bit 31-0 FPGA DNA bits 31-0 0x1f read only bit 31-25 always reads 0 bit 24-0 FPGA DNA bits 56-32 0x20-23 TTC command register for channel 0-3 R/W bit 31-0 long TTC command bit 7-0 short TTC command(bit 0 must be 0 for short command) 0x24-27 TTC command configuration register for channel 0-3 R/W bit 31 not used bit 30 if set, channel is enabled for single TTC command bit 29 if set, channel is enabled bit 28 if set, long TTC command, otherwise short TTC command bit 27-16 starting BX of TTC command range of legal starting BX for short command is 0-0xdc6 and 0xde6-0xdeb range of legal starting BX for long command is 0-0xdac and 0xde6-0xdeb A short command takes 16 BX and a long one takes 42, starting BX for enabled channels must observe this minimum distance. AMC13 does not check the legality of the setting. bit 15-0 Orbit count prescale, prescale factor = content+1 0x28 gap begin register R/W bit 31-12 not used bit 11-0 beginning of the gap is next(not included) 0x29 gap end register R/W bit 31-12 not used bit 11-0 end of the gap(included) if 0x28 = 0x29, no gap check. Otherwise, local L1A will not occur in the gap. 0x2a OcN reset command register R/W bit 31-16 not used, always reads 0 bit 15-8 OrN reset command mask, if 1, corresponding bit(N-8) will be ignored in the matching default value is 0x17, which is the current defined command bit 7-0 OcN reset command default value is 0x28, which is the current defined command 0x2b ReSync command register R/W bit 31-16 not used bit 15-8 ReSync command mask, if 1, corresponding bit(N-8) will be ignored in the matching default value is 0x17, which is the current defined command bit 7-0 ReSync command default value is 0x48, which is the current defined command 0x2c L1A rate in Herz Read Only 0x30 V6 die temperature in unit of 0.1 degree Celsius 0x31 1.0V analog power voltage in millivolt 0x32 1.2V analog power voltage in millivolt 0x33 1.0V Vccint power voltage in millivolt 0x34 1.5V power voltage in millivolt 0x35 2.5V power voltage in millivolt 0x36 3.3V power voltage in millivolt 0x38 12V power voltage in millivolt 0x39 1.8V VccAuxGTX power voltage in millivolt 0x3a 2.0V VccAuxIO power voltage in millivolt 0x3b 0.75V DDR3_Vtt power voltage in millivolt 0x3c 0.75V DDR3_Vref power voltage in millivolt 0x3d 1.8V VccAux power voltage in millivolt 0x3e 1.0V VccBRAM power voltage in millivolt 0x40 TTC single bit error counter bits[31:0] 0x41 bit 31-16 always 0 bit 15-0 TTC single bit error counter bits[47:32] 0x42 TTC multi-bit error counter bits[31:0] 0x43 bit 31-16 always 0 bit 15-0 TTC multi-bit error counter bits[47:32] 0x44 TTC BC0 error counter bits[31:0] 0x45 bit 31-16 always 0 bit 15-0 TTC BC0 error counter bits[47:32] 0x46 L1A counter bits[31:0] 0x47 bit 31-16 always 0 bit 15-0 L1A counter bits[47:32] 0x48 run time counter bits[31:0] 0x49 bit 31-16 always 0 bit 15-0 run time counter bits[47:32] 0x4a ready time counter bits[31:0] 0x4b bit 31-16 always 0 bit 15-0 ready time counter bits[47:32] 0x4c busy time counter bits[31:0] 0x4d bit 31-16 always 0 bit 15-0 busy time counter bits[47:32] 0x4e L1A sync lost time counter bits[31:0] 0x4f bit 31-16 always 0 bit 15-0 L1A sync lost time counter bits[47:32] 0x50 L1A overflow warning time counter bits[31:0] 0x51 bit 31-16 always 0 bit 15-0 L1A overflow warning time counter bits[47:32] 0x52 L1A received when TTS state is OFW bits[31:0] 0x53 bit 31-16 always 0 bit 15-0 L1A received when TTS state is OFW bits[47:32] 0x54 L1A received when TTS state is BUSY bits[31:0] 0x55 bit 31-16 always 0 bit 15-0 L1A received when TTS state is BUSY bits[47:32] 0x56 L1A received when TTS state is LOS bits[31:0] 0x57 bit 31-16 always 0 bit 15-0 L1A received when TTS state is LOS bits[47:32] 0x100-0x11f SFP0 ROM data(first 128 bytes, little endian) 0x120-0x13f SFP1 ROM data(first 128 bytes, little endian) 0x140-0x15f SFP2 ROM data(first 128 bytes, little endian) 0x160-0x17f TTC/TTS SFP ROM data(first 128 bytes, little endian) 0x800-0x87F AMC1 counter 0x0-1 AMC accept counter 0x2-3 AMC ACK counter 0x4-5 AMC L1A abort counter 0x6-7 AMC Evn mismatch counter 0x8-9 AMC OrN mismatch counter 0xa-b AMC BcN mismatch counter 0xc-d AMC received event counter 0xe-f AMC Counter ACK counter 0x10-11 AMC Resend counter 0x12-13 AMC event bad EventLength counter 0x14-15 AMC event trailer Evn mismatch error counter 0x16-17 AMC event buffer almost full time counter 0x18-19 total word counter at link input 0x1a-1b header word counter at link input 0x1c-1d trailer word counter at link input 0x1e-1f event number error counter at link input 0x20 AMC DAQ_Link ststus bit 31-16 Always 0 bit 15 FIFO_ovf bit 14-13 Always 0 bit 12-8 EventStatus_ra bit 7-6 Always 0 bit 4-0 EventStatus_wa 0x22 AMC DAQ_Link ststus bit 31-15 Always 0 bit 14-0 DataBuf_wa 0x24 AMC DAQ_Link ststus bit 31-15 Always 0 bit 14-0 DataBuf_ra 0x26 AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_wa 0x28 AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_ra 0x2a AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 AMCinfo_wa 0x2e AMC DAQ_Link ststus bit 31-9 Always 0 bit 8-4 EventCnt bit 3-2 ReSendQue_a bit 1 AlmostFull bit 0 dataFIFO_Empty 0x30-31 L1abort because of bad SEQ counter 0x32-33 L1abort because of bad CRC counter 0x34-35 L1abort because of bad frame structure counter 0x36-37 L1abort because of illegal K word counter 0x38-39 L1abort because of ACKNUM queue full counter 0x3a-3b short event at input counter 0x3c-3d padding word for short event counter 0x40-41 total word counter 0x42-43 single bit error counter 0x44-45 multi-bit error counter 0x46-47 BC0 mismatch error counter 0x48-49 bcnt mismatch error counter 0x4a-4b ReSend counter 0x4c-4d Accept counter 0x4e-4f Counter Accept counter 0x50-51 ACK counter 0x52-53 Receive Event counter 0x54-55 Read Event counter 0x56-57 Data abort counter 0x58-59 Counter abort counter 0x5a-5b abort due to ACKNUM_full counter 0x5c-5d abort due to EventBuf_full counter 0x5e-5f abort due to EventInfo_full counter 0x60-61 abort due to bad SEQ counter 0x62-63 abort due to bad CRC counter 0x64-65 abort due to bad frame counter 0x66-67 abort due to bad K character counter 0x68-69 BUSY time counter(reserved) 0x6a-6b AMC event EVN mismatch counter 0x6c-6d AMC event BCN mismatch counter 0x6e-6f AMC event OCN mismatch counter 0x70-71 bad eventlength counter 0x72-73 Block counter 0x76-77 TTC update counter 0x78-79 bad AMC event CRC counter 0x7a-7b TTS error counter 0x7c-7d TTS sync lost counter 0x7e-7f TTS disconnect counter 0x880-0x8FF AMC2 counter 0x900-0x97F AMC3 counter 0x980-0x9FF AMC4 counter 0xa00-0xa7F AMC5 counter 0xa80-0xaFF AMC6 counter 0xb00-0xb7F AMC7 counter 0xb80-0xbFF AMC8 counter 0xc00-0xc7F AMC9 counter 0xc80-0xcFF AMC10 counter 0xd00-0xd7F AMC11 counter 0xd80-0xdFF AMC12 counter 0xe00 EventInfo for AMC1 0xe01 EventInfo for AMC2 0xe02 EventInfo for AMC3 0xe03 EventInfo for AMC4 0xe04 EventInfo for AMC5 0xe05 EventInfo for AMC6 0xe06 EventInfo for AMC7 0xe07 EventInfo for AMC8 0xe08 EventInfo for AMC9 0xe09 EventInfo for AMC10 0xe0a EventInfo for AMC11 0xe0b EventInfo for AMC12 0xe0c AMC_if status bit 31-28 Always 0 bit 27-16 '1' if corresponding AMC_LINK buffer is full bit 15 '1' if any AMC_LINK buffer is full bit 14 '1' if qpll for AMC9-12 not locked bit 13 '1' if qpll for AMC5-8 not locked bit 12 '1' if qpll for AMC1-4 not locked bit 11-0 EventInfo_dav 0xe0d AMC_TTC_status bit 31-28 Always 0 bit 27-16 1 if corresponding AMC enabled and TTC locked bit 15-12 Always 0 bit 11-0 1 if corresponding AMC enabled and BC0 locked 0xe0e AMC_if status bit 31-28 Always 0 bit 27-16 1 if corresponding AMC txfsmresetdone set bit 15-11 Always 0 bit 11-0 1 if corresponding AMC rxfsmresetdone set 0xe10 AMC_if status bit 31-25 Always 0 bit 24-16 evn_ra bit 15-9 Always 0 bit 8-0 evn_wa 0xe11 AMC_if status bit 31-24 Always 0 bit 23-0 evn 0xe12 AMC_if status bit 31-25 Always 0 bit 24-16 CDF_ra bit 15-9 Always 0 bit 8-0 CDF_wa 0xe13 AMC_if status bit 31-23 Always 0 bit 22 mon_buf_avl bit 21 init_bldr bit 20 evn_empty bit 19 eventInfo_avl bit 18-16 bldr_fifo_full bit 15 ec_CDF_ra bit 14-12 AMC_wc_we bit 11 sel_CDF bit 10-8 AMC_header_we bit 7-6 sel_evn bit 5-4 Always 0 bit 3-0 sel_AMC 0xe14 AMC_if status bit 31-0 fake_word_cnt 0xe15 AMC_if status bit 31-0 fake_header_cnt 0xe16 AMC_if status bit 31-0 fake_evt_cnt 0xe17 AMC_if status bit 31-0 fake_empty_cnt 0xe18 TTC status 0xe19 TTC status 0xe1a AMC_if status read only TTS is encoded from MSB as disconnected, error, sync lost, busy and overflow warning bit 31 AMC4 has been in disconnected state bit 30 AMC4 has been in error state bit 29 AMC4 has been in out of sync state bit 28-24 AMC4 TTS_encoded bit 23 AMC3 has been in disconnected state bit 22 AMC3 has been in error state bit 21 AMC3 has been in out of sync state bit 20-16 AMC3 TTS_encoded bit 15 AMC3 has been in disconnected state bit 14 AMC3 has been in error state bit 13 AMC2 has been in out of sync state bit 12-8 AMC2 TTS_encoded bit 7 AMC1 has been in disconnected state bit 6 AMC1 has been in error state bit 5 AMC1 has been in out of sync state bit 4-0 AMC1 TTS_encoded 0xe1b AMC_if status read only TTS is encoded from MSB as disconnected, error, sync lost, busy and overflow warning bit 31 AMC8 has been in disconnected state bit 30 AMC8 has been in error state bit 29 AMC8 has been in out of sync state bit 28-24 AMC8 TTS_encoded bit 23 AMC7 has been in disconnected state bit 22 AMC7 has been in error state bit 21 AMC7 has been in out of sync state bit 20-16 AMC7 TTS_encoded bit 15 AMC6 has been in disconnected state bit 14 AMC6 has been in error state bit 13 AMC6 has been in out of sync state bit 12-8 AMC6 TTS_encoded bit 7 AMC5 has been in disconnected state bit 6 AMC5 has been in error state bit 5 AMC5 has been in out of sync state bit 4-0 AMC5 TTS_encoded 0xe1c AMC_if status read only TTS is encoded from MSB as disconnected, error, sync lost, busy and overflow warning bit 31 AMC12 has been in disconnected state bit 30 AMC12 has been in error state bit 29 AMC12 has been in out of sync state bit 28-24 AMC12 TTS_encoded bit 23 AMC11 has been in disconnected state bit 22 AMC11 has been in error state bit 21 AMC11 has been in out of sync state bit 20-16 AMC11 TTS_encoded bit 15 AMC10 has been in disconnected state bit 14 AMC10 has been in error state bit 13 AMC10 has been in out of sync state bit 12-8 AMC10 TTS_encoded bit 7 AMC9 has been in disconnected state bit 6 AMC9 has been in error state bit 5 AMC9 has been in out of sync state bit 4-0 AMC9 TTS_encoded 0xe20-0xe2b AMC eventCRC error for 12 AMC slot (read only) bit 31-0 AMC eventCRC error(indicates backplane link problem) 0xe30-0xe3b total event word of each AMC modul read by event builder(only 6 LSBs are kept) 0xe40-e4f AMC1 status 0xe40 bit 31-30 Always 0 bit 29-18 EventBuf_ra bit 17-16 Always 0 bit 15-14 Always 0 bit 13-0 EventBuf_wa 0xe41 bit 31-26 Always 0 bit 27-16 L1Ainfo_ra bit 15-10 Always 0 bit 9-0 L1Ainfo_wa 0xe42 bit 31-30 ReSendQue_a bit 29-28 rfifo_a bit 27-26 ACKNUM_a bit 25 reset_sync(3) bit 24 AMCRdy bit 23 TxResetDone bit 22 RxResetDone bit 21 RxPllLock bit 20 InitLink bit 19-16 TxState bit 15 AMC_L1A_full bit 14 Always 0 bit 13-8 AMC_L1A bit 7-0 L1Ainfo_wap 0xe43 bit 31-16 Always 0 bit 15-12 EventInfo_a bit 11-7 Always 0 bit 6 AMCRdy bit 5 Always 0 bit 4 got_AMC_BC0 bit 3 TTC_lock bit 2 BC0_lock bit 1 EventInfoRdDoneToggle bit 0 EventInfoToggle 0xe44 bit 31 block32k bit 30-20 Always 0 bit 19-0 EventWC 0xe45 bit 31-16 always 0 bit 15-0 AMC_DATA_RdEn word counter 0xe47 bit 31-4 always 0 bit 3-0 TTS received from AMC 0xe48 bit 31-24 always 0 bit 23-16 AMC13 link version bit 15-8 always 0 bit 7-0 AMC link version 0xe49 Recording the first mismatch of EvN,BcN or OrN bit 31-28 Link TTS bit 27 if 0, OrN mismatch bit 26 if 0, BcN mismatch bit 25 if 0, EvN mismatch bit 24-0 event number 0xe4a AMC_DATA_FIFO WRERR bit 31-8 Always 0 bit 7-0 WRERR for eight FIFOs 0xe4b AMC_DATA_FIFO RDERR bit 31-8 Always 0 bit 7-0 RDERR for eight FIFOs 0xe50-eff status for AMC2 -AMC12 0x1000-0x13ff SFP0 registers offset 0x200 SND.UNA offset 0x201 SND.NXT offset 0x202 SND.WND offset 0x203 CWND offset 0x204 SND.SEQ offset 0x205 SND.ACK offset 0x206 SEG.SEQ offset 0x207 SEG.ACK offset 0x208 ReTx.SEQ offset 0x209 TSclock offset 0x20a ReTxQueue_DOB offset 0x20b bit 15-0 MSS offset 0x20c bit 31-16 RTT, bit 15-0 RTO offset 0x20d bit 31 ReTxQueue full bit 23-16 ReTxQueue_wp bit 7-0 ReTxQueue_rp offset 0x20e SND.UNA + min(SND.WND,CWND) - 1 offset 0x20f EMACclientTack counter offset 0x210 SFP0 output data rate in byte/s offset 0x211 dead time(divide by 10^6, time in waiting for send window) offset 0x212 ISS offset 0x213 IRS 0x1400-0x17ff SFP1 registers 0x1800-0x1bff SFP2 registers 0x1c00-0x1fff TCPIP interface general registers 0x1c0d event cmsCRC error counter for event builder 0 0x1c0e event cmsCRC error counter for event builder 1 0x1c0f event cmsCRC error counter for event builder 2 0x1c1c SFP0 IP address register R/W (default 192.168.1.32) 0x1c1d SFP1 IP address register R/W (default 192.168.1.33) 0x1c1e SFP2 IP address register R/W (default 192.168.1.34) 0x1c1f congistion window upper limit register R/W (default 0x3fffffff) 0x20000-0x3ffff memory read window 0x8000000-0xfffffff full memory read/write access.(write disabled when bit 0 of reg 0x1 is set. spartan chip memory map: 0x0 read bit 31-24 always reads 0 bit 23-16 SN number bit 15-0 T2 firmware version write bit 8 start both S6 and V6 reconfiguration bit 4 start V6 reconfiguration bit 3 clear TTC command filter list bit 2 clear TTC command history bit 0 general reset 0x1 read/write read bit 31-16 always reads 0 bit 0 FLASH busy write sends data stored in FLASH wbuf to FLASH memory chip bit 8-0 specifies number of (clocks/8 -1) to be sent to the FLASH memory (depends on the type of the FLASH command and number of bytes to be read or written) 0x2 read only (reads back what was written to V6 chip 0x3) bit 31-12 always reads 0 bit 11-0 enables TTC clock and data to AMC modules 0x3 read only bit 31 if '1', kintex chip INIT_B is low bit 30 if '1', kintex chip DONE is low bit 29 if '1', T1 is not ready bit 28 if '1', RARP enabled bit 27 if '1', FPGA_PROG_B of T1 Kintex FPGA is asserted low bit 26 if '1', FPGA_PROG_B of T1 Kintex FPGA is asserted low bit 25-24 always reads 0 bit 23-0 configuration data CRC 0x4 read only bit 31-16 always reads 0 bit 15-0 TTC event number of last received L1A 0x5 read only bit 31-12 always reads 0 bit 11-0 TTC Bcnt number of last received L1A 0x6 read only bit 31-0 TTC orbit count number of last received L1A 0x7 read only bit 31-8 always reads 0 bit 7-0 TTC Bcnt error counter 0x8 read only bit 31-8 always reads 0 bit 7-0 TTC single bit error counter(stops counting when reaching 0xff) 0x9 read only bit 31-8 always reads 0 bit 7-0 TTC multi-bit error counter(stops counting when reaching 0xff) 0xa read only bit 31-16 L1A counter bit 15-0 BC0 counter, should be running all the time 0xb read only bit 31-28 always reads 0 bit 27-16 bcnt, should be running all the time bit 15-0 always reads 0 0xc read only bit 31-20 always reads 0 bit 19-0 TTC clock frequency divided by 50 0xd read/write bit 31 if 1, TTC command history enabled bit 30 if 1, TTC command filter enabled bit 29 TTC command history has at least 512 entries(read only) bit 28-25 not used, always reads 0 bit 24-16 write pointer of TTC command history(read only) if bit 29 is 0, this is the number of entries in the TTC command history. If bit 29 is 1, this points to the oldest entry of the history bit 15-12 not used, always reads 0 bit 11-0 enables TTC clock and data to AMC modules 0xe read only bit 31-0 FPGA DNA bits 31-0 0xf read only bit 31-25 always reads 0 bit 24-0 FPGA DNA bits 56-32 0x10 read only bit 31-16 always reads 0 bit 15-0 TTC reset event number command counter 0x11 TTC command counter for TTC command = 0x1 read only bit 31-16 always reads 0 bit 15-0 TTC command counter 0x12-0x1f TTC command counter for TTC command = 0x2 thru 0xf read only bit 31-16 always reads 0 bit 15-0 TTC command counter 0x20-0x2f TTC excluded command list (read/write) bit 31-17 always reads 0 bit 16 if 1, TTC command specified in bit 7-0 is excluded bit 15-8 TTC command mask, if 1, corresponding bit(N-8) of the TTC command will be ignored in the matching bit 7-0 TTC command 0x30 OrN reset command register R/W bit 31-16 not used, always reads 0 bit 15-8 OrN reset command mask, if 1, corresponding bit(N-8) will be ignored in the matching default value is 0x17, which is the current defined command bit 7-0 OcN reset command default value is 0x28, which is the current defined command 0x800-0xfff TTC command history (read only) each entry is constituted of four 32 bit words: bit 7-0 of the first word is the TTC command bit 31-0 of the second word is OrN bit 11-0 of the third word is BcN bit 23-0 of the fourth word is EvN 0x1000 thru 0x107f read/write FLASH write buffer always write FLASH command(including FLASH address if any) to address 0x1000 for page write command, attach the write data starting at address 0x1001 you can read back what you have writen to the write buffer. 0x1080 thru 0x10ff read only FLASH read buffer you read whatever data are returned from the FLASH memory here initial test of AMC13XG on the special test stand: Open CHIPSCOPE(v14.5 or later) and loading project file D:\vproject\testAMC\testAMC.runs\impl_3\testAMC.cpj Configure T2 and then T1 with files amc13_t2test.bit and amc13_t1.bit in D:\vproject\testAMC\testAMC.runs\impl_3. Open VIO consoles of MYVIO0 and MYVIO2, set prbssel to 0x111111111111 and amc1 thru amc12 in MYVIO0 would get some counts and then stay unchanging. If any channel is counting continuously, the corresponging AMC Tx/Rx has a proprblem. amc_en in the same window should read 0xfff. Connecting TTC signal to the bottom SFP and you should be able to see TTC clock signals on the terminating resistors on the test stand. instructions about internal TTC clock and L1A generation To use internally generated TTC clock, use an optical fiber to loop back the bottom SFP transceiver optical signal. Bit 8 of register 1 must be set to '1' To use internally generated L1A, bit 2 of register 1 must be set to '1' To send a predetermined number of L1A, write 1 to bit 10 of register 0 To send continous L1A, write 1 to bit 26 of register 0, to termainate it, write 1 to bit 10 of register 0. write 1 of bit 0 of register 0 will also terminate it. when in internal L1A mode, you can write 1 to bit 11 of register 0 to send an reset event number command through TTC, or write 1 to bit 12 to reset the orbit count TTC command. You can send both at the same time. A general reset, i.e. write 1 to bit 0 of register 0 will reset both too among other things. register 0x1c is used to configure internal L1A generation: N is contents of bit 15-0 bit 31 and 30 is used to chose the type of L1A: if "00", L1A is generated every N+1 orbits at BX = 500 if "10", L1A is generated every N+1 BX, trigger rules apply when N < 63 if "11", L1A is generated at random spacing, trigger rules apply. The average frequency is 2N Bit 29-28 determines how many trigger rules are enforced: "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A sent in a burst is its countents + 1 To run memory test, first write 0 to register 0x1, then write 1 to register0x0, write either 0x10 or 0x50 to register 0x1 to start the test.