May 13 2014 T1 version 0x201 and T2 version 0x20 a bug in a AMC_LINK data FIFO fixed. The bug caused unreliable bit 63 of AMC data words. Apr. 30 2014 T1 version 0x200 and T2 version 0x20 Starting fromv0x200, event built uses new data format(multiblock event) Biggest change in T1's memory map is that the monitored event window has been moved from 0x4000 to 0x20000 and the window size changed from 0x4000 to 0x20000 32bit words The memory page address has reduced from 13 bits to 10 bits. Another function added is that if MMC sets IP address as all 0, RARP is enabled(T1 and T2 must be set independently) AMC modules TTS signal can be individually disabled by writing to register 0x1a(when it is not used or malfunctions) Apr. 8 2014 T1 version 0x107 and T2 version 0x1e bit 30 of register 0xd added in 0x1d removed. A bug with SPI in T2 with s6lx45t fixed. Mar. 31 2014 T1 version 0x107 and T2 version 0x1d added bit 30 to register 0xd, if set, TTC clock source comes from T3 T2 version 0x1d exists only for T2 with s6lx45t Mar. 27 2014 T1 version 0x107 and T2 version 0x1c ipbus interface code modified. transactor_sm.vhd changed back to module come with ipbus_2_0_v1.r27848 Mar. 19 2014 T1 version 0x106 and T2 version 0x1b problem detected, replace transcator_sm.vhd with the home-modified version Mar. 18 2014 T1 version 0x105 and T2 version 0x1a ipbus firmware updated to ipbus_2_0_v1.r27848 Feb. 26 2014 T1 version 0x104 and T2 version 0x19 A bug in memory write fixed. Feb. 13 2014 T1 version 0x103 and T2 version 0x19 A bug fix in AMC_if module and an improved ddr_rport module. Jan. 6 2014 T1 version 0x102 and T2 version 0x19 DAQLSC_if module modified to make transition to 10Gb/s SFP much easier Dec. 23 2013 T1 version 0x101 and T2 version 0x19 Finally all bugs in DAQLSC(0x100) and DAQLDC(0xff) have been fixed. Could run different settings of DAQLSC and DAQLDC without errors noticed. Dec. 12 2013 T1 version 0x100 and T2 version 0x19 A bug in the SPI interface since T2 version 0x17 causes SPI data always to be written to both T1 and T2 and the SPI read data is always from T2. Modules with T2 version 0x17 and 0x18 must be updated to 0x19 in order to get correct IP address. Dec. 8 2013 T1 version 0x100 and T2 version 0x18 Starting from T1 version 0x100, the DAQ link is implemented for the Front panel SFP0, SFP1 and SFP2, which runs at bit rate of 5.0Gb/s as with AMC13 The event builder has also been changed so that when only one SFP port is enabled, all AMC modules' data are output by that enabled SFP port. when two SFP ports are enabled, data from AMC modules 1 thru 6 are output by the SFP port which sits above the other port on the front panel. And when all three SFP ports are enabled, data from AMC modules 1 thru 4 are output by SFP0, data from AMC modules 5 thru 8 are output by SFP1 and the rest bu SFP2. SFP assignment from top to bottom on module's front panel: SFP0 DAQLSC link SFP1 DAQLSC link SFP2 DAQLSC link TTC Spartan chip default IP address 192.168.1.(254 - 2*SN) kintex chip default IP address 192.168.1.(255 - 2*SN) kintex chip memory map: 0x0 read/write write: bit 0 general reset(ddr3 memory controller not encluded) write: bit 1 counter reset write: bit 5 reset ddr3 memory controller write: bit 10 if bit 10 reads '0', it sends a burst of local L1A if bit 10 reads '1', it only resets it to '0' write: bit 11 sends event number reset thru TTC when in local L1A mode write: bit 12 sends orbut number reset thru TTC when in local L1A mode write: bit 26 set continous local L1A(setup with register 0x1c) read: 0 reads '1' when any of the enabled SFP ports is down read: 1 monitor buffer overflow read: 2 monitor buffer full read: 3 monitor buffer empty read: 5 TTC not ready read: 6 TTC bcnt error read: 7 TTC single bit error read: 8 TTC multi-bit error read: 9 TTC sync lost(L1A buffer overflow) read: 10 continous local L1A on(setup with register 0x1c) read: 13 L1A overflow warning read: 15 if 0, DDR memory reset done read: bit 31-24 T1 board SN 0x1 read/write bit 31-16 read only Virtex firmware version bit 15 not used bit 14 if '1', monitor buffer full will stop event builder bit 13 if '1', send all data to downstream when ttc reset is received. if '0', flush all data when ttc reset is received. bit 12 if '1', TTS outputs correspond to bits 3-0 of register 0x19 instead of TTS state when run bit(bit 0) is '1', this bit will be forced to '0' bit 11-9 not used bit 8 if '1', TTS output is TTC signal output(you have to set bit 2 also to use this feature) bit 7 if '1', generate fake event upon receiving L1A bit 6 if '0', memory test uses 64bit PRBS. If '1', uses 32 bit sequencial numbers. bit 5 '1' enables non-standard TTCrx broadcast commands bit 4 '1' enables memory self test bit 3 if '1', pauses event building. For debugging only bit 2 if '1', uses internally generated L1A bit 1 '1' enables DAQLSC bit 0 run mode 0x2 monitoring event control R/W read: bit 31-24 Always 0 bit 23-16 read back what was written to. bit 15-0 scale factor write: bit 23 If set to '1', bit 22-19 determine which events will be saved bit 22-19 when x"0", only saves events which evn has lower 20 bits all 0 when x"1", only saves events which evn has lower 19 bits all 0 when x"2", only saves events which evn has lower 18 bits all 0 when x"3", only saves events which evn has lower 17 bits all 0 when x"4", only saves events which evn has lower 16 bits all 0 when x"5", only saves events which evn has lower 15 bits all 0 when x"6", only saves events which evn has lower 14 bits all 0 when x"7", only saves events which evn has lower 13 bits all 0 when x"8", only saves events which evn has lower 12 bits all 0 when x"9", only saves events which evn has lower 11 bits all 0 when x"a", only saves events which evn has lower 10 bits all 0 when x"b", only saves events which evn has lower 9 bits all 0 when x"c", only saves events which evn has lower 8 bits all 0 when x"d", only saves events which evn has lower 7 bits all 0 when x"e", only saves events which evn has lower 6 bits all 0 when x"f", only saves events which evn has lower 5 bits all 0 bit 18-16 not used bit 15-0 scale factor( = contents + 1). 0x3 HTR channel enable register R/w read: bit 31 always '0' bit 30 '1' when DAQLSC of SFP2 is down bit 29 '1' when DAQLSC of SFP1 is down bit 28 '1' when DAQLSC of SFP0 is down bit 27 '1' indicates AMC12 Link Ready bit 26 '1' indicates AMC11 Link Ready bit 25 '1' indicates AMC10 Link Ready bit 24 '1' indicates AMC9 Link Ready bit 23 '1' indicates AMC8 Link Ready bit 22 '1' indicates AMC7 Link Ready bit 21 '1' indicates AMC6 Link Ready bit 20 '1' indicates AMC5 Link Ready bit 19 '1' indicates AMC4 Link Ready bit 18 '1' indicates AMC3 Link Ready bit 17 '1' indicates AMC2 Link Ready bit 16 '1' indicates AMC1 Link Ready bit 15 always '0' bit 14 '1' enables SFP2 bit 13 '1' enables SFP1 bit 12 '1' enables SFP0 bit 11 '1' enables AMC12 bit 10 '1' enables AMC11 bit 9 '1' enables AMC10 bit 8 '1' enables AMC9 bit 7 '1' enables AMC8 bit 6 '1' enables AMC7 bit 5 '1' enables AMC6 bit 4 '1' enables AMC5 bit 3 '1' enables AMC4 bit 2 '1' enables AMC3 bit 1 '1' enables AMC2 bit 0 '1' enables AMC1 0x4 SFP Control and Status register R/w read: bit 31-16 SLINK ID(bits 15-14 always '0') bit 15 '1' disables TTS transmitter bit 14 '1' disables SFP2 transmitter bit 13 '1' disables SFP1 transmitter bit 12 '1' disables SFP0 transmitter bit 11 '1' indicates TTS TxFault bit 10 '1' indicates SFP2 TxFault bit 9 '1' indicates SFP1 TxFault bit 8 '1' indicates SFP0 TxFault bit 7 '1' indicates TTC_LOS or TTC_LOL bit 6 '1' indicates SFP2 Receiver signal lost bit 5 '1' indicates SFP1 Receiver signal lost bit 4 '1' indicates SFP0 Receiver signal lost bit 3 '1' indicates TTC/TTS SFP absent bit 2 '1' indicates SFP2 absent bit 1 '1' indicates SFP1 absent bit 0 '1' indicates SFP0 absent write: bit 31-16 SLINK ID(bits 15-14 always '0') bit 15-12 write '1' to disable the transmitter other bits not writable 0x5 HTR-AMC link version check and loss of sync status Read only bit 31-28 always '0' bit 27-16 '0' indicates loss of sync for corresponding AMC port bit 15-12 always '0' bit 11 '1' AMC12 link version wrong bit 10 '1' AMC11 link version wrong bit 9 '1' AMC10 link version wrong bit 8 '1' AMC9 link version wrong bit 7 '1' AMC8 link version wrong bit 6 '1' AMC7 link version wrong bit 5 '1' AMC6 link version wrong bit 4 '1' AMC5 link version wrong bit 3 '1' AMC4 link version wrong bit 2 '1' AMC3 link version wrong bit 1 '1' AMC2 link version wrong bit 0 '1' AMC1 link version wrong 0x6 AMC trigger data BC0 compensation register Read/write bit 31-28 always '0' bit 27 '1' AMC12 BC0 locked (Read only) bit 26 '1' AMC11 BC0 locked (Read only) bit 25 '1' AMC10 BC0 locked (Read only) bit 24 '1' AMC9 BC0 locked (Read only) bit 23 '1' AMC8 BC0 locked (Read only) bit 22 '1' AMC7 BC0 locked (Read only) bit 21 '1' AMC6 BC0 locked (Read only) bit 20 '1' AMC5 BC0 locked (Read only) bit 19 '1' AMC4 BC0 locked (Read only) bit 18 '1' AMC3 BC0 locked (Read only) bit 17 '1' AMC2 BC0 locked (Read only) bit 16 '1' AMC1 BC0 locked (Read only) bit 15-5 always '0' bit 4-0 set BCo compensation, default to 0x18 0x7 DCC source ID register Read/write read: bit 31-24 always '0' bit 23-0 source ID write: bit 31-24 not used bit 23-20 evt_ty bit 19-12 evt_stat bit 11-0 source ID 0x8 OrN/BCNT offset register R/W read: bit 31-20 always '0' bit 19-16 OrN offset bit 15-13 always '0' bit 12 if '1', ttc_bcntres only works once after system reset bit 11-0 BCNT offset write: bit 31-20 always '0' bit 19-16 OrN offset bit 15-13 always '0' bit 12 ttc_bcntres control bit bit 11-0 BCNT offset 0x9 calibration window register R/W read: bit 31 if '1', calibration events enabled bit 30-28 always '0' bit 27-16 calibration window upper limit(included) bit 15-12 current Laser position bit 11-0 calibration window lower limit(not included) write: bit 31 default to '1', enabling calibration events bit 30-28 always '0' bit 27-22 fixed as "110110" bit 21-16 settable part of calibration window upper limit,3519 maximum(included), default to "100110" bit 15-12 read only bit 11-6 fixed as "110110" bit 5-0 settable part of calibration window upper limit,3456 minimum(not included), default to "011101" offset 0xa memory status register lower word Read only For debugging purposes only offset 0xb memory status register high word Read only For debugging purposes only bit 10-0 SDRAM write page address offset 0xc SDRAM page register R/W read: bit 31-13 always '0' bit 12-0 SDRAM page number write: If run bit is '1', write '0' to bit 0 of this register increments page number by 1 bit 31-13 not used bit 12-0 SDRAM page number, each page is 64kbytes size In catch mode, only one event can be catched offset 0xd monitoring event word count Read only read: bit 31 always '0' bit 30-24 all 0 if not in catch mode, otherwise gives the number of events stored after the bad event bit 23-16 all 0 if not in catch mode, otherwise gives the type of error of the bad event bit 15-14 always '0' bit 13-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable word count for AMC1-12 when only one SFP enabled word count for AMC1-6 when two SFP enabled word count for AMC1-4 when all SFP enabled offset 0xe monitored event count Read only read: bit 31-12 always '0' bit 11-0 number of unread events captured by monitor offset 0xf HTR CRC check error count of built events Read only offset 0x10 Read only bit 31-18 always '0' bit 17 monitor buffer available bit 16 TCP buffer available bit 14-12 ddr3 event data write port input FIFO full bit 11 always '0' bit 10-8 ddr3 event data write port ready bit 7 always '0' bit 6-4 event size in event buffer of event builders bit 3 always '0' bit 2-0 event data ready in event buffer of event builders offset 0x18 payload size in 64bit words of faked HTR event R/W read: bit 31-18 always '0' bit 17-0 payload size write: bit 31-18 not used bit 17-0 payload size in 16bit words of faked HTR event(default 0x400) offset 0x19 AMC Trigger Mask register R/W read: bit 31-8 always '0' bit 7-0 AMC Trigger Mask write: bit 31-8 always '0' bit 7-0 AMC Trigger Mask offset 0x1a TTS disable register R/W read: bit 31-12 always '0' bit 11-0 if set to 1, corresponding AMC's TTS signal ignored write: bit 31-8 always '0' bit 7-0 HTR Trigger Mask offset 0x1c Local L1A control register bit 31-30 type of L1A "00": L1A per Orbit "10": L1A per Bunch crossing "11": random L1A bit 29-28 trigger rules enforced "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A generated in a burst equals its contents N+1. One L1A if all zero bit 15-0 determines L1A rates generated if in per orbit mode, it generates a L1A every N+1 orbits at BCN = 0x1f4 if in per BX mode, it generates a L1A every N+1 Bx trigger rules are applied if in random mode, it generates a L1A at 2*N/s trigger rules are applied 0x1d read only monitored event word count bit 31-16 word count for AMC9-12 when all SFP enabled bit 15-0 word count for AMC5-8 when all SFP enabled or word count for AMC7-12 when two SFP enabled 0x1e read only bit 31-0 FPGA DNA bits 31-0 0x1f read only bit 31-25 always reads 0 bit 24-0 FPGA DNA bits 56-32 0x30 V6 die temperature in unit of 0.1 degree Celsius 0x31 1.0V analog power voltage in millivolt 0x32 1.2V analog power voltage in millivolt 0x33 1.0V Vccint power voltage in millivolt 0x34 1.5V power voltage in millivolt 0x35 2.5V power voltage in millivolt 0x36 3.3V power voltage in millivolt 0x38 12V power voltage in millivolt 0x39 1.8V VccAuxGTX power voltage in millivolt 0x3a 2.0V VccAuxIO power voltage in millivolt 0x3b 0.75V DDR3_Vtt power voltage in millivolt 0x3c 0.75V DDR3_Vref power voltage in millivolt 0x3d 1.8V VccAux power voltage in millivolt 0x3e 1.0V VccBRAM power voltage in millivolt 0x40 TTC single bit error counter bits[31:0] 0x41 bit 31-16 always 0 bit 15-0 TTC single bit error counter bits[47:32] 0x42 TTC multi-bit error counter bits[31:0] 0x43 bit 31-16 always 0 bit 15-0 TTC multi-bit error counter bits[47:32] 0x44 TTC BC0 error counter bits[31:0] 0x45 bit 31-16 always 0 bit 15-0 TTC BC0 error counter bits[47:32] 0x46 L1A counter bits[31:0] 0x47 bit 31-16 always 0 bit 15-0 L1A counter bits[47:32] 0x48 run time counter bits[31:0] 0x49 bit 31-16 always 0 bit 15-0 run time counter bits[47:32] 0x4a ready time counter bits[31:0] 0x4b bit 31-16 always 0 bit 15-0 ready time counter bits[47:32] 0x4c busy time counter bits[31:0] 0x4d bit 31-16 always 0 bit 15-0 busy time counter bits[47:32] 0x4e L1A sync lost time counter bits[31:0] 0x4f bit 31-16 always 0 bit 15-0 L1A sync lost time counter bits[47:32] 0x50 L1A overflow warning time counter bits[31:0] 0x51 bit 31-16 always 0 bit 15-0 L1A overflow warning time counter bits[47:32] 0x56 total monitored event counter bits[31:0] 0x57 bit 31-16 always 0 bit 15-0 total monitored event counter bits[47:32] 0x80-0x97 DAQLSC counter and status registers Read Only 0x80 SFP0 ack count 0x81 SFP0 packet count 0x82 SFP0 retransmit count 0x83 SFP0 event count 0x85 SFP0 sync loss count 0x86 SFP0 DAQLSC status bit 31-0 0x87 SFP0 DAQLSC status bit 63-32 0x88 SFP1 ack count 0x89 SFP1 packet count 0x8a SFP1 retransmit count 0x8b SFP1 event count 0x8d SFP1 sync loss count 0x8e SFP1 DAQLSC status bit 31-0 0x8f SFP1 DAQLSC status bit 63-32 0x90 SFP2 ack count 0x91 SFP2 packet count 0x92 SFP2 retransmit count 0x93 SFP2 event count 0x95 SFP2 sync loss count 0x96 SFP2 DAQLSC status bit 31-0 0x97 SFP2 DAQLSC status bit 63-32 0xa0-0xae DAQLSC_if status and counters Read Only 0xa1 bit 12-0 Monitored buffer count 0xa2 bit 27-16 next monitor buffer for event builder 1 bit 11-0 next monitor buffer for event builder 0 0xa3 bit 27-16 next monitor buffer for all event builder bit 11-0 next monitor buffer for event builder 2 0xa4 bit 31-23 Always '0' bit 22-20 header bit 19 '0' bit 18-16 LinkFull_n bit 15 '0' bit 14-12 ReadBusy bit 11 '0' bit 10-8 evt_data_rdy bit 7 '0' bit 6-4 wport_FIFO_full bit 3 '0' bit 2-0 wport_rdy 0xa5 event count for SFP0 0xa6 event count for SFP1 0xa7 event count for SFP2 0xa8 word count for SFP0 0xa9 word count for SFP1 0xaa word count for SFP2 0xab event count for event builder 0 0xac event count for event builder 1 0xad event count for event builder 2 0xae monitored event count 0x100-0x11f SFP0 ROM data(first 128 bytes, little endian) 0x120-0x13f SFP1 ROM data(first 128 bytes, little endian) 0x140-0x15f SFP2 ROM data(first 128 bytes, little endian) 0x160-0x17f TTC/TTS SFP ROM data(first 128 bytes, little endian) 0x800-0x87F AMC1 counter 0x0-1 AMC accept counter 0x2-3 AMC ACK counter 0x4-5 AMC L1A abort counter 0x6-7 AMC Evn mismatch counter 0x8-9 AMC OrN mismatch counter 0xa-b AMC BcN mismatch counter 0xc-d AMC received event counter 0xe-f AMC Counter ACK counter 0x10-11 AMC Resend counter 0x12-13 AMC event bad EventLength counter 0x14-15 AMC event trailer Evn mismatch error counter 0x16-17 AMC event buffer almost full time counter 0x18-19 total word counter at link input 0x1a-1b header word counter at link input 0x1c-1d trailer word counter at link input 0x1e-1f event number error counter at link input 0x20 AMC DAQ_Link ststus bit 31-16 Always 0 bit 15 FIFO_ovf bit 14-13 Always 0 bit 12-8 EventStatus_ra bit 7-6 Always 0 bit 4-0 EventStatus_wa 0x22 AMC DAQ_Link ststus bit 31-15 Always 0 bit 14-0 DataBuf_wa 0x24 AMC DAQ_Link ststus bit 31-15 Always 0 bit 14-0 DataBuf_ra 0x26 AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_wa 0x28 AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_ra 0x2a AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 AMCinfo_wa 0x2e AMC DAQ_Link ststus bit 31-9 Always 0 bit 8-4 EventCnt bit 3-2 ReSendQue_a bit 1 AlmostFull bit 0 dataFIFO_Empty 0x40-41 total word counter 0x42-43 single bit error counter 0x44-45 multi-bit error counter 0x46-47 BC0 mismatch error counter 0x48-49 bcnt mismatch error counter 0x4a-4b ReSend counter 0x4c-4d Accept counter 0x4e-4f Counter Accept counter 0x50-51 ACK counter 0x52-53 Receive Event counter 0x54-55 Read Event counter 0x56-57 Data abort counter 0x58-59 Counter abort counter 0x5a-5b abort due to ACKNUM_full counter 0x5c-5d abort due to EventBuf_full counter 0x5e-5f abort due to EventInfo_full counter 0x60-61 abort due to bad SEQ counter 0x62-63 abort due to bad CRC counter 0x64-65 abort due to bad frame counter 0x66-67 abort due to bad K character counter 0x68-69 BUSY time counter(reserved) 0x6a-6b AMC event EVN mismatch counter 0x6c-6d AMC event BCN mismatch counter 0x6e-6f AMC event OCN mismatch counter 0x70-71 bad eventlength counter 0x72 AMC_Link ststus bit 31-14 Always 0 bit 13-0 EventBuf_wa 0x74 AMC_Link ststus bit 31-14 Always 0 bit 13-2 EventBuf_ra bit 1-0 Always 0 0x76 AMC_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_wa 0x78 AMC_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_ra 0x7a AMC_Link ststus bit 31-16 Always 0 bit 15 AMC_L1A_full bit 14 Always 0 bit 13-8 AMC_L1A bit 7-0 L1Ainfo_wap 0x7c AMC_Link ststus bit 31-16 Always 0 bit 15-14 ReSendQue_a bit 13-12 rfifo_a bit 11-10 ACKNUM_a bit 9 reset_sync(3) bit 8 RXLOSSOFSYNC(1) bit 7 TxResetDone bit 6 RxResetDone bit 5 RxPllLock bit 4 InitLink bit 3-0 TxState 0x7e AMC_Link ststus bit 31-15 Always 0 bit 4 got_AMC_BC0 bit 3 TTC_lock bit 2 BC0_lock bit 1 AMC_RdEnToggle bit 0 EventInfoToggle 0x880-0x8FF AMC2 counter 0x900-0x97F AMC3 counter 0x980-0x9FF AMC4 counter 0xa00-0xa7F AMC5 counter 0xa80-0xaFF AMC6 counter 0xb00-0xb7F AMC7 counter 0xb80-0xbFF AMC8 counter 0xc00-0xc7F AMC9 counter 0xc80-0xcFF AMC10 counter 0xd00-0xd7F AMC11 counter 0xd80-0xdFF AMC12 counter 0xe00 EventInfo for AMC1 0xe01 EventInfo for AMC2 0xe02 EventInfo for AMC3 0xe03 EventInfo for AMC4 0xe04 EventInfo for AMC5 0xe05 EventInfo for AMC6 0xe06 EventInfo for AMC7 0xe07 EventInfo for AMC8 0xe08 EventInfo for AMC9 0xe09 EventInfo for AMC10 0xe0a EventInfo for AMC11 0xe0b EventInfo for AMC12 0xe0c AMC_if status bit 31-15 Always 0 bit 14 '1' if qpll for AMC9-12 not locked bit 13 '1' if qpll for AMC5-8 not locked bit 12 '1' if qpll for AMC1-4 not locked bit 11-0 EventInfo_dav 0xe0d AMC_TTC_status bit 31-28 Always 0 bit 27-16 1 if corresponding AMC enabled and TTC locked bit 15-12 Always 0 bit 11-0 1 if corresponding AMC enabled and BC0 locked 0xe0f AMC_if status bit 31-8 Always 0 bit 7-0 evn_cnt 0xe10 AMC_if status bit 31-25 Always 0 bit 24-16 evn_ra bit 15-9 Always 0 bit 8-0 evn_wa 0xe11 AMC_if status bit 31-24 Always 0 bit 23-0 evn 0xe12 AMC_if status bit 31-25 Always 0 bit 24-16 CDF_ra bit 15-9 Always 0 bit 8-0 CDF_wa 0xe13 AMC_if status bit 31-23 Always 0 bit 22 mon_buf_avl bit 21 init_bldr bit 20 evn_empty bit 19 event_avl bit 18-16 wc_fifo_full bit 15 ec_CDF_ra bit 14-12 AMC_wc_we bit 11 sel_CDF bit 10-8 AMC_header_we bit 7-6 sel_evn bit 5-4 Always 0 bit 3-0 sel_AMC 0xe14 AMC_if status bit 31-0 fake_word_cnt 0xe15 AMC_if status bit 31-0 fake_header_cnt 0xe16 AMC_if status bit 31-0 fake_evt_cnt 0xe17 AMC_if status bit 31-0 fake_empty_cnt 0xe1a AMC_if status read only TTS is encoded from MSB as disconnected, error, sync lost, busy and overflow warning bit 31-29 Always 0 bit 28-24 AMC4 TTS_encoded bit 23-21 Always 0 bit 20-16 AMC3 TTS_encoded bit 15-13 Always 0 bit 12-8 AMC2 TTS_encoded bit 7-5 Always 0 bit 4-0 AMC1 TTS_encoded 0xe1b AMC_if status read only TTS is encoded from MSB as disconnected, error, sync lost, busy and overflow warning bit 31-29 Always 0 bit 28-24 AMC8 TTS_encoded bit 23-21 Always 0 bit 20-16 AMC7 TTS_encoded bit 15-13 Always 0 bit 12-8 AMC6 TTS_encoded bit 7-5 Always 0 bit 4-0 AMC5 TTS_encoded 0xe1c AMC_if status read only TTS is encoded from MSB as disconnected, error, sync lost, busy and overflow warning bit 31-29 Always 0 bit 28-24 AMC12 TTS_encoded bit 23-21 Always 0 bit 20-16 AMC11 TTS_encoded bit 15-13 Always 0 bit 12-8 AMC10 TTS_encoded bit 7-5 Always 0 bit 4-0 AMC9 TTS_encoded 0x20000-0x3ffff memory read window 0x8000000-0xfffffff full memory read/write access.(write disabled when bit 0 of reg 0x1 is set. spartan chip memory map: 0x0 reads: bit 23-16 SN number bit 15-0 T2 firmware version write: bit 0 general reset write: bit 4 start V6 reconfiguration write: bit 8 start both S6 and V6 reconfiguration 0x1 read/write read bit 0 FLASH busy write sends data stored in FLASH wbuf to FLASH memory chip bit 8-0 specifies number of (clocks/8 -1) to be sent to the FLASH memory (depends on the type of the FLASH command and number of bytes to be read or written) 0x2 read only (reads back what was written to V6 chip 0x3) bit 11-0 enables TTC clock and data to AMC modules 0x3 read only bit 31 if '1', virtex chip INIT_B is low bit 30 if '1', virtex chip DONE is low bit 23-0 configuration data CRC 0x4 bit 15-0 TTC event number register 0x5 bit 11-0 TTC L1 Bcnt register 0x6 bit 31-0 TTC L1 orbit count register 0x7 bit 7-0 TTC Bcnt error counter 0x8 bit 7-0 TTC single bit error counter 0x9 bit 7-0 TTC multi-bit error counter 0xa bit 7-0 T2 Serial Number 0xd read/write bit 11-0 enables TTC clock and data to AMC modules bit 30 if set, TTC clock source comes from T3 0xe read only bit 31-0 FPGA DNA bits 31-0 0xf read only bit 31-25 always reads 0 bit 24-0 FPGA DNA bits 56-32 0x1000 thru 0x107f read/write FLASH write buffer always write FLASH command(including FLASH address if any) to address 0x1000 for page write command, attach the write data starting at address 0x1001 you can read back what you have writen to the write buffer. 0x1080 thru 0x10ff read only FLASH read buffer you read whatever data are returned from the FLASH memory here initial test of AMC13XG on the special test stand: Open CHIPSCOPE(v14.5 or later) and loading project file D:\vproject\testAMC\testAMC.runs\impl_3\testAMC.cpj Configure T2 and then T1 with files amc13_t2test.bit and amc13_t1.bit in D:\vproject\testAMC\testAMC.runs\impl_3. Open VIO consoles of MYVIO0 and MYVIO2, set prbssel to 0x111111111111 and amc1 thru amc12 in MYVIO0 would get some counts and then stay unchanging. If any channel is counting continuously, the corresponging AMC Tx/Rx has a proprblem. amc_en in the same window should read 0xfff. Connecting TTC signal to the bottom SFP and you should be able to see TTC clock signals on the terminating resistors on the test stand. instructions about internal TTC clock and L1A generation To use internally generated TTC clock, use an optical fiber to loop back the bottom SFP transceiver optical signal. Bit 8 of register 1 must be set to '1' To use internally generated L1A, bit 2 of register 1 must be set to '1' To send a predetermined number of L1A, write 1 to bit 10 of register 0 To send continous L1A, write 1 to bit 26 of register 0, to termainate it, write 1 to bit 10 of register 0. write 1 of bit 0 of register 0 will also terminate it. when in internal L1A mode, you can write 1 to bit 11 of register 0 to send an reset event number command through TTC, or write 1 to bit 12 to reset the orbit count TTC command. You can send both at the same time. A general reset, i.e. write 1 to bit 0 of register 0 will reset both too among other things. register 0x1c is used to configure internal L1A generation: N is contents of bit 15-0 bit 31 and 30 is used to chose the type of L1A: if "00", L1A is generated every N+1 orbits at BX = 500 if "10", L1A is generated every N+1 BX, trigger rules apply when N < 63 if "11", L1A is generated at random spacing, trigger rules apply. The average frequency is 2N Bit 29-28 determines how many trigger rules are enforced: "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A sent in a burst is its countents + 1 To run memory test, first write 0 to register 0x1, then write 1 to register0x0, write either 0x10 or 0x50 to register 0x1 to start the test.