Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedSat Mar 22 09:37:22 2014 product_versionVivado v2013.4 (64-bit)
build_version353583 os_platformWIN64
registration_id tool_flowVivado
betaFALSE route_designTRUE
target_familykintex7 target_devicexc7k325t
target_packageffg900 target_speed-2
random_idffdced8f2a0b5c90ad7d9b2ad68415fc project_idec26b45bb88747f2b01ab0ebb1dc2217
project_iteration337

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Xeon(R) CPU W3680 @ 3.33GHz cpu_speed3340 MHz
total_processors1 system_ram25.000 GB

vivado_usage
project_data
srcsetcount=178 constraintsetcount=2 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1
other_data
guimode=51

unisim_transformation
pre_unisim_transformation
bufg=15 bufgctrl=1 bufh=3 carry4=3440
dna_port=1 dsp48e1=7 fdce=2381 fdpe=257
fdre=47746 fdse=3551 fifo18e1=5 fifo36e1=90
gnd=838 gtxe2_channel=16 gtxe2_common=4 ibuf=74
ibufds=5 ibufds_gte2=3 idelayctrl=1 idelaye2=32
in_fifo=4 iobuf=4 iobufds_dcien=4 iobuf_dcien=32
iserdese2=32 lut1=8065 lut2=9283 lut3=8284
lut4=7232 lut5=10151 lut6=20031 mmcme2_adv=2
muxf7=1576 muxf8=315 obuf=67 obufds=4
obuft=5 oddr=9 oserdese2=62 out_fifo=8
phaser_in_phy=4 phaser_out_phy=8 phaser_ref=3 phy_control=3
plle2_adv=4 ram32m=283 ram32x1d=685 ram32x1d_1=14
ram32x2s=9 ram64m=1024 ram64x1d=1250 ramb18e1=19
ramb36e1=145 rom256x1=1 srl16e=1572 srlc32e=336
vcc=830 xadc=1
post_unisim_transformation
bufg=15 bufgctrl=1 bufh=3 carry4=3440
dna_port=1 dsp48e1=7 fdce=2381 fdpe=257
fdre=47746 fdse=3551 fifo18e1=5 fifo36e1=90
gnd=838 gtxe2_channel=16 gtxe2_common=4 ibuf=78
ibufds=5 ibufds_gte2=3 ibufds_ibufdisable_int=8 ibuf_ibufdisable=32
idelayctrl=1 idelaye2=32 inv=5 in_fifo=4
iserdese2=32 lut1=8065 lut2=9283 lut3=8284
lut4=7232 lut5=10151 lut6=20035 mmcme2_adv=2
muxf7=1578 muxf8=316 obuf=67 obufds=5
obuft=9 obuftds_dcien=8 obuft_dcien=32 oddr=9
oserdese2=62 out_fifo=8 phaser_in_phy=4 phaser_out_phy=8
phaser_ref=3 phy_control=3 plle2_adv=4 ramb18e1=19
ramb36e1=145 ramd32=3096 ramd64e=6596 rams32=584
srl16e=1572 srlc32e=336 vcc=830 xadc=1

placer
usage
lut=61498 ff=53764 bram36=240 dsp=7
iob=138 bufg=0 global_clocks=16 pll=4
bufr=0 nets=146730 movable_instances=130703 pins=897376
bogomips=0 effort=2 threads=2 placer_timing_driven=1
timing_constraints_exist=1 placer_runtime=616.349000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=53761 srls_augmented=0
srls_newly_gated=0 srls_total=1908 bram_ports_augmented=24 bram_ports_newly_gated=61
bram_ports_total=328 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
mig_7series_v1_9/1
iptotal=1 language=Verilog synthesis_tool=Foundation_ISE level=CONTROLLER
axi_enable=0 no_of_controllers=1 interface_type=DDR3 clk_period=1072
phy_ratio=4 clkin_period=4288 vccaux_io=2.0V memory_type=COMP
memory_part=mt41j128m16xx-107g dq_width=32 ecc=OFF data_mask=1
ordering=NORM burst_mode=8 burst_type=SEQ ca_mirror=OFF
output_drv=LOW use_cs_port=0 use_odt_port=1 rtt_nom=60
memory_address_map=BANK_ROW_COLUMN refclk_freq=200 debug_port=OFF internal_vref=0
sysclk_type=DIFFERENTIAL refclk_type=NO_BUFFER

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=kintex7
die=xc7k325tffg900-2 package=ffg900 speedgrade=-2 version=2013.4
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=100 pct_inputs_defined=4 user_junc_temp=43.4 (C)
ambient_temp=25.0 (C) user_effective_thetaja=1.776301 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=3.3 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=2.8 (C/W)
user_board_temp=25.0 (C) junction_temp=43.4 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 on-chip_power=10.362189 dynamic=10.063274
effective_thetaja=1.8 thetasa=3.3 (C/W) thetajb=2.8 (C/W) off-chip_power=0.295951
clocks=0.771924 logic=0.254981 signals=0.362700 bram=0.598972
mmcm=0.206132 pll=0.481200 dsp=0.000338 i/o=0.591273
gtx=6.193960 phaser=0.600824 xadc=0.000970 devstatic=0.298915
vccint_voltage=1.000000 vccint_total_current=3.306852 vccint_dynamic_current=3.155200 vccint_static_current=0.151652
vccaux_voltage=1.800000 vccaux_total_current=0.653207 vccaux_dynamic_current=0.621270 vccaux_static_current=0.031937
vcco33_voltage=3.300000 vcco33_total_current=0.001019 vcco33_dynamic_current=0.000019 vcco33_static_current=0.001000
vcco25_voltage=2.500000 vcco25_total_current=0.001472 vcco25_dynamic_current=0.000472 vcco25_static_current=0.001000
vcco18_voltage=1.800000 vcco18_total_current=0.001000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.001000
vcco15_voltage=1.500000 vcco15_total_current=0.430058 vcco15_dynamic_current=0.429058 vcco15_static_current=0.001000
vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vccaux_io_voltage=2.000000 vccaux_io_total_current=0.109416 vccaux_io_dynamic_current=0.109416 vccaux_io_static_current=0.000000
vccbram_voltage=1.000000 vccbram_total_current=0.047855 vccbram_dynamic_current=0.039448 vccbram_static_current=0.008407
mgtavcc_voltage=1.050000 mgtavcc_total_current=3.380719 mgtavcc_dynamic_current=3.358097 mgtavcc_static_current=0.022623
mgtavtt_voltage=1.200000 mgtavtt_total_current=1.328502 mgtavtt_dynamic_current=1.318164 mgtavtt_static_current=0.010339
mgtvccaux_voltage=1.800000 mgtvccaux_total_current=0.041233 mgtvccaux_dynamic_current=0.041172 mgtvccaux_static_current=0.000061
vccadc_voltage=1.800000 vccadc_total_current=0.020400 vccadc_dynamic_current=0.000400 vccadc_static_current=0.020000
confidence_level_design_state=High confidence_level_clock_activity=High confidence_level_io_activity=Low confidence_level_internal_activity=Medium
confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=60002 slice_luts_loced=0 slice_luts_available=203800 slice_luts_util_percentage=29.44
lut_as_logic_used=50221 lut_as_logic_loced=0 lut_as_logic_available=203800 lut_as_logic_util_percentage=24.64
lut_as_memory_used=9781 lut_as_memory_loced=0 lut_as_memory_available=64000 lut_as_memory_util_percentage=15.28
lut_as_distributed_ram_used=8454 lut_as_distributed_ram_loced=0 lut_as_shift_register_used=1327 lut_as_shift_register_loced=0
slice_registers_used=53762 slice_registers_loced=0 slice_registers_available=407600 slice_registers_util_percentage=13.18
register_as_flip_flop_used=53762 register_as_flip_flop_loced=0 register_as_flip_flop_available=407600 register_as_flip_flop_util_percentage=13.18
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=407600 register_as_latch_util_percentage=0.00
f7_muxes_used=1578 f7_muxes_loced=0 f7_muxes_available=101900 f7_muxes_util_percentage=1.54
f8_muxes_used=316 f8_muxes_loced=0 f8_muxes_available=50950 f8_muxes_util_percentage=0.62
slice_used=24006 slice_loced=0 slice_available=50950 slice_util_percentage=47.11
lut_as_logic_used=50221 lut_as_logic_loced=0 lut_as_logic_available=203800 lut_as_logic_util_percentage=24.64
using_o5_output_only_used=1 using_o5_output_only_loced= using_o6_output_only_used=43658 using_o6_output_only_loced=
using_o5_and_o6_used=6562 using_o5_and_o6_loced= lut_as_memory_used=9781 lut_as_memory_loced=0
lut_as_memory_available=64000 lut_as_memory_util_percentage=15.28 lut_as_distributed_ram_used=8454 lut_as_distributed_ram_loced=0
using_o5_output_only_used=2 using_o5_output_only_loced= using_o6_output_only_used=6630 using_o6_output_only_loced=
using_o5_and_o6_used=1822 using_o5_and_o6_loced= lut_as_shift_register_used=1327 lut_as_shift_register_loced=0
using_o5_output_only_used=102 using_o5_output_only_loced= using_o6_output_only_used=644 using_o6_output_only_loced=
using_o5_and_o6_used=581 using_o5_and_o6_loced= lut_flip_flop_pairs_used=74419 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=203800 lut_flip_flop_pairs_util_percentage=36.51 fully_used_lut_ff_pairs_used=31650 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=14522 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=28247 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=3103 minimum_number_of_registers_lost_to_control_set_restriction_used=6790(Lost)
memory
block_ram_tile_used=247 block_ram_tile_loced=0 block_ram_tile_available=445 block_ram_tile_util_percentage=55.50
ramb36_fifo*_used=240 ramb36_fifo*_loced=0 ramb36_fifo*_available=445 ramb36_fifo*_util_percentage=53.93
fifo18e1_only_used=5 fifo36e1_only_used=90 ramb36e1_only_used=145 ramb18_used=19
ramb18_loced=0 ramb18_available=890 ramb18_util_percentage=2.13 ramb18e1_only_used=19
dsp
dsps_used=7 dsps_loced=0 dsps_available=840 dsps_util_percentage=0.83
dsp48e1_only_used=7
io_and_gtx
bonded_iob_used=138 bonded_iob_loced=138 bonded_iob_available=500 bonded_iob_util_percentage=27.60
iob_master_pads_used=66 iob_master_pads_loced= iob_slave_pads_used=72 iob_slave_pads_loced=
iob_flip_flops_used=2 iob_flip_flops_loced=2 bonded_ipads_used=38 bonded_ipads_loced=38
bonded_ipads_available=50 bonded_ipads_util_percentage=76.00 bonded_opads_used=32 bonded_opads_loced=32
bonded_opads_available=32 bonded_opads_util_percentage=100.00 gtxe2_channel_used=16 gtxe2_channel_loced=16
gtxe2_channel_available=16 gtxe2_channel_util_percentage=100.00 gtxe2_common_used=4 gtxe2_common_loced=0
gtxe2_common_available=4 gtxe2_common_util_percentage=100.00 ibufgds_used=0 ibufgds_loced=0
ibufgds_available=480 ibufgds_util_percentage=0.00 idelayctrl_used=2 idelayctrl_loced=0
idelayctrl_available=10 idelayctrl_util_percentage=20.00 in_fifo_used=4 in_fifo_loced=4
in_fifo_available=40 in_fifo_util_percentage=10.00 out_fifo_used=8 out_fifo_loced=8
out_fifo_available=40 out_fifo_util_percentage=20.00 phaser_ref_used=3 phaser_ref_loced=3
phaser_ref_available=10 phaser_ref_util_percentage=30.00 phy_control_used=3 phy_control_loced=3
phy_control_available=10 phy_control_util_percentage=30.00 phaser_out_phaser_out_phy_used=8 phaser_out_phaser_out_phy_loced=8
phaser_out_phaser_out_phy_available=40 phaser_out_phaser_out_phy_util_percentage=20.00 phaser_out_phy_only_used=8 phaser_out_phy_only_loced=8
phaser_in_phaser_in_phy_used=4 phaser_in_phaser_in_phy_loced=4 phaser_in_phaser_in_phy_available=40 phaser_in_phaser_in_phy_util_percentage=10.00
phaser_in_phy_only_used=4 phaser_in_phy_only_loced=4 idelaye2_idelaye2_finedelay_used=32 idelaye2_idelaye2_finedelay_loced=32
idelaye2_idelaye2_finedelay_available=500 idelaye2_idelaye2_finedelay_util_percentage=6.40 idelaye2_only_used=32 idelaye2_only_loced=32
odelaye2_odelaye2_finedelay_used=0 odelaye2_odelaye2_finedelay_loced=0 odelaye2_odelaye2_finedelay_available=150 odelaye2_odelaye2_finedelay_util_percentage=0.00
ibufds_gte2_used=3 ibufds_gte2_loced=3 ibufds_gte2_available=8 ibufds_gte2_util_percentage=37.50
ilogic_used=33 ilogic_loced=33 ilogic_available=500 ilogic_util_percentage=6.60
iff_register_used=1 iff_register_loced=1 iserdes_used=32 iserdes_loced=32
ologic_used=68 ologic_loced=68 ologic_available=500 ologic_util_percentage=13.60
outff_register_used=1 outff_register_loced=1 outff_oddr_register_used=5 outff_oddr_register_loced=5
tff_oddr_register_used=4 tff_oddr_register_loced=4 oserdes_used=62 oserdes_loced=62
clocking
bufgctrl_used=16 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=50.00
bufio_used=0 bufio_loced=0 bufio_available=40 bufio_util_percentage=0.00
mmcme2_adv_used=2 mmcme2_adv_loced=1 mmcme2_adv_available=10 mmcme2_adv_util_percentage=20.00
plle2_adv_used=4 plle2_adv_loced=1 plle2_adv_available=10 plle2_adv_util_percentage=40.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=20 bufmrce_util_percentage=0.00
bufhce_used=1 bufhce_loced=0 bufhce_available=168 bufhce_util_percentage=0.59
bufr_used=0 bufr_loced=0 bufr_available=40 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=1 dna_port_loced=1 dna_port_available=1 dna_port_util_percentage=100.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_loced=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=1 xadc_loced=1 xadc_available=1 xadc_util_percentage=100.00
primitives
fdre_used=47648 lut6_used=19921 lut5_used=10156 lut2_used=9272
lut3_used=8292 lut4_used=7252 ramd64e_used=6596 fdse_used=3496
carry4_used=3416 ramd32_used=3096 fdce_used=2384 lut1_used=1890
muxf7_used=1578 srl16e_used=1572 rams32_used=584 srlc32e_used=336
muxf8_used=316 fdpe_used=236 ramb36e1_used=145 fifo36e1_used=90
ibuf_used=78 obuf_used=67 oserdese2_used=62 obuft_dcien_used=32
iserdese2_used=32 idelaye2_used=32 ibuf_ibufdisable_used=32 ramb18e1_used=19
gtxe2_channel_used=16 bufg_used=15 oddr_used=9 obuft_used=9
phaser_out_phy_used=8 out_fifo_used=8 obuftds_dcien_used=8 ibufds_ibufdisable_int_used=8
dsp48e1_used=7 obufds_used=5 inv_used=5 ibufds_used=5
fifo18e1_used=5 plle2_adv_used=4 phaser_in_phy_used=4 in_fifo_used=4
gtxe2_common_used=4 phy_control_used=3 phaser_ref_used=3 ibufds_gte2_used=3
mmcme2_adv_used=2 idelayctrl_used=2 xadc_used=1 dna_port_used=1
bufh_used=1 bufgctrl_used=1
io_standard
diff_sstl15_dci=0 hstl_i_18=0 tmds_33=0 sstl18_ii_dci=0
diff_sstl18_ii=0 lvcmos15=1 diff_sstl18_i_dci=0 hstl_i_dci=0
blvds_25=0 sstl135=0 diff_hstl_i_18=0 lvcmos33=1
diff_hstl_i_dci_18=0 sstl135_r=0 pci33_3=0 sstl18_ii=0
sstl12_t_dci=0 diff_hstl_i_dci=0 hslvdci_15=0 diff_sstl12_dci=0
hstl_ii_t_dci_18=0 sstl135_dci=0 diff_sstl135_r=0 lvdci_15=0
diff_sstl15_t_dci=1 hstl_ii_18=0 mini_lvds_25=0 sstl18_ii_t_dci=0
diff_sstl15=1 lvcmos12=0 diff_sstl18_ii_dci=0 hstl_ii_dci=0
lvds_25=1 sstl12=0 diff_hstl_ii_18=1 lvttl=0
diff_hstl_ii_dci_18=0 hstl_i=0 mobile_ddr=0 sstl15=1
diff_hstl_i=0 diff_hstl_ii_dci=0 lvdci_dv2_18=0 diff_sstl12_t_dci=0
hstl_i_12=0 sstl135_t_dci=0 diff_sstl12=0 hsul_12_dci=0
diff_sstl135_dci=0 hstl_i_dci_18=0 ppds_25=0 sstl15_dci=0
diff_sstl15_r=0 hsul_12=0 diff_sstl18_ii_t_dci=0 hstl_ii_t_dci=0
rsds_25=0 sstl18_i_dci=0 diff_sstl18_i=0 lvcmos18=1
diff_hstl_ii_t_dci_18=0 hstl_ii=0 diff_mobile_ddr=0 sstl15_r=0
diff_hstl_ii=0 lvcmos25=1 diff_hstl_ii_t_dci=0 lvdci_dv2_15=0
diff_hsul_12_dci=0 sstl18_i=0 sstl12_dci=0 diff_hsul_12=0
hslvdci_18=0 diff_sstl135_t_dci=0 hstl_ii_dci_18=0 lvds=0
sstl15_t_dci=1 diff_sstl135=0 lvdci_18=0

router
usage
lut=62251 ff=53764 bram36=240 dsp=7
iob=138 bufg=0 global_clocks=16 pll=4
bufr=0 nets=146595 movable_instances=130568 pins=897245
bogomips=0 high_fanout_nets=102 effort=2 threads=2
router_timing_driven=1 timing_constraints_exist=1 congestion_level=2 router_runtime=453.171000

synthesis
command_line_options
-part=xc7k325tffg900-2 -name=default::[not_specified] -top=AMC13_T1 -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::4
usage
elapsed=00:11:40s memory_peak=2087.734MB memory_gain=1901.777MB