Mar. 27 2014 T1 version 0xfb and T2 version 0x1c ipbus interface code modified. transactor_sm.vhd changed back to module come with ipbus_2_0_v1.r27848 Mar. 19 2014 T1 version 0xfc and T2 version 0x1b problem detected, replace transcator_sm.vhd with the home-modified version Mar. 18 2014 T1 version 0xfd and T2 version 0x1a ipbus firmware updated to ipbus_2_0_v1.r27848 Dec. 23 2013 T1 version 0xff and T2 version 0x19 This is a special version which implements three DAQLDC receiving channels on SFP0, SFP1 and SFP2. It can save the first 0x1000 events in the ddr3 memory for monioring purposes. There are also various registers for status and counters. To use it, first set register 0x3 to enable SFPs to be used receiving DAQ data. Then write 1 to registers 0 to reset the module. The transmitter side must also enable the transmitting SFPs and write 1 to its register 0. Next write 0x80010006 to 0x80 and write 0 to 0x81 to set up the SFPs for receiving. The first 0x1000 events will be saved in the memory and can be read out as in standard amc13 modules. After the monitoring buffer is full, further events will not be saved, but the counters will continue counting. SFP assignment from top to bottom on module's front panel: SFP0 DAQLSC link SFP1 DAQLSC link SFP2 DAQLSC link TTC Spartan chip default IP address 192.168.1.(254 - 2*SN) kintex chip default IP address 192.168.1.(255 - 2*SN) kintex chip memory map: 0x0 read/write write: bit 0 general reset(ddr3 memory controller not encluded) write: bit 1 counter reset write: bit 5 reset ddr3 memory controller write: bit 10 if bit 10 reads '0', it sends a burst of local L1A if bit 10 reads '1', it only resets it to '0' write: bit 11 sends event number reset thru TTC when in local L1A mode write: bit 12 sends orbut number reset thru TTC when in local L1A mode write: bit 26 set continous local L1A(setup with register 0x1c) read: 0 reads '1' when any of the enabled SFP ports is down read: 2 monitor buffer full read: 3 monitor buffer empty read: 5 TTC not ready read: 6 TTC bcnt error read: 7 TTC single bit error read: 8 TTC multi-bit error read: 9 TTC sync lost(L1A buffer overflow) read: 10 continous local L1A on(setup with register 0x1c) read: 13 L1A overflow warning read: 15 if 0, DDR memory reset done read: bit 31-24 T1 board SN 0x1 read/write bit 31-16 read only Virtex firmware version bit 15-2 to be ignored bit 1 '1' enables DAQLDC, default is '1' bit 0 run mode, default is '1' 0x3 HTR channel enable register R/w read: bit 31 always '0' bit 30 '1' when DAQLSC of SFP2 is down bit 29 '1' when DAQLSC of SFP1 is down bit 28 '1' when DAQLSC of SFP0 is down bit 27-15 ignored bit 14 '1' enables SFP2 bit 13 '1' enables SFP1 bit 12 '1' enables SFP0 bit 11-0 ignored 0x4 SFP Control and Status register R/w read: bit 31-16 SLINK ID(bits 15-14 always '0') bit 15 '1' disables TTS transmitter bit 14 '1' disables SFP2 transmitter bit 13 '1' disables SFP1 transmitter bit 12 '1' disables SFP0 transmitter bit 11 '1' indicates TTS TxFault bit 10 '1' indicates SFP2 TxFault bit 9 '1' indicates SFP1 TxFault bit 8 '1' indicates SFP0 TxFault bit 7 '1' indicates TTC_LOS or TTC_LOL bit 6 '1' indicates SFP2 Receiver signal lost bit 5 '1' indicates SFP1 Receiver signal lost bit 4 '1' indicates SFP0 Receiver signal lost bit 3 '1' indicates TTC/TTS SFP absent bit 2 '1' indicates SFP2 absent bit 1 '1' indicates SFP1 absent bit 0 '1' indicates SFP0 absent write: bit 31-16 SLINK ID(bits 15-14 always '0') bit 15-12 write '1' to disable the transmitter other bits not writable offset 0xc SDRAM page register R/W read: bit 31-13 always '0' bit 12-0 SDRAM page number write: If run bit is '1', write '0' to bit 0 of this register increments page number by 1 bit 31-13 not used bit 12-0 SDRAM page number, each page is 64kbytes size In catch mode, only one event can be catched offset 0xd monitoring event word count Read only read: bit 31 always '0' bit 30-24 all 0 if not in catch mode, otherwise gives the number of events stored after the bad event bit 23-16 all 0 if not in catch mode, otherwise gives the type of error of the bad event bit 15-14 always '0' bit 13-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable word count for AMC1-12 when only one SFP enabled word count for AMC1-6 when two SFP enabled word count for AMC1-4 when all SFP enabled offset 0xe monitored event count Read only read: bit 31-12 always '0' bit 11-0 number of unread events captured by monitor 0x1d read only monitored event word count bit 31-16 word count for AMC9-12 when all SFP enabled bit 15-0 word count for AMC5-8 when all SFP enabled or word count for AMC7-12 when two SFP enabled 0x1e read only bit 31-0 FPGA DNA bits 31-0 0x1f read only bit 31-25 always reads 0 bit 24-0 FPGA DNA bits 56-32 0x30 V6 die temperature in unit of 0.1 degree Celsius 0x31 1.0V analog power voltage in millivolt 0x32 1.2V analog power voltage in millivolt 0x33 1.0V Vccint power voltage in millivolt 0x34 1.5V power voltage in millivolt 0x35 2.5V power voltage in millivolt 0x36 3.3V power voltage in millivolt 0x38 12V power voltage in millivolt 0x39 1.8V VccAuxGTX power voltage in millivolt 0x3a 2.0V VccAuxIO power voltage in millivolt 0x3b 0.75V DDR3_Vtt power voltage in millivolt 0x3c 0.75V DDR3_Vref power voltage in millivolt 0x3d 1.8V VccAux power voltage in millivolt 0x3e 1.0V VccBRAM power voltage in millivolt 0x80-0x97 DAQLDC counter and status registers Read Only 0x80 SFP0 ack count 0x81 SFP0 packet count 0x82 SFP0 retransmit count 0x83 SFP0 event count 0x84 SFP0 word count 0x85 SFP0 sync loss count 0x86 SFP0 DAQLSC status bit 31-0 0x87 SFP0 DAQLSC status bit 63-32 0x88 SFP1 ack count 0x89 SFP1 packet count 0x8a SFP1 retransmit count 0x8b SFP1 event count 0x8c SFP1 word count 0x8d SFP1 sync loss count 0x8e SFP1 DAQLSC status bit 31-0 0x8f SFP1 DAQLSC status bit 63-32 0x90 SFP2 ack count 0x91 SFP2 packet count 0x92 SFP2 retransmit count 0x93 SFP2 event count 0x94 SFP2 word count 0x95 SFP2 sync loss count 0x96 SFP2 DAQLSC status bit 31-0 0x97 SFP2 DAQLSC status bit 63-32 0xa0-0xae DAQLDC_if status and counters Read Only 0xa1 bit 12-0 Monitored buffer count 0xa2 bit 27-16 next monitor buffer for event builder 1 bit 11-0 next monitor buffer for event builder 0 0xa3 bit 27-16 next monitor buffer for all event builder bit 11-0 next monitor buffer for event builder 2 0xa4 bit 31-23 Always '0' bit 22-20 header bit 19 '0' bit 18-16 LinkFull_n bit 15 '0' bit 14-12 ReadBusy bit 11 '0' bit 10-8 evt_data_rdy bit 7 '0' bit 6-4 wport_FIFO_full bit 3 '0' bit 2-0 wport_rdy 0xa5 event count for SFP0 0xa6 event count for SFP1 0xa7 event count for SFP2 0xa8 word count for SFP0 0xa9 word count for SFP1 0xaa word count for SFP2 0xab event count for event builder 0 0xac event count for event builder 1 0xad event count for event builder 2 0xae monitored event count 0x100-0x11f SFP0 ROM data(first 128 bytes, little endian) 0x120-0x13f SFP1 ROM data(first 128 bytes, little endian) 0x140-0x15f SFP2 ROM data(first 128 bytes, little endian) 0x160-0x17f TTC/TTS SFP ROM data(first 128 bytes, little endian) 0x4000-0x7fff memory read window 0x8000000-0xbffffff full memory read/write access.(write disabled when bit 0 of reg 0x1 is set. spartan chip memory map: 0x0 reads: bit 23-16 SN number bit 15-0 T2 firmware version write: bit 0 general reset write: bit 4 start V6 reconfiguration write: bit 8 start both S6 and V6 reconfiguration 0x1 read/write read bit 0 FLASH busy write sends data stored in FLASH wbuf to FLASH memory chip bit 8-0 specifies number of (clocks/8 -1) to be sent to the FLASH memory (depends on the type of the FLASH command and number of bytes to be read or written) 0x2 read only (reads back what was written to V6 chip 0x3) bit 11-0 enables TTC clock and data to AMC modules 0x3 read only bit 31 if '1', virtex chip INIT_B is low bit 30 if '1', virtex chip DONE is low bit 23-0 configuration data CRC 0x4 bit 15-0 TTC event number register 0x5 bit 11-0 TTC L1 Bcnt register 0x6 bit 31-0 TTC L1 orbit count register 0x7 bit 7-0 TTC Bcnt error counter 0x8 bit 7-0 TTC single bit error counter 0x9 bit 7-0 TTC multi-bit error counter 0xa bit 7-0 T2 Serial Number 0xd read/write bit 11-0 enables TTC clock and data to AMC modules 0xe read only bit 31-0 FPGA DNA bits 31-0 0xf read only bit 31-25 always reads 0 bit 24-0 FPGA DNA bits 56-32 0x1000 thru 0x107f read/write FLASH write buffer always write FLASH command(including FLASH address if any) to address 0x1000 for page write command, attach the write data starting at address 0x1001 you can read back what you have writen to the write buffer. 0x1080 thru 0x10ff read only FLASH read buffer you read whatever data are returned from the FLASH memory here initial test of AMC13XG on the special test stand: Open CHIPSCOPE(v14.5 or later) and loading project file D:\vproject\testAMC\testAMC.runs\impl_3\testAMC.cpj Configure T2 and then T1 with files amc13_t2test.bit and amc13_t1.bit in D:\vproject\testAMC\testAMC.runs\impl_3. Open VIO consoles of MYVIO0 and MYVIO2, set prbssel to 0x111111111111 and amc1 thru amc12 in MYVIO0 would get some counts and then stay unchanging. If any channel is counting continuously, the corresponging AMC Tx/Rx has a proprblem. amc_en in the same window should read 0xfff. Connecting TTC signal to the bottom SFP and you should be able to see TTC clock signals on the terminating resistors on the test stand. instructions about internal TTC clock and L1A generation To use internally generated TTC clock, use an optical fiber to loop back the bottom SFP transceiver optical signal. Bit 8 of register 1 must be set to '1' To use internally generated L1A, bit 2 of register 1 must be set to '1' To send a predetermined number of L1A, write 1 to bit 10 of register 0 To send continous L1A, write 1 to bit 26 of register 0, to termainate it, write 1 to bit 10 of register 0. write 1 of bit 0 of register 0 will also terminate it. when in internal L1A mode, you can write 1 to bit 11 of register 0 to send an reset event number command through TTC, or write 1 to bit 12 to reset the orbit count TTC command. You can send both at the same time. A general reset, i.e. write 1 to bit 0 of register 0 will reset both too among other things. register 0x1c is used to configure internal L1A generation: N is contents of bit 15-0 bit 31 and 30 is used to chose the type of L1A: if "00", L1A is generated every N+1 orbits at BX = 500 if "10", L1A is generated every N+1 BX, trigger rules apply when N < 63 if "11", L1A is generated at random spacing, trigger rules apply. The average frequency is 2N Bit 29-28 determines how many trigger rules are enforced: "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A sent in a burst is its countents + 1 To run memory test, first write 0 to register 0x1, then write 1 to register0x0, write either 0x10 or 0x50 to register 0x1 to start the test.