Release 14.7 Map P.20131013 (lin64) Xilinx Map Application Log File for Design 'AMC13_T2' Design Information ------------------ Command Line : map -intstyle ise -p xc6slx45t-fgg484-2 -w -logic_opt on -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr b -lc off -power off -o AMC13_T2_map.ncd AMC13_T2.ngd AMC13_T2.pcf Target Device : xc6slx45t Target Package : fgg484 Target Speed : -2 Mapper Version : spartan6 -- $Revision: 1.55 $ Mapped Date : Fri Dec 4 10:37:26 2020 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc6slx45t' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Mapping design into LUTs... WARNING:MapLib:53 - The offset specification "OFFSET=OUT 10000 pS AFTER ipb_clk" has been discarded because the referenced clock pad net (ipb_clk) was optimized away. Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 1 mins Total CPU time at the beginning of Placer: 58 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:19c32ac2) REAL time: 1 mins 7 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:19c32ac2) REAL time: 1 mins 10 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:ae009222) REAL time: 1 mins 10 secs Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:76fedfe4) REAL time: 2 mins 49 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:76fedfe4) REAL time: 2 mins 49 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:76fedfe4) REAL time: 2 mins 49 secs Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization (Checksum:7bd036cc) REAL time: 2 mins 50 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:7bd036cc) REAL time: 2 mins 50 secs Phase 9.8 Global Placement ...................... .................................................................................. ....................................................................... ................................................................. .............................................................. Phase 9.8 Global Placement (Checksum:4c866328) REAL time: 7 mins 35 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:4c866328) REAL time: 7 mins 36 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:4988309d) REAL time: 8 mins 52 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:4988309d) REAL time: 8 mins 53 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:6cbda37e) REAL time: 8 mins 54 secs Total REAL time to Placer completion: 9 mins 45 secs Total CPU time to Placer completion: 9 mins 32 secs Running physical synthesis... Physical synthesis completed. Running post-placement packing... Writing output files... WARNING:PhysDesignRules:372 - Gated clock. Clock net GbEGTPreset is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net sysclk_dcm_locked_inv is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net sysclk_dcm_locked_reprogV6_OR_106_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net TTC_lock_inv is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp FLASH_S_PULLUP is set but the tri state is not configured. WARNING:PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp FLASH_C_PULLDOWN is set but the tri state is not configured. WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999. Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 8 Slice Logic Utilization: Number of Slice Registers: 6,154 out of 54,576 11% Number used as Flip Flops: 6,150 Number used as Latches: 4 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 5,346 out of 27,288 19% Number used as logic: 4,818 out of 27,288 17% Number using O6 output only: 2,957 Number using O5 output only: 524 Number using O5 and O6: 1,337 Number used as ROM: 0 Number used as Memory: 167 out of 6,408 2% Number used as Dual Port RAM: 18 Number using O6 output only: 2 Number using O5 output only: 0 Number using O5 and O6: 16 Number used as Single Port RAM: 0 Number used as Shift Register: 149 Number using O6 output only: 141 Number using O5 output only: 0 Number using O5 and O6: 8 Number used exclusively as route-thrus: 361 Number with same-slice register load: 320 Number with same-slice carry load: 41 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 2,064 out of 6,822 30% Number of MUXCYs used: 1,000 out of 13,644 7% Number of LUT Flip Flop pairs used: 6,508 Number with an unused Flip Flop: 1,428 out of 6,508 21% Number with an unused LUT: 1,162 out of 6,508 17% Number of fully used LUT-FF pairs: 3,918 out of 6,508 60% Number of unique control sets: 212 Number of slice register sites lost to control set restrictions: 535 out of 54,576 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 113 out of 296 38% Number of LOCed IOBs: 83 out of 113 73% IOB Flip Flops: 32 IOB Master Pads: 13 IOB Slave Pads: 13 Number of bonded IPADs: 6 out of 16 37% Number of LOCed IPADs: 6 out of 6 100% Number of bonded OPADs: 4 out of 8 50% Number of LOCed OPADs: 4 out of 4 100% Specific Feature Utilization: Number of RAMB16BWERs: 41 out of 116 35% Number of RAMB8BWERs: 1 out of 232 1% Number of BUFIO2/BUFIO2_2CLKs: 6 out of 32 18% Number used as BUFIO2s: 6 Number used as BUFIO2_2CLKs: 0 Number of BUFIO2FB/BUFIO2FB_2CLKs: 5 out of 32 15% Number used as BUFIO2FBs: 5 Number used as BUFIO2FB_2CLKs: 0 Number of BUFG/BUFGMUXs: 14 out of 16 87% Number used as BUFGs: 12 Number used as BUFGMUX: 2 Number of DCM/DCM_CLKGENs: 5 out of 8 62% Number used as DCMs: 5 Number used as DCM_CLKGENs: 0 Number of ILOGIC2/ISERDES2s: 4 out of 376 1% Number used as ILOGIC2s: 4 Number used as ISERDES2s: 0 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0% Number of OLOGIC2/OSERDES2s: 16 out of 376 4% Number used as OLOGIC2s: 16 Number used as OSERDES2s: 0 Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 256 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 58 0% Number of GTPA1_DUALs: 1 out of 2 50% Number of ICAPs: 1 out of 1 100% Number of MCBs: 0 out of 2 0% Number of PCIE_A1s: 0 out of 1 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 1 out of 4 25% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Number of RPM macros: 1 Average Fanout of Non-Clock Nets: 3.09 Peak Memory Usage: 1097 MB Total REAL time to MAP completion: 10 mins 11 secs Total CPU time to MAP completion (all processors): 9 mins 56 secs Mapping completed. See MAP report file "AMC13_T2_map.mrp" for details.