Release 14.7 par P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. localhost.localdomain:: Fri Dec 04 10:47:46 2020 par -w -intstyle ise -ol high -mt off AMC13_T2_map.ncd AMC13_T2.ncd AMC13_T2.pcf Constraints file: AMC13_T2.pcf. Loading device for application Rf_Device from file '6slx45t.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/. "AMC13_T2" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -2 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc6slx45t' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.23 2013-10-13". Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 6,154 out of 54,576 11% Number used as Flip Flops: 6,150 Number used as Latches: 4 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 5,346 out of 27,288 19% Number used as logic: 4,818 out of 27,288 17% Number using O6 output only: 2,957 Number using O5 output only: 524 Number using O5 and O6: 1,337 Number used as ROM: 0 Number used as Memory: 167 out of 6,408 2% Number used as Dual Port RAM: 18 Number using O6 output only: 2 Number using O5 output only: 0 Number using O5 and O6: 16 Number used as Single Port RAM: 0 Number used as Shift Register: 149 Number using O6 output only: 141 Number using O5 output only: 0 Number using O5 and O6: 8 Number used exclusively as route-thrus: 361 Number with same-slice register load: 320 Number with same-slice carry load: 41 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 2,064 out of 6,822 30% Number of MUXCYs used: 1,000 out of 13,644 7% Number of LUT Flip Flop pairs used: 6,508 Number with an unused Flip Flop: 1,428 out of 6,508 21% Number with an unused LUT: 1,162 out of 6,508 17% Number of fully used LUT-FF pairs: 3,918 out of 6,508 60% Number of slice register sites lost to control set restrictions: 0 out of 54,576 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 113 out of 296 38% Number of LOCed IOBs: 83 out of 113 73% IOB Flip Flops: 32 IOB Master Pads: 13 IOB Slave Pads: 13 Number of bonded IPADs: 6 out of 16 37% Number of LOCed IPADs: 6 out of 6 100% Number of bonded OPADs: 4 out of 8 50% Number of LOCed OPADs: 4 out of 4 100% Specific Feature Utilization: Number of RAMB16BWERs: 41 out of 116 35% Number of RAMB8BWERs: 1 out of 232 1% Number of BUFIO2/BUFIO2_2CLKs: 6 out of 32 18% Number used as BUFIO2s: 6 Number used as BUFIO2_2CLKs: 0 Number of BUFIO2FB/BUFIO2FB_2CLKs: 5 out of 32 15% Number used as BUFIO2FBs: 5 Number used as BUFIO2FB_2CLKs: 0 Number of BUFG/BUFGMUXs: 14 out of 16 87% Number used as BUFGs: 12 Number used as BUFGMUX: 2 Number of DCM/DCM_CLKGENs: 5 out of 8 62% Number used as DCMs: 5 Number used as DCM_CLKGENs: 0 Number of ILOGIC2/ISERDES2s: 4 out of 376 1% Number used as ILOGIC2s: 4 Number used as ISERDES2s: 0 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0% Number of OLOGIC2/OSERDES2s: 16 out of 376 4% Number used as OLOGIC2s: 16 Number used as OSERDES2s: 0 Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 256 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 58 0% Number of GTPA1_DUALs: 1 out of 2 50% Number of ICAPs: 1 out of 1 100% Number of MCBs: 0 out of 2 0% Number of PCIE_A1s: 0 out of 1 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 1 out of 4 25% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 33 secs Finished initial Timing Analysis. REAL time: 34 secs WARNING:Par:288 - The signal GPLED_B<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPLED_B<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPLED_B<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPLED_B<3>_IBUF has no load. PAR will not attempt to route this signal. Starting Router Phase 1 : 33158 unrouted; REAL time: 39 secs Phase 2 : 27253 unrouted; REAL time: 1 mins 34 secs Phase 3 : 11064 unrouted; REAL time: 2 mins 17 secs Phase 4 : 11064 unrouted; (Setup:575, Hold:1296, Component Switching Limit:0) REAL time: 2 mins 30 secs Updating file: AMC13_T2.ncd with current fully routed design. Phase 5 : 0 unrouted; (Setup:575, Hold:1162, Component Switching Limit:0) REAL time: 3 mins 18 secs Phase 6 : 0 unrouted; (Setup:431, Hold:1162, Component Switching Limit:0) REAL time: 3 mins 21 secs Updating file: AMC13_T2.ncd with current fully routed design. Phase 7 : 0 unrouted; (Setup:0, Hold:1162, Component Switching Limit:0) REAL time: 4 mins 38 secs Phase 8 : 0 unrouted; (Setup:0, Hold:1162, Component Switching Limit:0) REAL time: 4 mins 38 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 43 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 50 secs Total REAL time to Router completion: 4 mins 50 secs Total CPU time to Router completion: 4 mins 43 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | sysclk | BUFGMUX_X3Y14| No | 1206 | 0.102 | 1.810 | +---------------------+--------------+------+------+------------+-------------+ | ipb_clk | BUFGMUX_X3Y8| No | 268 | 0.683 | 2.391 | +---------------------+--------------+------+------+------------+-------------+ | TTCclk8x | BUFGMUX_X2Y12| No | 118 | 0.062 | 1.773 | +---------------------+--------------+------+------+------------+-------------+ | TTCclk | BUFGMUX_X3Y6| No | 193 | 0.689 | 2.397 | +---------------------+--------------+------+------+------------+-------------+ | S6_SCK | BUFGMUX_X3Y15| No | 34 | 0.580 | 2.336 | +---------------------+--------------+------+------+------------+-------------+ | DNA_clk | BUFGMUX_X3Y16| No | 26 | 0.104 | 1.814 | +---------------------+--------------+------+------+------------+-------------+ | TTCclk4x | BUFGMUX_X2Y10| No | 10 | 0.011 | 1.721 | +---------------------+--------------+------+------+------------+-------------+ | ICAP_clk | BUFGMUX_X3Y7| No | 16 | 0.094 | 1.807 | +---------------------+--------------+------+------+------------+-------------+ | TTCclkOut<3> | BUFGMUX_X3Y13| No | 7 | 0.000 | 2.350 | +---------------------+--------------+------+------+------------+-------------+ | TTCclkOut<0> | BUFGMUX_X2Y1| No | 7 | 0.063 | 2.382 | +---------------------+--------------+------+------+------------+-------------+ | TTCclkOut<1> | BUFGMUX_X2Y4| No | 7 | 0.084 | 2.404 | +---------------------+--------------+------+------+------------+-------------+ | TTCclkOut<2> | BUFGMUX_X2Y2| No | 7 | 0.062 | 2.404 | +---------------------+--------------+------+------+------------+-------------+ | sysclk2x | BUFGMUX_X3Y5| No | 2 | 0.009 | 1.809 | +---------------------+--------------+------+------+------------+-------------+ | GbEGTPreset | Local| | 694 | 0.000 | 8.406 | +---------------------+--------------+------+------+------------+-------------+ |sysclk_dcm_locked_in | | | | | | | v | Local| | 7 | 0.000 | 2.187 | +---------------------+--------------+------+------+------------+-------------+ |sysclk_dcm_locked_re | | | | | | | progV6_OR_106_o | Local| | 30 | 0.000 | 1.944 | +---------------------+--------------+------+------+------------+-------------+ |i_GTP_if/tile0_refcl | | | | | | | k_ibufds_i_ML_IBUF2 | Local| | 1 | 0.000 | 0.002 | +---------------------+--------------+------+------+------------+-------------+ |i_GTP_if/tile0_refcl | | | | | | | k_ibufds_i_ML_IBUF1 | Local| | 1 | 0.000 | 0.002 | +---------------------+--------------+------+------+------------+-------------+ | TTC_REFCLK_in | Local| | 2 | 0.000 | 3.263 | +---------------------+--------------+------+------+------------+-------------+ | i_GTP_if/REFCLK | Local| | 2 | 0.000 | 0.002 | +---------------------+--------------+------+------+------------+-------------+ | TTC_lock_inv | Local| | 2 | 0.000 | 2.340 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. * The fanout is the number of component pins not the individual BEL loads, for example SLICE loads not FF loads. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Number of Timing Constraints that were not applied: 8 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns | SETUP | 0.496ns| 7.504ns| 0| 0 HIGH 50% | HOLD | 0.263ns| | 0| 0 | MINPERIOD | 0.000ns| 8.000ns| 0| 0 ---------------------------------------------------------------------------------------------------------- TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dc | SETUP | 0.027ns| 24.684ns| 0| 0 m" TS_TTC_REFCLK PHASE -3.890625 ns | HOLD | 0.266ns| | 0| 0 HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclk4x_dcm = PERIOD TIMEGRP "TTCclk4 | SETUP | 0.038ns| 6.149ns| 0| 0 x_dcm" TS_TTC_REFCLK / 4 PHASE -3 | HOLD | 0.136ns| | 0| 0 .890625 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.122ns| 7.078ns| 0| 0 <0>" "RISING" | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.184ns| 7.016ns| 0| 0 <0>" "FALLING" | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.189ns| 7.011ns| 0| 0 <1>" "RISING" | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.237ns| 6.963ns| 0| 0 <2>" "RISING" | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.251ns| 6.949ns| 0| 0 <1>" "FALLING" | | | | | ---------------------------------------------------------------------------------------------------------- TS_sysclk2x = PERIOD TIMEGRP "sysclk2x" 4 | MINPERIOD | 0.297ns| 3.703ns| 0| 0 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.298ns| 6.902ns| 0| 0 <3>" "FALLING" | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.298ns| 6.902ns| 0| 0 <3>" "RISING" | | | | | ---------------------------------------------------------------------------------------------------------- OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p | MAXDELAY | 0.299ns| 6.901ns| 0| 0 <2>" "FALLING" | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclk8x_dcm = PERIOD TIMEGRP "TTCclk8 | SETUP | 0.333ns| 2.779ns| 0| 0 x_dcm" TS_TTC_REFCLK / 8 PHASE -0 | HOLD | 0.303ns| | 0| 0 .778125 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<5>" MAXDELAY = 3 ns | MAXDELAY | 0.360ns| 2.640ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<9>" MAXDELAY = 3 ns | MAXDELAY | 0.387ns| 2.613ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<6>" MAXDELAY = 3 ns | MAXDELAY | 0.550ns| 2.450ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<12>" MAXDELAY = 3 ns | MAXDELAY | 0.582ns| 2.418ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<7>" MAXDELAY = 3 ns | MAXDELAY | 0.582ns| 2.418ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "i_TRIG1/din_polarity_din_XOR_576_o" | MAXDELAY | 0.585ns| 2.415ns| 0| 0 MAXDELAY = 3 ns | | | | | ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<4>" MAXDELAY = 3 ns | MAXDELAY | 0.609ns| 2.391ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<3>" MAXDELAY = 3 ns | MAXDELAY | 0.609ns| 2.391ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<2>" MAXDELAY = 3 ns | MAXDELAY | 0.609ns| 2.391ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "i_TRIG0/din_polarity_din_XOR_576_o" | MAXDELAY | 0.622ns| 2.378ns| 0| 0 MAXDELAY = 3 ns | | | | | ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<1>" MAXDELAY = 3 ns | MAXDELAY | 0.622ns| 2.378ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<11>" MAXDELAY = 3 ns | MAXDELAY | 0.670ns| 2.330ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<10>" MAXDELAY = 3 ns | MAXDELAY | 0.826ns| 2.174ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<8>" MAXDELAY = 3 ns | MAXDELAY | 0.853ns| 2.147ns| 0| 0 ---------------------------------------------------------------------------------------------------------- COMP "TTCdata_p" OFFSET = IN 10 ns VALID | SETUP | 2.607ns| 7.393ns| 0| 0 7 ns BEFORE COMP "TTC_REFCLK" "FA | HOLD | 1.990ns| | 0| 0 LLING" | | | | | ---------------------------------------------------------------------------------------------------------- COMP "TTCdata_p" OFFSET = IN 10 ns VALID | SETUP | 2.667ns| 7.333ns| 0| 0 7 ns BEFORE COMP "TTC_REFCLK" "RI | HOLD | 1.915ns| | 0| 0 SING" | | | | | ---------------------------------------------------------------------------------------------------------- TS_REFCLK_P = PERIOD TIMEGRP "REFCLK_P" 8 | MINPERIOD | 4.297ns| 3.703ns| 0| 0 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTC_REFCLK = PERIOD TIMEGRP "TTC_REFCL | MINLOWPULSE | 14.900ns| 10.000ns| 0| 0 K" 24.9 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP | MAXDELAY | 5.361ns| 19.539ns| 0| 0 "TO_TTC_data_1_LD" TS_TTCclk_dcm | | | | | DATAPATHONLY | | | | | ---------------------------------------------------------------------------------------------------------- TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 | SETUP | 7.073ns| 17.854ns| 0| 0 ns HIGH 50% | HOLD | 0.382ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- TS_TTCclk_p = PERIOD TIMEGRP "TTCclk_p" 2 | MINLOWPULSE | 8.900ns| 16.000ns| 0| 0 4.9 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclkOut_dcm_3_ = PERIOD TIMEGRP "TTC | MINPERIOD | 22.234ns| 2.666ns| 0| 0 clkOut_dcm_3_" TS_TTCclk_p PHASE | | | | | 3.40429688 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclkOut_dcm_2_ = PERIOD TIMEGRP "TTC | MINPERIOD | 22.234ns| 2.666ns| 0| 0 clkOut_dcm_2_" TS_TTCclk_p PHASE | | | | | 3.40429688 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclkOut_dcm_1_ = PERIOD TIMEGRP "TTC | MINPERIOD | 22.234ns| 2.666ns| 0| 0 clkOut_dcm_1_" TS_TTCclk_p PHASE | | | | | 3.40429688 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclkOut_dcm_0_ = PERIOD TIMEGRP "TTC | MINPERIOD | 22.234ns| 2.666ns| 0| 0 clkOut_dcm_0_" TS_TTCclk_p PHASE | | | | | 3.40429688 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TO_CRC_0_LD = MAXDELAY TO TIMEGRP "TO_ | MAXDELAY | 28.174ns| 3.826ns| 0| 0 CRC_0_LD" TS_ipb_clk DATAPATHONLY | | | | | ---------------------------------------------------------------------------------------------------------- TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 2 | SETUP | 117.211ns| 15.578ns| 0| 0 50 ns HIGH 50% | HOLD | 0.410ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Derived Constraint Report Review Timing Report for more details on the following derived constraints. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" or "Run Timing Analysis" from Timing Analyzer (timingan). Derived Constraints for TS_TTC_REFCLK +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_TTC_REFCLK | 24.900ns| 10.000ns| 24.684ns| 0| 0| 0| 6582| | TS_TTCclk4x_dcm | 6.225ns| 6.149ns| N/A| 0| 0| 169| 0| | TS_TTCclk_dcm | 24.900ns| 24.684ns| 19.539ns| 0| 0| 6120| 2| | TS_TO_TTC_data_1_LD | 24.900ns| 19.539ns| N/A| 0| 0| 2| 0| | TS_TTCclk8x_dcm | 3.113ns| 2.779ns| N/A| 0| 0| 291| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_TTCclk_p +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_TTCclk_p | 24.900ns| 16.000ns| 2.666ns| 0| 0| 0| 0| | TS_TTCclkOut_dcm_0_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| | TS_TTCclkOut_dcm_1_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| | TS_TTCclkOut_dcm_2_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| | TS_TTCclkOut_dcm_3_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_ipb_clk +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_ipb_clk | 32.000ns| 17.854ns| 3.826ns| 0| 0| 25885| 1| | TS_TO_CRC_0_LD | 32.000ns| 3.826ns| N/A| 0| 0| 1| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 4 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 4 mins 58 secs Total CPU time to PAR completion: 4 mins 50 secs Peak Memory Usage: 905 MB Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 6 Number of info messages: 0 Writing design to file AMC13_T2.ncd PAR done!