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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:59:34 07/10/2015 
-- Design Name: 
-- Module Name:    trig_data - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity trig_data is
    Port ( clk : in  STD_LOGIC;
           din : in  STD_LOGIC;
           din_polarity : in  STD_LOGIC;
           dl : in  STD_LOGIC_VECTOR (7 downto 0);
           twinmux_ra : out  STD_LOGIC;
           buffer_dinA : out  STD_LOGIC;
           buffer_dinB : out  STD_LOGIC);
end trig_data;

architecture Behavioral of trig_data is
signal d : std_logic_vector(8 downto 0) := (others => '0');
signal q : std_logic_vector(7 downto 0) := (others => '0');
signal o : std_logic_vector(2 downto 0) := (others => '0');
attribute IOB : string;
attribute IOB of d : signal is "false";
begin
i_delay0 : SRLC32E
   port map (
      Q => q(0),        -- SRL data output
      Q31 => open,    -- SRL cascade output pin
      A => dl(4 downto 0),        -- 5-bit shift depth select input
      CE => '1',      -- Clock enable input
      CLK => clk,    -- Clock input
      D => d(0)         -- SRL data input
   );
g_delay : for i in 1 to 7 generate
	i_delay : SRLC32E
   port map (
      Q => q(i),        -- SRL data output
      Q31 => open,    -- SRL cascade output pin
      A => "11110",        -- 5-bit shift depth select input
      CE => '1',      -- Clock enable input
      CLK => clk,    -- Clock input
      D => d(i)         -- SRL data input
   );
end generate;
i_delay_buffer : SRLC32E
   port map (
      Q => o(1),        -- SRL data output
      Q31 => open,    -- SRL cascade output pin
      A => "11110",        -- 5-bit shift depth select input
      CE => '1',      -- Clock enable input
      CLK => clk,    -- Clock input
      D => o(0)         -- SRL data input
   );
process(clk)
begin
	if(clk'event and clk = '1')then
		d <= q & (din_polarity xor din);
		o(2) <= o(1);
		buffer_dinA <= o(2);
		buffer_dinB <= o(1);
		twinmux_ra <= o(0);
		case dl(7 downto 5) is
			when "000" => o(0) <= d(1);
			when "001" => o(0) <= d(2);
			when "010" => o(0) <= d(3);
			when "011" => o(0) <= d(4);
			when "100" => o(0) <= d(5);
			when "101" => o(0) <= d(6);
			when "110" => o(0) <= d(7);
			when others => o(0) <= d(8);
		end case;
	end if;
end process;
end Behavioral;