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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:36:18 12/03/2020 
-- Design Name: 
-- Module Name:    reboot - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity reboot is
    Port ( 
					 rst : in  STD_LOGIC;
					 ICAP_clk : in  STD_LOGIC;
           reprogs6 : in  STD_LOGIC);
end reboot;

architecture Behavioral of reboot is
signal en_ICAP_b : std_logic := '1';
signal ICAP_a : std_logic_vector(3 downto 0) := (others =>'0');
signal ICAP_Di : std_logic_vector(15 downto 0) := (others =>'0');

begin
process(ICAP_clk,rst)
begin
	if(rst = '1')then
		en_ICAP_b <= '1';
		ICAP_a <= x"0";
		ICAP_Di <= x"FFFF";
	elsif(ICAP_clk'event and ICAP_clk = '1')then
		if(reprogS6 = '1')then
			ICAP_a <= x"1";
		elsif(ICAP_a /= x"0")then
			ICAP_a <= ICAP_a + 1;
		end if;
		if(ICAP_a = x"1")then
			en_ICAP_b <= '0';
		elsif(ICAP_a = x"0")then
			en_ICAP_b <= '1';
		end if;
		case ICAP_a is
			when x"0" => ICAP_Di <= x"FFFF";
			when x"1" => ICAP_Di <= x"5599";
			when x"2" => ICAP_Di <= x"AA66";
--			when x"3" => ICAP_Di <= x"4C86";
--			when x"4" => ICAP_Di <= x"0000";
--			when x"5" => ICAP_Di <= x"4C81";
--			when x"6" => ICAP_Di <= x"D004";
--			when x"7" => ICAP_Di <= x"4C85";
--			when x"8" => ICAP_Di <= x"0000";
--			when x"9" => ICAP_Di <= x"4C83";
--			when x"a" => ICAP_Di <= x"D010";
			when x"3" => ICAP_Di <= x"0C85";
			when x"4" => ICAP_Di <= x"0000";
			when x"5" => ICAP_Di <= x"0C85";
			when x"6" => ICAP_Di <= x"0070";
			when others => ICAP_Di <= x"0400";
		end case;
	end if;
end process;
   ICAP_SPARTAN6_inst : ICAP_SPARTAN6
   generic map (
      DEVICE_ID => X"4000093",     -- Specifies the pre-programmed Device ID value
      SIM_CFG_FILE_NAME => "NONE"  -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
                                   -- model
   )
   port map (
      BUSY => open,   -- 1-bit output: Busy/Ready output
      O => open,         -- 16-bit output: Configuartion data output bus
      CE => en_ICAP_b,       -- 1-bit input: Active-Low ICAP Enable input
      CLK => ICAP_clk,     -- 1-bit input: Clock input
      I => ICAP_Di,         -- 16-bit input: Configuration data input bus
      WRITE => en_ICAP_b  -- 1-bit input: Read/Write control input
   );


end Behavioral;