Welcome to Xilinx CORE Generator. Help system initialized. The IP Catalog has been reloaded. Wrote CGP file for project 'coregen'. Customize and GenerateINFO:sim:172 - Generating IP... WARNING:sim:100 - The Simulation File Type is not valid for this core. Overriding with File Type . Applying current project options... Finished applying current project options. Customizing IP... Release 14.7 - Xilinx CORE Generator IP GUI Launcher P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Finished Customizing. Generating IP... WARNING:sim:100 - The Simulation File Type is not valid for this core. Overriding with File Type . Configuring files for chipscope_icon root... Gathering HDL files for chipscope_icon root... Creating XST project for chipscope_icon... Creating XST script file for chipscope_icon... Creating XST instantiation file for chipscope_icon... Running XST for chipscope_icon... XST: HDL Parsing XST: HDL Elaboration XST: HDL Synthesis XST: Advanced HDL Synthesis XST: Low Level Synthesis XST: Design Summary Generating VHDL wrapper Not generating Verilog wrapper Creating ISE instantiation template for chipscope_icon... Skipping Verilog instantiation template for chipscope_icon... Finished Generation. Generating IP instantiation template... Generating ASY schematic symbol... INFO:sim:949 - Finished generation of ASY schematic symbol. Generating metadata file... Generating ISE project... XCO file found: chipscope_icon.xco XMDF file found: chipscope_icon_xmdf.tcl Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ icon.asy -view all -origin_type imported Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ icon.ngc -view all -origin_type created Checking file "/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope _icon.ngc" for project device match ... File "/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope _icon.ngc" device information matches project device. Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ icon.vhd -view all -origin_type created INFO:HDLCompiler:1061 - Parsing VHDL file "/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipsc ope_icon.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ icon.vho -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/chipscope_icon" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory Saved CGP file for project 'coregen'. Customize and GenerateINFO:sim:172 - Generating IP... WARNING:sim:100 - The Simulation File Type is not valid for this core. Overriding with File Type . Applying current project options... Finished applying current project options. Customizing IP... Release 14.7 - Xilinx CORE Generator IP GUI Launcher P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Finished Customizing. Generating IP... WARNING:sim:100 - The Simulation File Type is not valid for this core. Overriding with File Type . Configuring files for chipscope_vio root... Gathering HDL files for chipscope_vio root... Creating XST project for chipscope_vio... Creating XST script file for chipscope_vio... Creating XST instantiation file for chipscope_vio... Running XST for chipscope_vio... XST: HDL Parsing XST: HDL Elaboration XST: HDL Synthesis XST: Advanced HDL Synthesis XST: Low Level Synthesis XST: Design Summary Generating VHDL wrapper Not generating Verilog wrapper Creating ISE instantiation template for chipscope_vio... Skipping Verilog instantiation template for chipscope_vio... Finished Generation. Generating IP instantiation template... Generating ASY schematic symbol... INFO:sim:949 - Finished generation of ASY schematic symbol. Generating metadata file... Generating ISE project... XCO file found: chipscope_vio.xco XMDF file found: chipscope_vio_xmdf.tcl Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ vio.asy -view all -origin_type imported Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ vio.ngc -view all -origin_type created Checking file "/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope _vio.ngc" for project device match ... File "/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope _vio.ngc" device information matches project device. Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ vio.vhd -view all -origin_type created INFO:HDLCompiler:1061 - Parsing VHDL file "/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipsc ope_vio.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/tmp/_cg/chipscope_ vio.vho -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/chipscope_vio" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory Saved CGP file for project 'coregen'. Closed project file.