The following files were generated for 'chipscope_vio' in directory
/home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/ipcore_dir/

XCO file generator:
   Generate an XCO file for compatibility with legacy flows.

   * chipscope_vio.xco

Creates an implementation netlist:
   Creates an implementation netlist for the IP.

   * chipscope_vio.cdc
   * chipscope_vio.constraints/chipscope_vio.ucf
   * chipscope_vio.constraints/chipscope_vio.xdc
   * chipscope_vio.ngc
   * chipscope_vio.ucf
   * chipscope_vio.vhd
   * chipscope_vio.vho
   * chipscope_vio.xdc
   * chipscope_vio_xmdf.tcl

Creates an HDL instantiation template:
   Creates an HDL instantiation template for the IP.

   * chipscope_vio.vho

IP Symbol Generator:
   Generate an IP symbol based on the current project options'.

   * chipscope_vio.asy

Generate ISE subproject:
   Create an ISE subproject for use when including this core in ISE designs

   * chipscope_vio.gise
   * chipscope_vio.xise

Deliver Readme:
   Readme file for the IP.

   * chipscope_vio_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * chipscope_vio_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.