##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Tue Dec  1 06:51:26 2020
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=16
CSET asynchronous_output_port_width=8
CSET component_name=chipscope_vio
CSET constraint_type=external
CSET enable_asynchronous_input_port=true
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=false
CSET example_design=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T14:13:48Z
# END Extra information
GENERATE
# CRC: 4cf0f523