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-- Company: 
-- Engineer:
--
-- Create Date:   10:42:59 12/03/2020
-- Design Name:   
-- Module Name:   /home/ise/D_DRIVE/Design_collection/AMC13_fw/T2new/icap_tb.vhd
-- Project Name:  T2New
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: reboot
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY icap_tb IS
END icap_tb;
 
ARCHITECTURE behavior OF icap_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT reboot
    PORT(
         rst : IN  std_logic;
         ICAP_clk : IN  std_logic;
         reprogs6 : IN  std_logic
        );
    END COMPONENT;
component ICAP_SP605_reboot
	PORT(
		clk : IN std_logic;
		MBT_RESET : IN std_logic;
		MBT_REBOOT : IN std_logic;
		MBT_BUSY : OUT std_logic;
		ICAP_DOUT : OUT std_logic_vector(15 downto 0)
		);
END COMPONENT;
    

   --Inputs
   signal rst : std_logic := '1';
   signal ICAPclk : std_logic := '0';
   signal reprogs6 : std_logic := '0';

   -- Clock period definitions
   constant ICAPclk_period : time := 10 ns;
 
BEGIN
--I_ICAP : ICAP_SP605_reboot
--	PORT map(
--		clk => ICAPclk,
--		MBT_RESET => rst,
--		MBT_REBOOT => reprogs6,
--		MBT_BUSY => open,
--		ICAP_DOUT => open
--		);
 
	-- Instantiate the Unit Under Test (UUT)
   uut: reboot PORT MAP (
          rst => rst,
          ICAP_clk => ICAPclk,
          reprogs6 => reprogs6
        );

   -- Clock process definitions
   ICAPclk_process :process
   begin
		ICAPclk <= '0';
		wait for ICAPclk_period/2;
		ICAPclk <= '1';
		wait for ICAPclk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
rst <= '0';
      wait for ICAPclk_period*10;
reprogs6 <= '1';
      wait for ICAPclk_period;
reprogs6 <= '0';
      -- insert stimulus here 

      wait;
   end process;

END;