---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:32:13 05/16/2011 -- Design Name: -- Module Name: GTP - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.std_logic_misc.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity GTP_if is Port ( sysclk : in STD_LOGIC; sysclk2x : in STD_LOGIC; S6LinkGTPreset : in STD_LOGIC; S6LinkCDRreset : in STD_LOGIC; GbEGTPreset : in STD_LOGIC; REFCLK_P : in STD_LOGIC; REFCLK_N : in STD_LOGIC; LINK_RXP : in STD_LOGIC; LINK_RXN : in STD_LOGIC; GbE_RXP : in STD_LOGIC; GbE_RXN : in STD_LOGIC; T1_ready : out STD_LOGIC; LINK_TXP : out STD_LOGIC; LINK_TXN : out STD_LOGIC; GbE_TXP : out STD_LOGIC; GbE_TXN : out STD_LOGIC; debug_in : in STD_LOGIC_VECTOR(31 downto 0); debug_out : out STD_LOGIC_VECTOR(31 downto 0); LINKtxdata : in STD_LOGIC_VECTOR(15 downto 0); LINKtxcharisk : in STD_LOGIC_VECTOR(1 downto 0); LINKrxdata : out STD_LOGIC_VECTOR(15 downto 0); Link_RXBYTEISALIGNED : out STD_LOGIC; LINKrxchariscomma : out STD_LOGIC_VECTOR(1 downto 0); LINKrxcharisk : out STD_LOGIC_VECTOR(1 downto 0); -- EMAC signals GbEtxdvld : in STD_LOGIC; GbEtxd : in STD_LOGIC_VECTOR(7 downto 0); GbEtxdlast : in STD_LOGIC; GbEtxerr : in STD_LOGIC; GbEtxready : out STD_LOGIC; GbErxd : out STD_LOGIC_VECTOR(7 downto 0); GbErxdvld : out STD_LOGIC; GbErxdlast : out STD_LOGIC; GbErxerr : out STD_LOGIC; GTPCLKOUT : out STD_LOGIC; LINKpllLock : out STD_LOGIC ); end GTP_if; architecture Behavioral of GTP_if is component chipscope_icon PORT ( CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)); end component; component chipscope_ila PORT ( CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); CLK : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)); end component; component chipscope_vio PORT ( CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); CLK : IN STD_LOGIC; ASYNC_IN : IN STD_LOGIC_VECTOR(63 DOWNTO 0); SYNC_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); end component; component S6Link_GbE generic ( -- Simulation attributes WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation ); port ( --_________________________________________________________________________ --_________________________________________________________________________ --TILE0 (X0_Y0) ------------------------ Loopback and Powerdown Ports ---------------------- TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0); TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0); TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); --------------------------------- PLL Ports -------------------------------- TILE0_CLK00_IN : in std_logic; TILE0_CLK01_IN : in std_logic; TILE0_GTPRESET0_IN : in std_logic; TILE0_GTPRESET1_IN : in std_logic; TILE0_PLLLKDET0_OUT : out std_logic; TILE0_PLLLKDET1_OUT : out std_logic; TILE0_REFCLKOUT1_OUT : out std_logic; TILE0_RESETDONE0_OUT : out std_logic; TILE0_RESETDONE1_OUT : out std_logic; ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE0_RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISCOMMA1_OUT : out std_logic; TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK1_OUT : out std_logic; TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); TILE0_RXDISPERR1_OUT : out std_logic; TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); TILE0_RXNOTINTABLE1_OUT : out std_logic; TILE0_RXRUNDISP1_OUT : out std_logic; ---------------------- Receive Ports - Clock Correction -------------------- TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- TILE0_RXBYTEISALIGNED0_OUT : out std_logic; TILE0_RXBYTEREALIGN0_OUT : out std_logic; TILE0_RXCOMMADET0_OUT : out std_logic; TILE0_RXENMCOMMAALIGN0_IN : in std_logic; TILE0_RXENMCOMMAALIGN1_IN : in std_logic; TILE0_RXENPCOMMAALIGN0_IN : in std_logic; TILE0_RXENPCOMMAALIGN1_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE0_RXDATA1_OUT : out std_logic_vector(7 downto 0); TILE0_RXRECCLK1_OUT : out std_logic; TILE0_RXRESET1_IN : in std_logic; TILE0_RXUSRCLK0_IN : in std_logic; TILE0_RXUSRCLK1_IN : in std_logic; TILE0_RXUSRCLK20_IN : in std_logic; TILE0_RXUSRCLK21_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE0_RXCDRRESET0_IN : in std_logic; TILE0_RXN0_IN : in std_logic; TILE0_RXN1_IN : in std_logic; TILE0_RXP0_IN : in std_logic; TILE0_RXP1_IN : in std_logic; ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- TILE0_RXBUFRESET1_IN : in std_logic; TILE0_RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0); ---------------------------- TX/RX Datapath Ports -------------------------- TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0); TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0); ------------------- Transmit Ports - 8b10b Encoder Control ----------------- TILE0_TXCHARDISPMODE1_IN : in std_logic; TILE0_TXCHARDISPVAL1_IN : in std_logic; TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0); TILE0_TXCHARISK1_IN : in std_logic; --------------- Transmit Ports - TX Buffer and Phase Alignment ------------- TILE0_TXBUFSTATUS1_OUT : out std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0); TILE0_TXDATA1_IN : in std_logic_vector(7 downto 0); TILE0_TXOUTCLK0_OUT : out std_logic; TILE0_TXOUTCLK1_OUT : out std_logic; TILE0_TXRESET1_IN : in std_logic; TILE0_TXUSRCLK0_IN : in std_logic; TILE0_TXUSRCLK1_IN : in std_logic; TILE0_TXUSRCLK20_IN : in std_logic; TILE0_TXUSRCLK21_IN : in std_logic; --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE0_TXN0_OUT : out std_logic; TILE0_TXN1_OUT : out std_logic; TILE0_TXP0_OUT : out std_logic; TILE0_TXP1_OUT : out std_logic ); end component; COMPONENT soft_emac PORT( reset : IN std_logic; phyemacrxd : IN std_logic_vector(7 downto 0); phyemacrxdv : IN std_logic; phyemacrxer : IN std_logic; clientemactxd : IN std_logic_vector(7 downto 0); clientemactxdvld : IN std_logic; clientemactxdlast : IN std_logic; clientemactxerr : IN std_logic; txgmiimiiclk : IN std_logic; rxgmiimiiclk : IN std_logic; emacphytxd : OUT std_logic_vector(7 downto 0); emacphytxen : OUT std_logic; emacphytxer : OUT std_logic; emacclienttxready : OUT std_logic; emacclientrxd : OUT std_logic_vector(7 downto 0); emacclientrxdvld : OUT std_logic; emacclientrxdlast : OUT std_logic; emacclientrxerr : OUT std_logic ); END COMPONENT; component gig_eth_pcs_pma_v11_1 port ( reset: in std_logic; signal_detect: in std_logic; mgt_rx_reset: out std_logic; mgt_tx_reset: out std_logic; userclk: in std_logic; userclk2: in std_logic; dcm_locked: in std_logic; rxbufstatus: in std_logic_vector(1 downto 0); rxchariscomma: in std_logic; rxcharisk: in std_logic; rxclkcorcnt: in std_logic_vector(2 downto 0); rxdata: in std_logic_vector(7 downto 0); rxdisperr: in std_logic; rxnotintable: in std_logic; rxrundisp: in std_logic; txbuferr: in std_logic; powerdown: out std_logic; txchardispmode: out std_logic; txchardispval: out std_logic; txcharisk: out std_logic; txdata: out std_logic_vector(7 downto 0); enablealign: out std_logic; gmii_txd: in std_logic_vector(7 downto 0); gmii_tx_en: in std_logic; gmii_tx_er: in std_logic; gmii_rxd: out std_logic_vector(7 downto 0); gmii_rx_dv: out std_logic; gmii_rx_er: out std_logic; gmii_isolate: out std_logic; configuration_vector: in std_logic_vector(3 downto 0); status_vector: out std_logic_vector(15 downto 0)); end component; signal gmii_txd : std_logic_vector(7 downto 0) := (others =>'0'); signal gmii_rxd : std_logic_vector(7 downto 0) := (others =>'0'); signal gmii_tx_en : std_logic := '0'; signal gmii_tx_er : std_logic := '0'; signal gmii_rx_dv : std_logic := '0'; signal gmii_rx_er : std_logic := '0'; signal gmii_isolate : std_logic := '0'; signal GTPCLKOUT1 : std_logic_vector(1 downto 0) := (others =>'0'); signal LINKresetDone : std_logic := '0'; signal LINKrxdisperr : std_logic_vector(1 downto 0) := (others =>'0'); signal LINKrxchariscomma_i : std_logic_vector(1 downto 0) := (others =>'0'); signal LINKrxnotintable : std_logic_vector(1 downto 0) := (others =>'0'); signal LINKrxbyteisaligned : std_logic := '0'; signal LINKrxbyterealign : std_logic := '0'; signal LINKcommaDet : std_logic := '0'; signal LINKenablealign : std_logic := '0'; --signal LINKcommaDet : std_logic := '0'; --signal LINKcommaDet : std_logic := '0'; signal GbErxdata : std_logic_vector(7 downto 0) := (others =>'0'); signal GbEtxdata : std_logic_vector(7 downto 0) := (others =>'0'); signal GbErxbufstatus : std_logic_vector(1 downto 0) := (others =>'0'); signal GbEtxbufstatus : std_logic_vector(1 downto 0) := (others =>'0'); signal GbErxclkcorcnt : std_logic_vector(2 downto 0) := (others =>'0'); --signal GbErxbufstatus : std_logic_vector(2 downto 0) := (others =>'0'); --signal GbErxbufstatus : std_logic_vector(2 downto 0) := (others =>'0'); --signal GbErxrundisp : std_logic_vector(7 downto 0) := (others =>'0'); signal powerdown : std_logic := '0'; signal TILE0_POWERDOWN : std_logic_vector(1 downto 0) := (others =>'0'); signal GbEtx_reset : std_logic := '0'; signal GbErx_reset : std_logic := '0'; signal GbEtxcharisk : std_logic := '0'; signal GbErxcharisk : std_logic := '0'; signal REFCLK : std_logic := '0'; signal GbEpllLock : std_logic := '0'; signal GbEresetDone : std_logic := '0'; signal GbErxchariscomma : std_logic := '0'; signal GbErxdisperr : std_logic := '0'; signal GbEtxchardispval : std_logic := '0'; signal GbEtxchardispmode : std_logic := '0'; signal GbErxrundisp : std_logic := '0'; signal GbEenablealign : std_logic := '0'; signal GbErxnotintable : std_logic := '0'; signal wait_cntr : std_logic_vector(15 downto 0) := (others =>'0'); signal TILE0_RXBUFSTATUS1 : std_logic_vector(2 downto 0) := (others =>'0'); signal TILE0_TXBUFSTATUS1 : std_logic_vector(1 downto 0) := (others =>'0'); signal control0 : std_logic_vector(35 downto 0) := (others =>'0'); signal control1 : std_logic_vector(35 downto 0) := (others =>'0'); signal cs_data : std_logic_vector(31 downto 0) := (others =>'0'); signal cs_trig : std_logic_vector(7 downto 0) := (others =>'0'); signal cs_sync_out : std_logic_vector(31 downto 0) := (others =>'0'); signal cs_async_in : std_logic_vector(63 downto 0) := (others =>'0'); attribute KEEP : string; attribute KEEP of GbEresetDone : signal is "TRUE"; begin GTPCLKOUT <= GTPCLKOUT1(0); T1_ready <= wait_cntr(15); LINKrxchariscomma <= LINKrxchariscomma_i; process(sysclk,GbEGTPreset) begin if(GbEGTPreset = '1')then wait_cntr <= (others => '0'); elsif(sysclk'event and sysclk = '1')then if(LINKrxnotintable /= "00")then wait_cntr <= (others => '0'); elsif(wait_cntr(15) = '0' and LINKrxchariscomma_i(0) = '1')then wait_cntr <= wait_cntr + 1; end if; end if; end process; i_mac: soft_emac port map( reset => GbEGTPreset, emacphytxd => gmii_txd, emacphytxen => gmii_tx_en, emacphytxer => gmii_tx_er, phyemacrxd => gmii_rxd, phyemacrxdv => gmii_rx_dv, phyemacrxer => gmii_rx_er, clientemactxd => GbEtxd, clientemactxdvld => GbEtxdvld, clientemactxdlast => GbEtxdlast, clientemactxerr => GbEtxerr, emacclienttxready => GbEtxready, emacclientrxd => GbErxd, emacclientrxdvld => GbErxdvld, emacclientrxdlast => GbErxdlast, emacclientrxerr => GbErxerr, txgmiimiiclk => sysclk, rxgmiimiiclk => sysclk ); i_GbE_pcs_pma : gig_eth_pcs_pma_v11_1 port map ( reset => GbEGTPreset, signal_detect => '1', mgt_rx_reset => GbErx_reset, mgt_tx_reset => GbEtx_reset, userclk => sysclk, userclk2 => sysclk, dcm_locked => GbEpllLock, rxbufstatus => GbErxbufstatus, rxchariscomma => GbErxchariscomma, rxcharisk => GbErxcharisk, rxclkcorcnt => GbErxclkcorcnt, rxdata => GbErxdata, rxdisperr => GbErxdisperr, rxnotintable => GbErxnotintable, rxrundisp => GbErxrundisp, txbuferr => TILE0_TXBUFSTATUS1(1), powerdown => powerdown, txchardispmode => GbEtxchardispmode, txchardispval => GbEtxchardispval, txcharisk => GbEtxcharisk, txdata => GbEtxdata, enablealign => GbEenablealign, gmii_txd => gmii_txd, gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_rxd => gmii_rxd, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_isolate => open, configuration_vector => x"0", status_vector => open); GbErxbufstatus <= TILE0_RXBUFSTATUS1(2) & '0'; TILE0_POWERDOWN <= powerdown & powerdown; i_S6Link_GbE : S6Link_GbE generic map ( WRAPPER_SIM_GTPRESET_SPEEDUP => 0, -- Set this to 1 for simulation WRAPPER_SIMULATION => 0 -- Set this to 1 for simulation ) port map ( --_____________________________________________________________________ --_____________________________________________________________________ --TILE0 (X0_Y0) ------------------------ Loopback and Powerdown Ports ---------------------- TILE0_LOOPBACK0_IN => "000", TILE0_LOOPBACK1_IN => "000", TILE0_RXPOWERDOWN1_IN => TILE0_POWERDOWN, TILE0_TXPOWERDOWN1_IN => TILE0_POWERDOWN, --------------------------------- PLL Ports -------------------------------- TILE0_CLK00_IN => REFCLK, TILE0_CLK01_IN => REFCLK, TILE0_GTPRESET0_IN => S6LinkGTPreset, TILE0_GTPRESET1_IN => GbEGTPreset, TILE0_PLLLKDET0_OUT => LINKpllLock, TILE0_PLLLKDET1_OUT => GbEpllLock, TILE0_REFCLKOUT1_OUT => open, TILE0_RESETDONE0_OUT => LINKresetDone, TILE0_RESETDONE1_OUT => GbEresetDone, ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE0_RXCHARISCOMMA0_OUT => LINKrxchariscomma_i, TILE0_RXCHARISCOMMA1_OUT => GbErxchariscomma, TILE0_RXCHARISK0_OUT => LINKrxcharisK, TILE0_RXCHARISK1_OUT => GbErxcharisk, TILE0_RXDISPERR0_OUT => open, TILE0_RXDISPERR1_OUT => GbErxdisperr, TILE0_RXNOTINTABLE0_OUT => Linkrxnotintable, TILE0_RXNOTINTABLE1_OUT => GbErxnotintable, TILE0_RXRUNDISP1_OUT => GbErxrundisp, ---------------------- Receive Ports - Clock Correction -------------------- TILE0_RXCLKCORCNT1_OUT => GbErxclkcorcnt, --------------- Receive Ports - Comma Detection and Alignment -------------- TILE0_RXBYTEISALIGNED0_OUT => Link_RXBYTEISALIGNED, TILE0_RXBYTEREALIGN0_OUT => open, TILE0_RXCOMMADET0_OUT => open, TILE0_RXENMCOMMAALIGN0_IN => '1', TILE0_RXENMCOMMAALIGN1_IN => GbEenablealign, TILE0_RXENPCOMMAALIGN0_IN => '1', TILE0_RXENPCOMMAALIGN1_IN => GbEenablealign, ------------------- Receive Ports - RX Data Path interface ----------------- TILE0_RXDATA0_OUT => LINKrxdata, TILE0_RXDATA1_OUT => GbErxdata, TILE0_RXRECCLK1_OUT => open, TILE0_RXRESET1_IN => GbErx_reset, TILE0_RXUSRCLK0_IN => sysclk2x, TILE0_RXUSRCLK1_IN => sysclk, TILE0_RXUSRCLK20_IN => sysclk, TILE0_RXUSRCLK21_IN => sysclk, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE0_RXCDRRESET0_IN => S6LinkCDRreset, TILE0_RXN0_IN => LINK_RXN, TILE0_RXN1_IN => GbE_RXN, TILE0_RXP0_IN => LINK_RXP, TILE0_RXP1_IN => GbE_RXP, ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- TILE0_RXBUFRESET1_IN => GbErx_reset, TILE0_RXBUFSTATUS1_OUT => TILE0_RXBUFSTATUS1, ---------------------------- TX/RX Datapath Ports -------------------------- TILE0_GTPCLKOUT0_OUT => open, TILE0_GTPCLKOUT1_OUT => GTPCLKOUT1, ------------------- Transmit Ports - 8b10b Encoder Control ----------------- TILE0_TXCHARDISPMODE1_IN => GbEtxchardispmode, TILE0_TXCHARDISPVAL1_IN => GbEtxchardispval, TILE0_TXCHARISK0_IN => LINKtxcharisK, TILE0_TXCHARISK1_IN => GbEtxcharisK, --------------- Transmit Ports - TX Buffer and Phase Alignment ------------- TILE0_TXBUFSTATUS1_OUT => TILE0_TXBUFSTATUS1, ------------------ Transmit Ports - TX Data Path interface ----------------- TILE0_TXDATA0_IN => LINKtxdata, TILE0_TXDATA1_IN => GbEtxdata, TILE0_TXOUTCLK0_OUT => open, TILE0_TXOUTCLK1_OUT => open, TILE0_TXRESET1_IN => GbEtx_reset, TILE0_TXUSRCLK0_IN => sysclk2x, TILE0_TXUSRCLK1_IN => sysclk, TILE0_TXUSRCLK20_IN => sysclk, TILE0_TXUSRCLK21_IN => sysclk, --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE0_TXN0_OUT => LINK_TXN, TILE0_TXN1_OUT => GbE_TXN, TILE0_TXP0_OUT => LINK_TXP, TILE0_TXP1_OUT => GbE_TXP ); -----------------------Dedicated GTP Reference Clock Inputs --------------- -- Each dedicated refclk you are using in your design will need its own IBUFDS instance tile0_refclk_ibufds_i : IBUFDS port map ( O => REFCLK, I => REFCLK_P, -- Connect to package pin A10 IB => REFCLK_N -- Connect to package pin B10 ); end Behavioral;