AMC13_T2 Project Status (12/05/2020 - 04:05:28) | |||
Project File: | T2New.xise | Parser Errors: | No Errors |
Module Name: | AMC13_T2 | Implementation State: | Programming File Generated |
Target Device: | xc6slx45t-2fgg484 |
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No Errors |
Product Version: | ISE 14.7 |
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1288 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [+] |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Dec 5 19:23:41 2020 | 0 | 1025 Warnings (0 new) | 49 Infos (0 new) | |
Translation Report | Current | Sat Dec 5 19:24:23 2020 | 0 | 242 Warnings (0 new) | 7 Infos (0 new) | |
Map Report | Current | Sat Dec 5 19:34:28 2020 | 0 | 8 Warnings (0 new) | 315 Infos (0 new) | |
Place and Route Report | Current | Sat Dec 5 19:39:29 2020 | 0 | 6 Warnings (0 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Sat Dec 5 19:40:18 2020 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Current | Sat Dec 5 19:41:48 2020 | 0 | 7 Warnings (0 new) | 2 Infos (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Sat Dec 5 01:02:28 2020 | |
Physical Synthesis Report | Current | Sat Dec 5 19:34:28 2020 | |
WebTalk Log File | Current | Sat Dec 5 19:41:53 2020 |