---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:49:29 05/12/2010 -- Design Name: -- Module Name: DTC_T2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- TTC Hamming encoding -- hmg[0] = d[0]^d[1]^d[2]^d[3]; -- hmg[1] = d[0]^d[4]^d[5]^d[6]; -- hmg[2] = d[1]^d[2]^d[4]^d[5]^d[7]; -- hmg[3] = d[1]^d[3]^d[4]^d[6]^d[7]; -- hmg[4] = d[0]^d[2]^d[3]^d[5]^d[6]^d[7]; ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.std_logic_misc.all; use work.ipbus.ALL; use work.ipbus_trans_decl.ALL; use work.amc13_pack.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; entity AMC13_T2 is Port ( REFCLK_P : in STD_LOGIC; -- 125MHz REFCLK_N : in STD_LOGIC; SN_IN : in STD_LOGIC_VECTOR(9 downto 0); -- FLASH interface FLASH_S : out STD_LOGIC; FLASH_S2 : out STD_LOGIC; FLASH_D : out STD_LOGIC; FLASH_Q : in STD_LOGIC; FLASH_C : out STD_LOGIC; -- TTC data outputs TxFB_p : out STD_LOGIC_VECTOR (12 downto 1); TxFB_n : out STD_LOGIC_VECTOR (12 downto 1); RxFB_p : in STD_LOGIC_VECTOR (12 downto 1); RxFB_n : in STD_LOGIC_VECTOR (12 downto 1); -- CLK1 enable CLK1_en : out STD_LOGIC_VECTOR (11 downto 0); -- MMC signals FSIO_SCK : in STD_LOGIC; FSIO_CS_B : inout STD_LOGIC_VECTOR(3 downto 0); FSIO_MISO : out STD_LOGIC; FSIO_MOSI : in STD_LOGIC; FSIO_SCAN : in STD_LOGIC; GPLED_B : in STD_LOGIC_VECTOR(3 downto 0); -- GTP in/out LINK_RXN : in STD_LOGIC; LINK_RXP : in STD_LOGIC; LINK_TXN : out STD_LOGIC; LINK_TXP : out STD_LOGIC; GbE_RXN : in STD_LOGIC; GbE_RXP : in STD_LOGIC; GbE_TXN : out STD_LOGIC; GbE_TXP : out STD_LOGIC; -- signal to/from AMC13_T1 SEL_TTC_CLK : out STD_LOGIC; TTC_REFCLK : in STD_LOGIC; TTC_CLK_p : in STD_LOGIC_VECTOR (3 downto 0); TTC_CLK_n : in STD_LOGIC_VECTOR (3 downto 0); TTCdata_p : in STD_LOGIC; TTCdata_n : in STD_LOGIC; T3_TCDS_aux1 : in STD_LOGIC; T3_TCDS_aux2 : in STD_LOGIC; T3_SCK : out STD_LOGIC; -- V2S_p : in STD_LOGIC; -- V2S_n : in STD_LOGIC; S2V_p : out STD_LOGIC; S2V_n : out STD_LOGIC; T1_SCK : out STD_LOGIC; T1_CS_B : out STD_LOGIC; T1_MISO : in STD_LOGIC; T1_MOSI : out STD_LOGIC; V6_CDATA : out STD_LOGIC; V6_CCLK : out STD_LOGIC; V6_PROG_B : out STD_LOGIC; V6_INIT_B : in STD_LOGIC; V6_DONE : in STD_LOGIC); end AMC13_T2; architecture Behavioral of AMC13_T2 is COMPONENT GTP_if PORT( sysclk : IN std_logic; sysclk2x : IN std_logic; S6LinkGTPreset : IN std_logic; S6LinkCDRreset : IN std_logic; GbEGTPreset : IN std_logic; REFCLK_P : IN std_logic; REFCLK_N : IN std_logic; LINK_RXP : IN std_logic; LINK_RXN : IN std_logic; GbE_RXP : IN std_logic; GbE_RXN : IN std_logic; debug_in : IN std_logic_vector(31 downto 0); LINKtxdata : IN std_logic_vector(15 downto 0); LINKtxcharisk : IN std_logic_vector(1 downto 0); GbEtxdvld : IN std_logic; GbEtxd : IN std_logic_vector(7 downto 0); GbEtxdlast : IN std_logic; GbEtxerr : IN std_logic; T1_ready : OUT std_logic; LINK_TXP : OUT std_logic; LINK_TXN : OUT std_logic; GbE_TXP : OUT std_logic; GbE_TXN : OUT std_logic; debug_out : OUT std_logic_vector(31 downto 0); LINKrxdata : OUT std_logic_vector(15 downto 0); Link_RXBYTEISALIGNED : OUT std_logic; LINKrxchariscomma : OUT std_logic_vector(1 downto 0); LINKrxcharisk : OUT std_logic_vector(1 downto 0); GbEtxready : OUT std_logic; GbErxd : OUT std_logic_vector(7 downto 0); GbErxdvld : OUT std_logic; GbErxdlast : OUT std_logic; GbErxerr : OUT std_logic; GTPCLKOUT : OUT std_logic; LINKpllLock : OUT std_logic ); END COMPONENT; COMPONENT SPI_if Port ( SCK : in STD_LOGIC; CSn : in STD_LOGIC; MOSI : in STD_LOGIC; MISO : out STD_LOGIC; SN : in STD_LOGIC_VECTOR (8 downto 0); IsT1 : in STD_LOGIC; OT : in STD_LOGIC; newIPADDR : out STD_LOGIC; SPI_we : out STD_LOGIC; en_RARP : out STD_LOGIC; IPADDR : out STD_LOGIC_VECTOR (31 downto 0); SPI_rdata : in STD_LOGIC_VECTOR (7 downto 0); SPI_wdata : out STD_LOGIC_VECTOR (7 downto 0); SPI_addr : out STD_LOGIC_VECTOR (7 downto 0)); END COMPONENT; COMPONENT BRAM_8 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT flash PORT( clk : IN std_logic; sysclk : IN std_logic; we : IN std_logic; strobe : IN std_logic; w_data : IN std_logic_vector(31 downto 0); addr : IN std_logic_vector(31 downto 0); MQ : IN std_logic; flash_wdata : OUT std_logic_vector(31 downto 0); flash_rdata : OUT std_logic_vector(31 downto 0); flash_busy : OUT std_logic; MD : OUT std_logic; MCS : OUT std_logic_vector(1 downto 0) ); END COMPONENT; COMPONENT LinkFIFO PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(8 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT ipbus_ctrl generic( MAC_CFG: ipb_mac_cfg := EXTERNAL; IP_CFG: ipb_ip_cfg := EXTERNAL; -- Number of address bits to select RX or TX buffer in UDP I/F -- Number of RX and TX buffers is 2**BUFWIDTH BUFWIDTH: natural := 4; -- Numer of address bits to select internal buffer in UDP I/F -- Number of internal buffers is 2**INTERNALWIDTH INTERNALWIDTH: natural := 1; -- Number of address bits within each buffer in UDP I/F -- Size of each buffer is 2**ADDRWIDTH ADDRWIDTH: natural := 11; -- UDP port for IPbus traffic in this instance of UDP I/F IPBUSPORT: std_logic_vector(15 DOWNTO 0) := x"C351"; -- Flag whether this UDP I/F instance ignores everything except IPBus traffic SECONDARYPORT: std_logic := '0'; N_OOB: natural := 0 ); port( mac_clk: in std_logic; -- Ethernet MAC clock (125MHz) rst_macclk: in std_logic; -- MAC clock domain sync reset ipb_clk: in std_logic; -- IPbus clock rst_ipb: in std_logic; -- IPbus clock domain sync reset mac_rx_data: in std_logic_vector(7 downto 0); -- AXI4 style MAC signals mac_rx_valid: in std_logic; mac_rx_last: in std_logic; mac_rx_error: in std_logic; mac_tx_data: out std_logic_vector(7 downto 0); mac_tx_valid: out std_logic; mac_tx_last: out std_logic; mac_tx_error: out std_logic; mac_tx_ready: in std_logic; ipb_out: out ipb_wbus; -- IPbus bus signals ipb_in: in ipb_rbus; ipb_req: out std_logic; ipb_grant: in std_logic := '1'; mac_addr: in std_logic_vector(47 downto 0) := X"000000000000"; -- Static MAC and IP addresses ip_addr: in std_logic_vector(31 downto 0) := X"00000000"; enable: in std_logic := '1'; RARP_select: in std_logic := '0'; pkt_rx: out std_logic; pkt_tx: out std_logic; pkt_rx_led: out std_logic; pkt_tx_led: out std_logic; oob_in: in ipbus_trans_in_array(N_OOB - 1 downto 0) := (others => ('0', X"00000000", '0')); oob_out: out ipbus_trans_out_array(N_OOB - 1 downto 0) ); END COMPONENT; COMPONENT trig_data PORT( clk : IN std_logic; din : IN std_logic; din_polarity : IN std_logic; dl : IN std_logic_vector(7 downto 0); twinmux_ra : OUT std_logic; buffer_dinA : OUT std_logic; buffer_dinB : OUT std_logic ); END COMPONENT; component ICAP_SP605_reboot PORT( clk : IN std_logic; MBT_RESET : IN std_logic; MBT_REBOOT : IN std_logic; MBT_BUSY : OUT std_logic; ICAP_DOUT : OUT std_logic_vector(15 downto 0) ); END COMPONENT; COMPONENT reboot PORT( rst : IN std_logic; ICAP_clk : IN std_logic; reprogs6 : IN std_logic ); END COMPONENT; constant zero : std_logic_vector(31 downto 0) := (others =>'0'); constant twinmux_addr : std_logic_vector(15 downto 0) := x"0200"; constant SPI_data_addr: std_logic_vector(7 downto 0) := x"04"; constant SPI_IP_addr: std_logic_vector(7 downto 0) := x"08"; constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0"; constant TxFB_pol : std_logic_vector(11 downto 0) := x"000"; constant RxFB_pol : std_logic_vector(11 downto 0) := x"000"; constant V6_Tx_pol : std_logic_vector(1 downto 0) := "11"; constant V6_Rx_pol : std_logic_vector(1 downto 0) := "00"; constant TTCclk_pol : std_logic := '0'; constant TTCdata_pol : std_logic := '0'; constant TTS_pol : std_logic := '1'; constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000"; constant amc_en_addr : std_logic_vector(15 downto 0) := x"0002"; type array17x32 is array(0 to 16) of bit_vector(31 downto 0); constant cmd_list_INIT : array17x32 := (x"00000001",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000", x"00000000",x"00000001",x"00000000",x"00000001",x"00000000",x"00000000",x"00000000",x"00000001"); signal SN : std_logic_vector(8 downto 0) := (others =>'0'); signal FSIO_CS_O : std_logic_vector(3 downto 0) := (others =>'0'); signal FSIO_CS_I : std_logic_vector(3 downto 0) := (others =>'0'); signal S6_SCK : std_logic := '0'; signal S6_CS_B : std_logic := '0'; signal S6_MOSI : std_logic := '0'; signal S6_MISO : std_logic := '0'; signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0'); signal GTPCLKOUT : std_logic := '0'; signal sysclk_in : std_logic := '0'; signal sysclk : std_logic := '0'; signal sysclk_dcm : std_logic := '0'; signal sysclk2x : std_logic := '0'; signal sysclk2x_dcm : std_logic := '0'; signal sysclk_dcm_locked : std_logic := '0'; signal DNA_clk : std_logic := '0'; signal DNA_div : std_logic_vector(4 downto 0) := (others =>'0'); signal ipb_clk : std_logic := '0'; signal ipb_clk_n : std_logic := '0'; signal ipb_clk_dcm : std_logic := '0'; signal rst_sysclk_dcm : std_logic := '0'; signal ICAP_clk : std_logic := '0'; signal ICAP_clk_dcm : std_logic := '0'; signal LINKPLLLOCK : std_logic := '0'; signal SN_high : std_logic := '0'; signal LINKrxdata : std_logic_vector(15 downto 0) := (others =>'0'); signal LINKrxdata_q : std_logic_vector(7 downto 0) := (others =>'0'); signal LINKtxdata : std_logic_vector(15 downto 0) := (others =>'0'); signal LINKrxchariscomma : std_logic_vector(1 downto 0) := (others =>'0'); signal LINKrxcharisk : std_logic_vector(1 downto 0) := (others =>'0'); signal LINKrxcharisk1_q : std_logic := '0'; signal LINKtxcharisk : std_logic_vector(1 downto 0) := (others =>'0'); signal Link_RXBYTEISALIGNED : std_logic := '1'; signal div : std_logic_vector(3 downto 0) := (others =>'0'); signal reset : std_logic := '0'; signal ipbus_txdvld : std_logic := '0'; signal ipbus_txready : std_logic := '0'; signal ipbus_txdlast : std_logic := '0'; signal ipbus_txerr : std_logic := '0'; signal ipbus_txd : std_logic_vector(7 downto 0) := (others =>'0'); signal S6LinkGTPreset : std_logic := '0'; signal GbEGTPreset : std_logic := '0'; signal sel_Link : std_logic := '0'; --signal readLink : std_logic := '0'; signal LinkFIFO_rst : std_logic := '1'; signal LinkFIFO_wep : std_logic := '0'; signal LinkFIFO_we : std_logic := '0'; signal LinkFIFO_re : std_logic := '0'; signal LinkFIFO_empty : std_logic := '0'; signal LinkFIFO_din : std_logic_vector(8 downto 0) := (others =>'0'); signal LinkFIFO_dout : std_logic_vector(8 downto 0) := (others =>'0'); signal GbEtxdvld : std_logic := '0'; signal GbEtxdlast : std_logic := '0'; signal GbEtxerr : std_logic := '0'; signal GbEtxready : std_logic := '0'; signal GbErxdvld : std_logic := '0'; signal GbErxdlast : std_logic := '0'; signal GbErxerr : std_logic := '0'; signal GbEtxd : std_logic_vector(7 downto 0) := (others =>'0'); signal GbErxd : std_logic_vector(7 downto 0) := (others =>'0'); signal GbErxdvld_q : std_logic := '0'; signal GbErxbadframe : std_logic := '0'; signal GbErxgoodframe : std_logic := '0'; signal GbErxbadframe_q : std_logic := '0'; signal GbErxgoodframe_q : std_logic := '0'; signal GbErxd_q : std_logic_vector(7 downto 0) := (others =>'0'); signal debug_in : std_logic_vector(31 downto 0) := (others =>'0'); signal debug_out : std_logic_vector(31 downto 0) := (others =>'0'); signal V2S : std_logic := '0'; signal S2V : std_logic := '0'; signal S2V_cntr : std_logic_vector(5 downto 0) := "110111"; signal S2V_sr : std_logic_vector(4 downto 0) := (others => '0'); signal GPLED_sync : std_logic_vector(3 downto 0) := (others => '0'); signal GPLED_sync2 : std_logic_vector(3 downto 0) := (others => '0'); signal clk_div : std_logic_vector(1 downto 0) := (others => '0'); signal LED_change : std_logic := '0'; signal rst_ipb : std_logic := '0'; signal rst_macclk : std_logic := '0'; signal rom_FAST_READ : std_logic := '0'; signal flash_md : std_logic := '0'; signal flash_mc : std_logic := '0'; signal flash_mcs : std_logic_vector(1 downto 0) := (others => '1'); signal V6_INIT_B_q : std_logic_vector(1 downto 0) := (others => '0'); signal reprogV6 : std_logic := '0'; signal reprogV6_dl : std_logic := '0'; signal inh_conf : std_logic := '0'; signal en_conf : std_logic := '0'; signal en_CCLK : std_logic := '0'; signal en_flash_c : std_logic := '0'; signal buffer_ack : std_logic := '0'; signal flash_busy : std_logic := '0'; signal flash_wdata : std_logic_vector(31 downto 0) := (others => '0'); signal flash_rdata : std_logic_vector(31 downto 0) := (others => '0'); signal rdata : std_logic_vector(31 downto 0) := (others => '0'); signal prog_V6_n : std_logic := '0'; signal conf_cntr : std_logic_vector(26 downto 0) := (others => '0'); signal conf_end : std_logic_vector(27 downto 0) := (others => '0'); signal rst_CRC : std_logic := '0'; signal calc_CRC : std_logic := '0'; signal M_Q : std_logic := '0'; signal CRC : std_logic_vector(23 downto 0) := (others => '0'); signal RxFB_in : std_logic_vector(12 downto 1) := (others => '0'); signal RxFB : std_logic_vector(11 downto 0) := (others => '0'); signal trig_in : std_logic_vector(13 downto 0) := (others => '0'); signal TxFB : std_logic_vector(12 downto 1) := (others => '0'); signal TxFB_D0 : std_logic_vector(11 downto 0) := (others => '0'); signal TxFB_D1 : std_logic_vector(11 downto 0) := (others => '0'); signal TxFB_T : std_logic_vector(12 downto 1) := (others => '0'); signal RxV6cmd : std_logic := '0'; signal rst_ipbus : std_logic := '0'; signal wr_amc_en : std_logic := '0'; signal RxV6Cntr : std_logic_vector(2 downto 0) := (others => '0'); signal amc_en : std_logic_vector(11 downto 0) := (others => '0'); signal amc_enp : std_logic_vector(11 downto 0) := (others => '0'); signal clk1_en_i : std_logic_vector(11 downto 0) := (others => '0'); --signal TTCclk_in : std_logic := '0'; signal CLKFB : std_logic := '0'; signal CLKFB_dcm : std_logic := '0'; signal TTCclk4x : std_logic := '0'; signal TTCclk4x_dcm : std_logic := '0'; signal TTCclk8x : std_logic := '0'; signal TTCclk8x_dcm : std_logic := '0'; signal TTCclk : std_logic := '0'; signal TTCclk_dcm : std_logic := '0'; signal TTCclk_n : std_logic := '0'; signal TTC_REFCLK_in : std_logic := '0'; signal TTCclk_in : std_logic_vector(3 downto 0) := (others =>'0'); signal TTCclkOut : std_logic_vector(3 downto 0) := (others =>'0'); signal TTCclkOut_dcm : std_logic_vector(3 downto 0) := (others =>'0'); signal TTCclkOutn : std_logic_vector(3 downto 0) := (others =>'0'); signal rst_TTC1 : std_logic := '0'; signal rst_TTC : std_logic := '0'; signal TTC_STATUS : std_logic_vector(7 downto 0) := (others => '0'); signal TTC_lock : std_logic := '0'; signal TTCdata_in : std_logic := '0'; signal TTCdata : std_logic_vector(3 downto 0) := (others => '0'); signal TTC_data : std_logic_vector(2 downto 0) := (others => '0'); signal L1A : std_logic := '0'; signal sr : std_logic_vector(12 downto 0) := (others => '0'); signal rec_cntr : std_logic_vector(5 downto 0) := (others => '0'); signal rec_cmd : std_logic := '0'; signal FMT : std_logic := '0'; signal brcst_str : std_logic_vector(3 downto 0) := (others => '0'); signal brcst_data : std_logic_vector(7 downto 0) := (others => '0'); signal brcst_syn : std_logic_vector(4 downto 0) := (others => '0'); signal Brcst : std_logic_vector(7 downto 0) := (others => '0'); signal frame_err : std_logic := '0'; signal single_err : std_logic := '0'; signal double_err : std_logic := '0'; signal EvCntRes : std_logic := '0'; signal BCntRes : std_logic := '0'; signal OCntRes : std_logic := '0'; signal SinErrStr : std_logic := '0'; signal DbErrStr : std_logic := '0'; signal L1Accept : std_logic := '0'; signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0'); signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0'); signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0'); signal Event_nr : std_logic_vector(23 downto 0) := x"000001"; signal Bcnt : std_logic_vector(11 downto 0) := (others =>'0'); signal OC_cnt : std_logic_vector(31 downto 0) := (others =>'0'); signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0'); signal L1A_cnt : std_logic_vector(15 downto 0) := (others =>'0'); signal BC0_cnt : std_logic_vector(15 downto 0) := (others =>'0'); signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0'); signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0'); signal ipb_master_out : ipb_wbus; signal ipb_master_in : ipb_rbus; signal T1_ready : std_logic := '0'; signal reprogS6 : std_logic := '0'; signal reprogS6_dl : std_logic_vector(3 downto 0) := (others =>'0'); signal rebootS6 : std_logic := '0'; signal DNA_out : std_logic := '0'; signal shift_DNA : std_logic := '0'; signal load_DNA : std_logic_vector(1 downto 0) := (others =>'0'); signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0'); signal DNA : std_logic_vector(56 downto 0) := (others =>'0'); signal ipbclk_cntr : std_logic_vector(19 downto 0) := (others =>'0'); signal ipbclk_cntr19_sync : std_logic_vector(3 downto 0) := (others =>'0'); signal TTC_cntr : std_logic_vector(19 downto 0) := (others =>'0'); signal F_TTC : std_logic_vector(19 downto 0) := (others =>'0'); signal en_RARP : std_logic := '0'; signal pulse : std_logic := '0'; signal T3_L1A_sync : std_logic_vector(3 downto 0) := (others =>'0'); signal T3_L1A_cnt : std_logic_vector(15 downto 0) := (others =>'0'); signal inc_TTCcmdCntr : std_logic_vector(15 downto 0) := (others =>'0'); type array16X16 is array(0 to 15) of std_logic_vector(15 downto 0); signal TTCcmdCntr : array16x16; signal TTC_CMD : std_logic_vector(7 downto 0) := (others =>'0'); signal TTC_OrN : std_logic_vector(31 downto 0) := (others =>'0'); signal TTC_BcN : std_logic_vector(11 downto 0) := (others =>'0'); signal TTC_EvN : std_logic_vector(23 downto 0) := (others =>'0'); signal cmd_list_wa : std_logic_vector(3 downto 0) := (others =>'0'); signal cmd_list_wap : std_logic_vector(3 downto 0) := (others =>'0'); signal cmd_list_ra : std_logic_vector(3 downto 0) := (others =>'0'); signal cmd_list : std_logic_vector(16 downto 0) := (others =>'0'); signal cmd_list_SP : std_logic_vector(16 downto 0) := (others =>'0'); signal cmd_list_di : std_logic_vector(16 downto 0) := (others =>'0'); signal cmd_list_we : std_logic := '0'; signal TTC_history_di : std_logic_vector(75 downto 0) := (others =>'0'); signal TTC_history_do : std_logic_vector(75 downto 0) := (others =>'0'); signal TTC_history_wa : std_logic_vector(8 downto 0) := (others =>'0'); signal TTC_history_ra : std_logic_vector(8 downto 0) := (others =>'0'); signal TTC_history_we : std_logic := '0'; signal chk_cmd_list : std_logic := '0'; signal clear_TTC_history : std_logic := '0'; signal TTC_history_full : std_logic := '0'; signal clear_cmd_list : std_logic := '0'; signal en_TTC_filter : std_logic := '1'; signal en_TTC_history : std_logic := '1'; signal OcNresetCmd : std_logic_vector(15 downto 0) := x"1728"; signal clk_toggle : std_logic := '0'; signal clk_toggle_q : std_logic := '0'; signal catch_twinmux : std_logic := '0'; signal catch_twinmuxSync : std_logic_vector(2 downto 0) := (others => '0'); signal en_twinmux : std_logic := '0'; signal T3_SCK_o : std_logic := '0'; signal en_trig : std_logic := '0'; signal TTCclkPhase : std_logic_vector(3 downto 1) := (others => '0'); signal delay_TRIG0 : std_logic_vector(7 downto 0) := (others => '0'); signal delay_TRIG1 : std_logic_vector(7 downto 0) := (others => '0'); signal delay_twinmux : array12x8 := (others => (others => '0')); signal twinmux : std_logic_vector(0 downto 0) := (others => '0'); signal twinmux_data : std_logic_vector(31 downto 0) := (others => '0'); signal twinmux_ra : std_logic_vector(13 downto 0) := (others => '0'); signal twinmux_wa : std_logic_vector(8 downto 0) := (others => '0'); signal twinmux_web : std_logic_vector(3 downto 0) := (others => '0'); signal buffer_di : std_logic_vector(31 downto 0) := (others =>'0'); signal buffer_do : std_logic_vector(15 downto 0) := (others =>'0'); signal buffer_wa : std_logic_vector(8 downto 0) := (others =>'0'); signal buffer_we : std_logic_vector(3 downto 0) := (others =>'0'); signal TTCclk_toggle : std_logic := '0'; signal TTCclk_toggle_q : std_logic := '0'; attribute IOB : string; attribute IOB of T3_SCK_o : signal is "true"; begin FLASH_S2 <= 'Z'; SN(7 downto 0) <= SN_IN(7 downto 0); SN(8) <= '0' when SN_IN(9) = '0' else SN_IN(8); SEL_TTC_CLK <= '1'; T3_SCK <= T3_SCK_o when en_twinmux = '1' else 'Z'; -- SPI interface g_FSIO_CS_B: for i in 0 to 3 generate i_FSIO_CS_B : IOBUF port map ( O => FSIO_CS_I(i), -- Buffer output IO => FSIO_CS_B(i), -- Buffer inout port (connect directly to top-level port) I => FSIO_CS_O(i), -- Buffer input T => FSIO_SCAN -- 3-state enable input, high=input, low=output ); end generate; FSIO_CS_O(0) <= '0'; FSIO_CS_O(1) <= not (V6_DONE and T1_ready); FSIO_CS_O(2) <= '1'; FSIO_CS_O(3) <= '1'; FSIO_MISO <= S6_MISO when FSIO_CS_I(0) = '0' else T1_MISO when FSIO_CS_I(1) = '0' else 'Z'; T1_SCK <= FSIO_SCK; T1_MOSI <= FSIO_MOSI; T1_CS_B <= FSIO_CS_I(1); S6_MOSI <= FSIO_MOSI; S6_CS_B <= FSIO_CS_I(0); i_S6_SCK: bufg port map(i => FSIO_SCK, o => S6_SCK); i_SPI_if: SPI_if PORT MAP( SCK => S6_SCK, CSn => S6_CS_B, MOSI => S6_MOSI, MISO => S6_MISO, SN => SN, IsT1 => '0', OT => '0', newIPADDR => open, SPI_we => open, en_RARP => en_RARP, IPADDR => IPADDR, SPI_rdata => (others => '0'), SPI_wdata => open, SPI_addr => open ); i_S2V: OBUFDS generic map(IOSTANDARD => "LVDS_25") port map (O => S2V_p, OB => S2V_n, I => S2V); S2V <= not T3_TCDS_aux1 or pulse; -- LVDS input/output buffers i_TTC_REFCLK_in: IBUFG port map(I => TTC_REFCLK, O => TTC_REFCLK_in); g_TTCclkOut: for i in 0 to 3 generate i_TTCclk_in: ibufgds generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_33") port map(i => TTC_CLK_p(i), ib => TTC_CLK_n(i), o => TTCclk_in(i)); i_DCM_TTCclkOut: DCM_SP generic map(CLKIN_PERIOD => 25.0,CLK_FEEDBACK => "1X",DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",CLKOUT_PHASE_SHIFT => "FIXED",PHASE_SHIFT => 35) port map ( CLKIN => TTCclk_in(i) , CLKFB => TTCclkOut(i) , RST => rst_TTC, LOCKED => open, -- DCM LOCK status output STATUS => open, -- 8-bit DCM status bits output DSSEN => '0' , PSINCDEC=> '0', PSEN => '0', PSCLK => '0', CLK0 => TTCclkOut_dcm(i)); i_TTCclk_buf: BUFG port map(I => TTCclkOut_dcm(i), O => TTCclkOut(i)); TTCclkOutn(i) <= not TTCclkOut(i); end generate; i_TTCdata: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_33") port map(i => TTCdata_p, ib => TTCdata_n, o => TTCdata_in); g_FB: for i in 1 to 12 generate i_RxFB: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_33") port map(i => RxFB_p(i), ib => RxFB_n(i), o => RxFB_in(i)); i_TxFB: OBUFTDS generic map(IOSTANDARD => "LVDS_33") port map (O => TxFB_p(i), OB => TxFB_n(i), I => TxFB(i), T => TxFB_T(i)); end generate; g_TxFB: for i in 0 to 11 generate i_TxFB : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '0', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => TxFB(i+1), -- 1-bit output data C0 => TTCclkOut(i/3), -- 1-bit clock input C1 => TTCclkOutn(i/3), -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => TTCdata(2), -- 1-bit data input (associated with C0) D1 => TTCdata(3), -- 1-bit data input (associated with C1) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); i_TxFB_T : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '1', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => TxFB_T(i+1), -- 1-bit output data C0 => TTCclkOut(i/3), -- 1-bit clock input C1 => TTCclkOutn(i/3), -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => not clk1_en_i(i), -- 1-bit data input (associated with C0) D1 => not clk1_en_i(i), -- 1-bit data input (associated with C1) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); end generate; process(TTCclk) begin if(TTCclk'event and TTCclk = '1')then TTCdata(3) <= TTCdata(1); end if; end process; process(TTCclk) begin if(TTCclk'event and TTCclk = '0')then TTCdata(2) <= TTCdata(0); end if; end process; i_rst_TTC : SRL16E generic map ( INIT => X"ffff") port map ( Q => rst_TTC1, -- SRL data output A0 => '1', -- Select[0] input A1 => '1', -- Select[1] input A2 => '1', -- Select[2] input A3 => '1', -- Select[3] input CE => '1', -- Clock enable input CLK => TTC_REFCLK_in, -- Clock input D => '0' -- SRL data input ); rst_TTC <= TTC_STATUS(1) or rst_TTC1 or not V6_DONE; i_DCM_TTCclk: PLL_BASE generic map ( CLKFBOUT_MULT => 24, -- Multiply value for all CLKOUT clock outputs (1-64) CLKFBOUT_PHASE => 56.25, -- Phase offset in degrees of the clock feedback output CLKIN_PERIOD => 24.948, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 -- MHz). -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128) CLKOUT0_DIVIDE => 24, CLKOUT1_DIVIDE => 6, CLKOUT2_DIVIDE => 3 ) port map ( CLKFBOUT => CLKFB_dcm, -- 1-bit output: PLL_BASE feedback output -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs CLKOUT0 => TTCclk_dcm, CLKOUT1 => TTCclk4x_dcm, CLKOUT2 => TTCclk8x_dcm, LOCKED => TTC_lock, -- 1-bit output: PLL_BASE lock status output CLKFBIN => CLKFB, -- 1-bit input: Feedback clock input CLKIN => TTC_REFCLK_in, -- 1-bit input: Clock input RST => rst_TTC -- 1-bit input: Reset input ); i_CLKFB: bufg port map(i => CLKFB_dcm, o => CLKFB); i_TTCclk: bufg port map(i => TTCclk_dcm, o => TTCclk); i_TTCclk4x: bufgce port map(i => TTCclk4x_dcm, ce => en_twinmux, o => TTCclk4x); i_TTCclk8x: bufgce port map(i => TTCclk8x_dcm, ce => en_twinmux, o => TTCclk8x); -- TTCdata output i_TTC_data : IDDR2 generic map ( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC" port map ( Q0 => TTCdata(0), -- 1-bit output captured with C0 clock Q1 => TTCdata(1), -- 1-bit output captured with C1 clock C0 => TTCclk, -- 1-bit clock input C1 => not TTCclk, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D => TTCdata_in, -- 1-bit DDR data input R => '0', -- 1-bit reset S => '0' -- 1-bit set ); TTC_data(0) <= TTCdata(0); TTC_data(2) <= TTCdata(1); clk1_en <= clk1_en_i; clk1_en_i <= amc_en or amc_enp; -- monitoring TTCclk and TTCdata process(TTCclk,TTC_lock) begin if(TTC_lock = '0')then TTC_data(1) <= '1'; L1A <= '0'; elsif(TTCclk'event and TTCclk = '1')then TTC_data(1) <= TTC_data(2); L1A <= TTC_data(0); end if; end process; process(TTCclk) variable brcst_cmd : std_logic_vector(3 downto 0); begin brcst_cmd := Brcst(7 downto 5) & Brcst(3); if(TTCclk'event and TTCclk = '1')then if(rec_cmd = '0')then rec_cntr <= (others => '0'); else rec_cntr <= rec_cntr + 1; end if; if(rec_cntr(5 downto 3) = "101" or (FMT = '0' and rec_cntr(3 downto 0) = x"d"))then rec_cmd <= '0'; elsif(TTC_data(1) = '0')then rec_cmd <= '1'; end if; if(or_reduce(rec_cntr) = '0')then FMT <= TTC_data(1); end if; sr <= sr(11 downto 0) & TTC_data(1); if(FMT = '0' and rec_cntr(3 downto 0) = x"e")then brcst_data <= sr(12 downto 5); brcst_syn(0) <= sr(0) xor sr(5) xor sr(6) xor sr(7) xor sr(8); brcst_syn(1) <= sr(1) xor sr(5) xor sr(9) xor sr(10) xor sr(11); brcst_syn(2) <= sr(2) xor sr(6) xor sr(7) xor sr(9) xor sr(10) xor sr(12); brcst_syn(3) <= sr(3) xor sr(6) xor sr(8) xor sr(9) xor sr(11) xor sr(12); brcst_syn(4) <= xor_reduce(sr); frame_err <= not TTC_data(1); brcst_str(0) <= '1'; else brcst_str(0) <= '0'; end if; single_err <= xor_reduce(brcst_syn) and not frame_err; if((or_reduce(brcst_syn) = '1' and xor_reduce(brcst_syn) = '0') or frame_err = '1')then double_err <= '1'; else double_err <= '0'; end if; SinErrStr <= single_err and brcst_str(1); DbErrStr <= double_err and brcst_str(1); brcst_str(2) <= brcst_str(1) and not double_err; if(brcst_syn(3 downto 0) = x"c")then Brcst(7) <= not brcst_data(7); else Brcst(7) <= brcst_data(7); end if; if(brcst_syn(3 downto 0) = x"a")then Brcst(6) <= not brcst_data(6); else Brcst(6) <= brcst_data(6); end if; if(brcst_syn(3 downto 0) = x"6")then Brcst(5) <= not brcst_data(5); else Brcst(5) <= brcst_data(5); end if; if(brcst_syn(3 downto 0) = x"e")then Brcst(4) <= not brcst_data(4); else Brcst(4) <= brcst_data(4); end if; if(brcst_syn(3 downto 0) = x"9")then Brcst(3) <= not brcst_data(3); else Brcst(3) <= brcst_data(3); end if; if(brcst_syn(3 downto 0) = x"5")then Brcst(2) <= not brcst_data(2); else Brcst(2) <= brcst_data(2); end if; if(brcst_syn(3 downto 0) = x"d")then Brcst(1) <= not brcst_data(1); else Brcst(1) <= brcst_data(1); end if; if(brcst_syn(3 downto 0) = x"3")then Brcst(0) <= not brcst_data(0); else Brcst(0) <= brcst_data(0); end if; OCntRes <= brcst_str(3) and and_reduce((Brcst xnor OcNresetCmd(7 downto 0)) or OcNresetCmd(15 downto 8)); BCntRes <= brcst_str(3) and Brcst(0); EvCntRes <= brcst_str(3) and Brcst(1); if(L1Accept = '1')then L1_reg <= Event_nr(15 downto 0); Bcnt_reg <= Bcnt; OC_reg <= OC_cnt; end if; if(brcst_str(3) = '1' and brcst_cmd /= x"0")then inc_TTCcmdCntr(CONV_INTEGER(brcst_cmd)) <= '1'; else inc_TTCcmdCntr <= (others => '0'); end if; end if; end process; process(TTCclk) begin if(TTCclk'event and TTCclk = '1')then if(BCntRes = '1' or Bcnt = x"deb")then Bcnt <= (others => '0'); else Bcnt <= Bcnt + 1; end if; if(OCntRes = '1')then OC_cnt <= (others => '0'); elsif(BCntRes = '1' or Bcnt = x"deb")then OC_cnt <= OC_cnt + 1; end if; end if; end process; process(TTCclk,reset) begin if(reset = '1')then Event_nr <= x"000001"; BcntErr_cnt <= (others => '0'); SinErr_cnt <= (others => '0'); DbErr_cnt <= (others => '0'); L1A_cnt <= (others => '0'); BC0_cnt <= (others => '0'); TTCcmdCntr <= (others => (others => '0')); elsif(TTCclk'event and TTCclk = '1')then if(EvCntRes = '1')then Event_nr <= x"000001"; elsif(L1Accept = '1')then Event_nr <= Event_nr + 1; end if; if((BcntRes = '1' and Bcnt /= x"deb") or (BcntRes = '0' and Bcnt = x"deb"))then BcntErr_cnt <= BcntErr_cnt + 1; end if; if(SinErrStr = '1' and SinErr_cnt /= x"ff")then SinErr_cnt <= SinErr_cnt + 1; end if; if(DbErrStr = '1' and DbErr_cnt /= x"ff")then DbErr_cnt <= DbErr_cnt + 1; end if; if(L1Accept = '1')then L1A_cnt <= L1A_cnt + 1; end if; if(BCntRes = '1')then BC0_cnt <= BC0_cnt + 1; end if; if(EvCntRes = '1')then TTCcmdCntr(0) <= TTCcmdCntr(0) + 1; end if; for i in 1 to 15 loop if(inc_TTCcmdCntr(i) = '1')then TTCcmdCntr(i) <= TTCcmdCntr(i) + 1; end if; end loop; end if; end process; i_L1Accept : SRL16E port map ( Q => L1Accept, -- SRL data output A0 => Coarse_Delay(0), -- Select[0] input A1 => Coarse_Delay(1), -- Select[1] input A2 => Coarse_Delay(2), -- Select[2] input A3 => Coarse_Delay(3), -- Select[3] input CE => '1', -- Clock enable input CLK => TTCclk, -- Clock input D => L1A -- SRL data input ); i_brcst_str1 : SRL16E port map ( Q => brcst_str(1), -- SRL data output A0 => '0', -- Select[0] input A1 => '1', -- Select[1] input A2 => '0', -- Select[2] input A3 => '0', -- Select[3] input CE => '1', -- Clock enable input CLK => TTCclk, -- Clock input D => brcst_str(0) -- SRL data input ); i_brcst_str3 : SRL16E port map ( Q => brcst_str(3), -- SRL data output A0 => Coarse_Delay(0), -- Select[0] input A1 => Coarse_Delay(1), -- Select[1] input A2 => Coarse_Delay(2), -- Select[2] input A3 => Coarse_Delay(3), -- Select[3] input CE => '1', -- Clock enable input CLK => TTCclk, -- Clock input D => brcst_str(2) -- SRL data input ); i_V6PROG_B : SRL16E generic map ( INIT => X"0000") port map ( Q => prog_V6_n, -- SRL data output A0 => '1', -- Select[0] input A1 => '1', -- Select[1] input A2 => '1', -- Select[2] input A3 => '1', -- Select[3] input CE => '1', -- Clock enable input CLK => ipb_clk, -- Clock input D => sysclk_DCM_LOCKED -- SRL data input ); V6_PROG_B <= prog_V6_n and not reprogV6; conf_end <= x"574ed09" when SN(8 downto 5) /= x"f" else x"4670209" when SN(4) = '0' else x"29b1c89"; process(ipb_clk,sysclk_DCM_LOCKED,reprogV6) begin if(sysclk_DCM_LOCKED = '0' or reprogV6 = '1')then inh_conf <= '0'; V6_INIT_B_q <= "00"; en_conf <= '0'; conf_cntr <= (others => '0'); M_Q <= '0'; FLASH_D <= '0'; V6_CDATA <= '0'; en_CCLK <= '0'; rst_crc <= '0'; calc_crc <= '0'; crc <= (others => '1'); elsif(ipb_clk'event and ipb_clk = '1')then if(prog_V6_n = '0')then inh_conf <= '0'; elsif(en_conf = '1')then inh_conf <= '1'; end if; V6_INIT_B_q <= V6_INIT_B_q(0) & V6_INIT_B; if(V6_DONE = '0' and V6_INIT_B_q = "01" and inh_conf = '0')then en_conf <= '1'; elsif(conf_cntr(26 downto 23) = x"f")then en_conf <= '0'; end if; if(en_conf = '0')then conf_cntr <= (others => '0'); else conf_cntr <= conf_cntr + 1; end if; M_Q <= FLASH_Q; if(en_conf = '0')then FLASH_D <= flash_MD; elsif(or_reduce(conf_cntr(26 downto 5)) = '0')then FLASH_D <= rom_FAST_READ; V6_CDATA <= '0'; else FLASH_D <= '0'; V6_CDATA <= M_Q; end if; FLASH_S <= not en_conf and (not flash_MCS(1) and not flash_MCS(0)); if(en_conf = '0')then en_CCLK <= '0'; elsif(conf_cntr(5) = '1' and conf_cntr(3) = '1' and conf_cntr(1) = '1')then en_CCLK <= '1'; end if; if(V6_DONE = '0' and V6_INIT_B_q = "01")then rst_crc <= '1'; else rst_crc <= '0'; end if; if(en_conf = '0' or conf_cntr = conf_end(26 downto 0))then -- reset calc_crc when conf_cntr = bitstream length + 41 calc_crc <= '0'; elsif(or_reduce(conf_cntr(26 downto 24)) = '0' and conf_cntr(5) = '1' and conf_cntr(3) = '1' and conf_cntr(0) = '1')then calc_crc <= '1'; end if; if(rst_crc = '1')then CRC <= (others => '1'); elsif(calc_crc = '1')then CRC(23) <= CRC(23) xor CRC(22); CRC(22 downto 19) <= CRC(21 downto 18); CRC(18) <= CRC(23) xor CRC(17); CRC(17) <= CRC(23) xor CRC(16); CRC(16 downto 15) <= CRC(15 downto 14); CRC(14) <= CRC(23) xor CRC(13); CRC(13 downto 12) <= CRC(12 downto 11); CRC(11) <= CRC(23) xor CRC(10); CRC(10) <= CRC(23) xor CRC(9); CRC(9 downto 8) <= CRC(8 downto 7); CRC(7) <= CRC(23) xor CRC(6); CRC(6) <= CRC(23) xor CRC(5); CRC(5) <= CRC(23) xor CRC(4); CRC(4) <= CRC(23) xor CRC(3); CRC(3) <= CRC(23) xor CRC(2); CRC(2) <= CRC(1); CRC(1) <= CRC(23) xor CRC(0); CRC(0) <= CRC(23) xor M_Q; end if; end if; end process; en_FLASH_C <= en_conf or flash_MCS(1); ipb_clk_n <= not ipb_clk; i_V6CCLK_ddr : ODDR2 port map ( Q => V6_CCLK, -- 1-bit output data C0 => ipb_clk, -- 1-bit clock input C1 => ipb_clk_n, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => '0', -- 1-bit data input (associated with C0) D1 => en_CCLK, -- 1-bit data input (associated with C1) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); i_FLASH_C_ddr : ODDR2 port map ( Q => FLASH_C, -- 1-bit output data C0 => ipb_clk, -- 1-bit clock input C1 => ipb_clk_n, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => '0', -- 1-bit data input (associated with C0) D1 => en_FLASH_C, -- 1-bit data input (associated with C1) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); i_rom_FAST_READ : ROM32X1 generic map ( INIT => X"000002d0") -- fast read start at 0x400000 port map ( O => rom_FAST_READ, -- ROM output A0 => conf_cntr(0), -- ROM address[0] A1 => conf_cntr(1), -- ROM address[1] A2 => conf_cntr(2), -- ROM address[2] A3 => conf_cntr(3), -- ROM address[3] A4 => conf_cntr(4) -- ROM address[4] ); i_flash: flash PORT MAP( clk => ipb_clk, sysclk => sysclk, we => ipb_master_out.ipb_write, strobe => ipb_master_out.ipb_strobe, w_data => ipb_master_out.ipb_wdata, addr => ipb_master_out.ipb_addr, flash_wdata => flash_wdata, flash_rdata => flash_rdata, flash_busy => flash_busy, MQ => FLASH_Q, MD => flash_MD, MCS => flash_MCS ); i_ICAP_clkBUFG : BUFG port map ( O => ICAP_clk, -- 1-bit output: Clock buffer output I => ICAP_clk_dcm -- 1-bit input: Clock buffer input ); i_ipb_clkBUFG : BUFG port map ( O => ipb_clk, -- 1-bit output: Clock buffer output I => ipb_clk_dcm -- 1-bit input: Clock buffer input ); i_sysclkBUFG : BUFG port map ( O => sysclk, -- 1-bit output: Clock buffer output I => sysclk_dcm -- 1-bit input: Clock buffer input ); i_sysclk2xBUFG : BUFG port map ( O => sysclk2x, -- 1-bit output: Clock buffer output I => sysclk2x_dcm -- 1-bit input: Clock buffer input ); i_sysclkBUFIO2 : BUFIO2 generic map ( DIVIDE => 1, -- DIVCLK divider (1-8) DIVIDE_BYPASS => TRUE, -- Bypass the divider circuitry (TRUE/FALSE) I_INVERT => FALSE, -- Invert clock (TRUE/FALSE) USE_DOUBLER => FALSE -- Use doubler circuitry (TRUE/FALSE) ) port map ( DIVCLK => sysclk_in, -- 1-bit output: Divided clock output IOCLK => open, -- 1-bit output: I/O output clock SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) I => GTPCLKOUT -- 1-bit input: Clock input (connect to IBUFG) ); i_sysclk_dcm : DCM_SP generic map ( CLKDV_DIVIDE => 4.0, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 8.0, CLKFX_DIVIDE => 16, -- Divide value on CLKFX outputs - D - (1-32) CLKFX_MULTIPLY => 2, -- Multiply value on CLKFX outputs - M - (2-32) CLK_FEEDBACK => "1X" ) port map ( CLK0 => sysclk_dcm, CLK180 => open, CLK270 => open, CLK2X => sysclk2x_dcm, CLK2X180 => open, CLK90 => open, CLKDV => ipb_clk_dcm, CLKFX => ICAP_clk_dcm, CLKFX180 => open, PSDONE => open, STATUS => open, DSSEN => '0', PSCLK => '0', PSEN => '0', PSINCDEC => '0', LOCKED => sysclk_DCM_LOCKED, CLKFB => sysclk, CLKIN => sysclk_in, RST => rst_sysclk_dcm ); rst_sysclk_dcm <= '0'; S6LinkGTPreset <= conf_cntr(26); GbEGTPreset <= conf_cntr(26) or rst_ipbus; i_GTP_if: GTP_if PORT MAP( sysclk => sysclk, sysclk2x => sysclk2x, S6LinkGTPreset => S6LinkGTPreset, S6LinkCDRreset => en_conf, GbEGTPreset => GbEGTPreset, T1_ready => T1_ready, REFCLK_P => REFCLK_P, REFCLK_N => REFCLK_N, LINK_RXP => LINK_RXP, LINK_RXN => LINK_RXN, GbE_RXP => GbE_RXP, GbE_RXN => GbE_RXN, LINK_TXP => LINK_TXP, LINK_TXN => LINK_TXN, GbE_TXP => GbE_TXP, GbE_TXN => GbE_TXN, LINKtxdata => LINKtxdata, LINKtxcharisk => LINKtxcharisk, LINKrxdata => LINKrxdata, LINKrxchariscomma => LINKrxchariscomma, LINKrxcharisk => LINKrxcharisk, Link_RXBYTEISALIGNED => Link_RXBYTEISALIGNED, GbEtxdvld => GbEtxdvld, GbEtxd => GbEtxd, GbEtxdlast => GbEtxdlast, GbEtxerr => GbEtxerr, GbEtxready => GbEtxready, GbErxd => GbErxd, GbErxdvld => GbErxdvld, GbErxdlast => GbErxdlast, GbErxerr => GbErxerr, debug_in => debug_in, debug_out => debug_out, GTPCLKOUT => GTPCLKOUT, LINKPLLLOCK => LINKPLLLOCK ); process(sysclk) begin if(sysclk'event and sysclk = '1')then GbErxd_q <= GbErxd; GbErxdvld_q <= GbErxdvld; GbErxgoodframe <= GbErxdvld and GbErxdlast and not GbErxerr; GbErxbadframe <= GbErxdvld and GbErxdlast and GbErxerr; GbErxgoodframe_q <= GbErxgoodframe; GbErxbadframe_q <= GbErxbadframe; if(GbErxdvld_q = '1')then LINKtxcharisk(0) <= '0'; LINKtxdata(7 downto 0) <= GbErxd_q; elsif(GbErxgoodframe_q = '1')then LINKtxcharisk(0) <= '1'; LINKtxdata(7 downto 0) <= x"f7"; elsif(GbErxbadframe_q = '1')then LINKtxcharisk(0) <= '1'; LINKtxdata(7 downto 0) <= x"fb"; elsif(GbErxdvld = '1')then LINKtxcharisk(0) <= '1'; LINKtxdata(7 downto 0) <= x"3c"; elsif(div(3) = '1')then LINKtxcharisk(0) <= '1'; LINKtxdata(7 downto 0) <= x"bc"; else LINKtxcharisk(0) <= '0'; LINKtxdata(7 downto 0) <= x"00"; end if; if(div(3) = '1' or GbErxdvld_q = '1')then div <= (others => '0'); else div <= div + 1; end if; if((GbEtxdlast = '1' and sel_Link = '1') or (LinkFIFO_empty = '1' and GbErxdvld = '1' and GbErxdvld_q = '0'))then LINKtxcharisk(1) <= '1'; LINKtxdata(15 downto 8) <= x"f7"; else LINKtxcharisk(1) <= '0'; SN_high <= not SN_high; if(SN(8) = '1')then LINKtxdata(15 downto 8) <= SN(7 downto 0); elsif(SN_high = '0')then LINKtxdata(15 downto 8) <= '0' & SN(6 downto 0); else LINKtxdata(15 downto 8) <= "100000" & SN(8 downto 7); end if; end if; LinkFIFO_din(7 downto 0) <= LINKrxdata(7 downto 0); LINKrxcharisk1_q <= LINKrxcharisk(1); LINKrxdata_q <= LINKrxdata(15 downto 8); if(V6_Done = '0')then RxV6cmd <= '0'; elsif(LINKrxcharisk1_q = '1')then if(LINKrxdata_q = x"fe")then RxV6cmd <= '1'; else RxV6cmd <= '0'; end if; end if; if(RxV6cmd = '0')then RxV6Cntr <= (others => '0'); else RxV6Cntr <= RxV6Cntr + 1; end if; if(RxV6cmd = '0')then wr_amc_en <= '0'; rst_ipbus <= '0'; elsif(or_reduce(RxV6Cntr) = '0')then if(LINKrxdata_q = x"a5")then wr_amc_en <= '1'; elsif(LINKrxdata_q = x"38")then rst_ipbus <= '1'; end if; end if; LinkFIFO_rst <= not Link_RXBYTEISALIGNED or not V6_Done; end if; end process; process(sysclk,V6_Done,Link_RXBYTEISALIGNED) begin if(V6_Done = '0' or Link_RXBYTEISALIGNED = '0')then LinkFIFO_wep <= '0'; LinkFIFO_we <= '0'; sel_Link <= '0'; elsif(sysclk'event and sysclk = '1')then if(LINKrxcharisk(0) = '1')then if(LINKrxdata(7 downto 0) = x"3c")then LinkFIFO_wep <= '1'; else LinkFIFO_wep <= '0'; LinkFIFO_we <= '0'; end if; else LinkFIFO_we <= LinkFIFO_wep; end if; if(GbEtxdvld = '0')then sel_Link <= not LinkFIFO_empty; end if; end if; end process; process(sysclk,V6_Done) begin if(V6_Done = '0')then amc_en <= (others => '0'); elsif(sysclk'event and sysclk = '1')then if(wr_amc_en = '1' and RxV6Cntr = "001")then amc_en(7 downto 0) <= LINKrxdata_q; end if; if(wr_amc_en = '1' and RxV6Cntr = "010")then amc_en(11 downto 8) <= LINKrxdata_q(3 downto 0); end if; end if; end process; GbEtxd <= LinkFIFO_dout(7 downto 0) when sel_Link = '1' else ipbus_txd; GbEtxdvld <= not LinkFIFO_empty when sel_Link = '1' else ipbus_txdvld; GbEtxdlast <= LinkFIFO_dout(8) when sel_Link = '1' else ipbus_txdlast; GbEtxerr <= '0' when sel_Link = '1' else ipbus_txerr; LinkFIFO_re <= GbEtxready and sel_Link; ipbus_txready <= GbEtxready and not sel_Link; -- this is a first word fall through FIFO with synchronous reset i_LinkFIFO : LinkFIFO PORT MAP ( clk => sysclk, srst => LinkFIFO_rst, din => LinkFIFO_din, wr_en => LinkFIFO_we, rd_en => LinkFIFO_re, dout => LinkFIFO_dout, full => open, empty => LinkFIFO_empty ); LinkFIFO_din(8) <= LINKrxcharisk(0); rst_ipb <= conf_cntr(26) or rst_ipbus; rst_macclk <= conf_cntr(26) or rst_ipbus; i_ipbus: ipbus_ctrl port map( mac_clk => sysclk, rst_macclk => rst_macclk, ipb_clk => ipb_clk, rst_ipb => rst_ipb, mac_rx_data => GbErxd, mac_rx_valid => GbErxdvld, mac_rx_last => GbErxdlast, mac_rx_error => GbErxerr, mac_tx_data => ipbus_txd, mac_tx_valid => ipbus_txdvld, mac_tx_last => ipbus_txdlast, mac_tx_error => ipbus_txerr, mac_tx_ready => ipbus_txready, ipb_out => ipb_master_out, ipb_in => ipb_master_in, ipb_req => open, ipb_grant => '1', mac_addr => x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '0' & SN(5 downto 0), ip_addr => IPADDR, enable => '1', RARP_select => en_RARP, pkt_rx => open, pkt_tx => open, pkt_rx_led => open, pkt_tx_led => open, oob_in => (others => ('0', X"00000000", '0')), oob_out => open ); process(ipb_master_in,flash_wdata,flash_rdata) begin if(ipb_master_out.ipb_addr(12 downto 8) = "10000")then if(ipb_master_out.ipb_addr(7) = '0')then ipb_master_in.ipb_rdata <= flash_wdata; else ipb_master_in.ipb_rdata <= flash_rdata; end if; elsif(ipb_master_out.ipb_addr(11) = '1')then case ipb_master_out.ipb_addr(1 downto 0) is when "00" => ipb_master_in.ipb_rdata <= x"000000" & TTC_history_do(7 downto 0); -- TTC_CMD when "01" => ipb_master_in.ipb_rdata <= TTC_history_do(39 downto 8); -- TTC_OrN when "10" => ipb_master_in.ipb_rdata <= x"00000" & TTC_history_do(51 downto 40); -- TTC_BcN when others => ipb_master_in.ipb_rdata <= x"00" & TTC_history_do(75 downto 52); -- TTC_EvN end case; elsif(ipb_master_out.ipb_addr(10) = '1')then ipb_master_in.ipb_rdata <= zero(31 downto 14) & buffer_do(13 downto 0); elsif(ipb_master_out.ipb_addr(9) = '1')then ipb_master_in.ipb_rdata <= twinmux_data; elsif(ipb_master_out.ipb_addr(8) = '1')then case ipb_master_out.ipb_addr(3 downto 0) is when x"1" => ipb_master_in.ipb_rdata <= zero(31 downto 1) & en_twinmux; when x"2" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_TRIG0; when x"3" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_TRIG1; when x"4" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(0); when x"5" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(1); when x"6" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(2); when x"7" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(3); when x"8" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(4); when x"9" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(5); when x"a" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(6); when x"b" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(7); when x"c" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(8); when x"d" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(9); when x"e" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(10); when x"f" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & delay_twinmux(11); when others => ipb_master_in.ipb_rdata <= (others => '0'); end case; elsif(ipb_master_out.ipb_addr(7 downto 4) = x"0")then case ipb_master_out.ipb_addr(3 downto 0) is when x"0" => ipb_master_in.ipb_rdata <= zero(31 downto 25) & not SN & T2_version; when x"1" => ipb_master_in.ipb_rdata <= zero(31 downto 1) & flash_busy; when x"2" => ipb_master_in.ipb_rdata <= zero(31 downto 12) & amc_en; when x"3" => ipb_master_in.ipb_rdata <= not V6_INIT_B & not V6_DONE & not T1_Ready & en_RARP & not prog_V6_n & reprogV6 & "00" & crc; when x"4" => ipb_master_in.ipb_rdata <= zero(31 downto 16) & L1_reg; when x"5" => ipb_master_in.ipb_rdata <= zero(31 downto 12) & Bcnt_reg; when x"6" => ipb_master_in.ipb_rdata <= OC_reg; when x"7" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & BcntErr_cnt; when x"8" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & SinErr_cnt; when x"9" => ipb_master_in.ipb_rdata <= zero(31 downto 8) & DbErr_cnt; when x"a" => ipb_master_in.ipb_rdata <= L1A_cnt & BC0_cnt; when x"b" => ipb_master_in.ipb_rdata <= zero(31 downto 28) & bcnt & T3_L1A_cnt; when x"c" => ipb_master_in.ipb_rdata <= zero(31 downto 20) & F_TTC; when x"d" => ipb_master_in.ipb_rdata <= en_TTC_history & en_TTC_filter & TTC_history_full & x"0" & TTC_history_wa & x"0" & amc_enp; when x"e" => ipb_master_in.ipb_rdata <= DNA(31 downto 0); when others => ipb_master_in.ipb_rdata <= zero(31 downto 25) & DNA(56 downto 32); end case; elsif(ipb_master_out.ipb_addr(7 downto 4) = x"1")then ipb_master_in.ipb_rdata <= zero(31 downto 16) & TTCcmdCntr(CONV_INTEGER(ipb_master_out.ipb_addr(3 downto 0))); elsif(ipb_master_out.ipb_addr(7 downto 4) = x"2")then ipb_master_in.ipb_rdata <= zero(31 downto 17) & cmd_list_SP; elsif(ipb_master_out.ipb_addr(7 downto 0) = x"30")then ipb_master_in.ipb_rdata <= zero(31 downto 16) & OcNresetCmd; else ipb_master_in.ipb_rdata <= (others => '0'); end if; end process; process(sysclk) begin if(sysclk'event and sysclk = '1')then if(reset = '1')then T3_L1A_sync <= (others => '0'); T3_L1A_cnt <= (others => '0'); else T3_L1A_sync <= T3_L1A_sync(2 downto 0) & S2V; if(T3_L1A_sync(3 downto 2) = "01")then T3_L1A_cnt <= T3_L1A_cnt + 1; end if; end if; end if; end process; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(ipbclk_cntr = x"98967")then ipbclk_cntr <= (others => '0'); else ipbclk_cntr <= ipbclk_cntr + 1; end if; end if; end process; process(TTCclk) begin if(TTCclk'event and TTCclk = '1')then ipbclk_cntr19_sync <= ipbclk_cntr19_sync(2 downto 0) & ipbclk_cntr(19); if(ipbclk_cntr19_sync(3 downto 2) = "10")then TTC_cntr <= (others => '0'); F_TTC <= TTC_cntr; else TTC_cntr <= TTC_cntr + 1; end if; end if; end process; i_reprogV6_dl : SRL16E port map ( Q => reprogV6_dl, -- SRL data output A0 => '1', -- Select[0] input A1 => '1', -- Select[1] input A2 => '1', -- Select[2] input A3 => '1', -- Select[3] input CE => '1', -- Clock enable input CLK => ipb_clk, -- Clock input D => reprogV6 -- SRL data input ); process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then DNA_div <= DNA_div + 1; if(ipb_master_out.ipb_addr(15 downto 0) = ipbus_ver_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then reset <= ipb_master_out.ipb_wdata(0); pulse <= ipb_master_out.ipb_wdata(1); clear_TTC_history <= ipb_master_out.ipb_wdata(2); reprogS6 <= ipb_master_out.ipb_wdata(8); else reset <= '0'; pulse <= '0'; clear_TTC_history <= '0'; end if; if(reprogV6_dl = '1')then reprogV6 <= '0'; elsif(ipb_master_out.ipb_addr(15 downto 0) = ipbus_ver_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then reprogV6 <= ipb_master_out.ipb_wdata(4); end if; if(cmd_list_wap = x"f")then clear_cmd_list <= '0'; elsif(ipb_master_out.ipb_addr(15 downto 0) = ipbus_ver_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then clear_cmd_list <= ipb_master_out.ipb_wdata(3); end if; if(ipb_master_out.ipb_addr(15 downto 0) = x"000d" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then amc_enp <= ipb_master_out.ipb_wdata(11 downto 0); en_TTC_history <= ipb_master_out.ipb_wdata(31); en_TTC_filter <= ipb_master_out.ipb_wdata(30); end if; if(ipb_master_out.ipb_addr(15 downto 0) = x"0031" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then OcNresetCmd <= ipb_master_out.ipb_wdata(15 downto 0); end if; if(ipb_master_out.ipb_addr(15 downto 4) = x"010" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then case ipb_master_out.ipb_addr(3 downto 0) is when x"0" => catch_twinmux <= ipb_master_out.ipb_wdata(0); when x"1" => en_twinmux <= ipb_master_out.ipb_wdata(0); when x"2" => delay_TRIG0 <= ipb_master_out.ipb_wdata(7 downto 0); when x"3" => delay_TRIG1 <= ipb_master_out.ipb_wdata(7 downto 0); when others => delay_twinmux(conv_integer(ipb_master_out.ipb_addr(3 downto 0)) - 4) <= ipb_master_out.ipb_wdata(7 downto 0); end case; else catch_twinmux <= '0'; end if; end if; end process; ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe; ipb_master_in.ipb_err <= '0'; process(ICAP_clk) begin if(ICAP_clk'event and ICAP_clk = '1')then reprogs6_dl(3 downto 1) <= reprogs6_dl(2 downto 0); reboots6 <= not reprogs6_dl(3) and reprogs6_dl(2); end if; end process; --I_ICAP : ICAP_SP605_reboot -- PORT map( -- clk => ICAP_clk, -- MBT_RESET => rst_macclk, -- MBT_REBOOT => reboots6, -- MBT_BUSY => open, -- ICAP_DOUT => open -- ); i_reboot: reboot PORT MAP ( rst => rst_macclk, ICAP_clk => ICAP_clk, reprogs6 => reboots6 ); i_reprogS6_dl : SRLC32E generic map ( INIT => X"00000000") port map ( Q => reprogS6_dl(0), -- SRL data output Q31 => open, -- SRL cascade output pin A => "11111", -- 5-bit shift depth select input CE => '1', -- Clock enable input CLK => ICAP_clk, -- Clock input D => reprogS6 -- SRL data input ); i_DNA_clk : BUFG port map ( O => DNA_clk, -- 1-bit output: Clock buffer output I => DNA_div(4) -- 1-bit input: Clock buffer input ); i_DNA_PORT : DNA_PORT generic map ( SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation ) port map ( DOUT => DNA_out, -- 1-bit output: DNA output data. CLK => DNA_clk, -- 1-bit input: Clock input. DIN => '0', -- 1-bit input: User data input pin. READ => load_DNA(1), -- 1-bit input: Active high load DNA, active low read input. SHIFT => shift_DNA -- 1-bit input: Active high shift enable input. ); process(DNA_clk,sysclk_DCM_LOCKED) begin if(sysclk_DCM_LOCKED = '0')then load_DNA <= "11"; elsif(DNA_clk'event and DNA_clk = '1')then load_DNA <= load_DNA(0) & '0'; if(shift_DNA = '1')then DNA <= DNA(55 downto 0) & DNA_OUT; end if; end if; end process; process(DNA_clk,sysclk_DCM_LOCKED) begin if(sysclk_DCM_LOCKED = '0')then shift_DNA <= '0'; DNA_cntr <= "111001"; elsif(DNA_clk'event and DNA_clk = '0')then if(or_reduce(DNA_cntr(5 downto 1)) = '0')then shift_DNA <= '0'; else shift_DNA <= not load_DNA(1); end if; if(shift_DNA = '1')then DNA_cntr <= DNA_cntr - 1; end if; end if; end process; -- TTC command history process(TTCclk) begin if(TTCclk'event and TTCclk = '1')then if(brcst_str(3) = '1')then TTC_CMD <= Brcst; TTC_OrN <= OC_cnt; TTC_BcN <= Bcnt; TTC_EvN <= Event_nr; end if; if(brcst_str(3) = '1')then chk_cmd_list <= en_TTC_history; elsif(en_TTC_filter = '0' or cmd_list_ra = x"f" or (cmd_list(16) = '1' and and_reduce((TTC_CMD xnor cmd_list(7 downto 0)) or cmd_list(15 downto 8)) = '1'))then chk_cmd_list <= '0'; end if; if(chk_cmd_list = '0')then cmd_list_ra <= x"0"; else cmd_list_ra <= cmd_list_ra + 1; end if; if(chk_cmd_list = '1' and en_TTC_filter = '0')then TTC_history_we <= '1'; elsif(chk_cmd_list = '0' or cmd_list_ra /= x"f" or (cmd_list(16) = '1' and and_reduce((TTC_CMD xnor cmd_list(7 downto 0)) or cmd_list(15 downto 8)) = '1'))then TTC_history_we <= '0'; else TTC_history_we <= '1'; end if; TTC_history_di <= TTC_EvN & TTC_BcN & TTC_OrN & TTC_CMD; if(clear_cmd_list = '0')then cmd_list_wap <= x"0"; else cmd_list_wap <= cmd_list_wap + 1; end if; if(reset = '1' or clear_TTC_history = '1')then TTC_history_wa <= (others => '0'); TTC_history_full <= '0'; elsif(TTC_history_we = '1')then TTC_history_wa <= TTC_history_wa + 1; if(and_reduce(TTC_history_wa) = '1')then TTC_history_full <= '1'; end if; end if; end if; end process; g_cmd_list : for i in 0 to 16 generate i_cmd_list : RAM32X1D generic map(INIT => cmd_list_INIT(i)) port map ( DPO => cmd_list(i), -- Read-only 1-bit data output SPO => cmd_list_SP(i), -- R/W 1-bit data output A0 => cmd_list_wa(0), -- R/W address[0] input bit A1 => cmd_list_wa(1), -- R/W address[1] input bit A2 => cmd_list_wa(2), -- R/W address[2] input bit A3 => cmd_list_wa(3), -- R/W address[3] input bit A4 => '0', -- R/W address[4] input bit D => cmd_list_di(i), -- Write 1-bit data input DPRA0 => cmd_list_ra(0), -- Read-only address[0] input bit DPRA1 => cmd_list_ra(1), -- Read-only address[1] input bit DPRA2 => cmd_list_ra(2), -- Read-only address[2] input bit DPRA3 => cmd_list_ra(3), -- Read-only address[3] input bit DPRA4 => '0', -- Read-only address[4] input bit WCLK => ipb_clk, -- Write clock input WE => cmd_list_we -- Write enable input ); end generate; cmd_list_wa <= ipb_master_out.ipb_addr(3 downto 0) when clear_cmd_list = '0' else cmd_list_wap; cmd_list_di <= ipb_master_out.ipb_wdata(16 downto 0) when clear_cmd_list = '0' else (others => '0'); cmd_list_we <= '1' when clear_cmd_list = '1' or (ipb_master_out.ipb_addr(15 downto 4) = x"002" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1') else '0'; i_TTC_history0 : BRAM_SDP_MACRO generic map ( BRAM_SIZE => "18Kb", -- Target BRAM, "9Kb" or "18Kb" DEVICE => "SPARTAN6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6" WRITE_WIDTH => 32, -- Valid values are 1-36 READ_WIDTH => 32) -- Valid values are 1-36 port map ( DO => TTC_history_do(31 downto 0), -- Output read data port, width defined by READ_WIDTH parameter DI => TTC_history_di(31 downto 0), -- Input write data port, width defined by WRITE_WIDTH parameter RDADDR => ipb_master_out.ipb_addr(10 downto 2), -- Input read address, width defined by read port depth RDCLK => sysclk, -- 1-bit input read clock RDEN => '1', -- 1-bit input read port enable REGCE => '1', -- 1-bit input read output register enable RST => '0', -- 1-bit input reset WE => x"f", -- Input write enable, width defined by write port depth WRADDR => TTC_history_wa, -- Input write address, width defined by write port depth WRCLK => TTCclk, -- 1-bit input write clock WREN => TTC_history_we -- 1-bit input write port enable ); i_TTC_history1 : BRAM_SDP_MACRO generic map ( BRAM_SIZE => "18Kb", -- Target BRAM, "9Kb" or "18Kb" DEVICE => "SPARTAN6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6" WRITE_WIDTH => 32, -- Valid values are 1-36 READ_WIDTH => 32) -- Valid values are 1-36 port map ( DO => TTC_history_do(63 downto 32), -- Output read data port, width defined by READ_WIDTH parameter DI => TTC_history_di(63 downto 32), -- Input write data port, width defined by WRITE_WIDTH parameter RDADDR => ipb_master_out.ipb_addr(10 downto 2), -- Input read address, width defined by read port depth RDCLK => sysclk, -- 1-bit input read clock RDEN => '1', -- 1-bit input read port enable REGCE => '1', -- 1-bit input read output register enable RST => '0', -- 1-bit input reset WE => x"f", -- Input write enable, width defined by write port depth WRADDR => TTC_history_wa, -- Input write address, width defined by write port depth WRCLK => TTCclk, -- 1-bit input write clock WREN => TTC_history_we -- 1-bit input write port enable ); i_TTC_history2 : BRAM_SDP_MACRO generic map ( BRAM_SIZE => "9Kb", -- Target BRAM, "9Kb" or "18Kb" DEVICE => "SPARTAN6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6" WRITE_WIDTH => 12, -- Valid values are 1-36 READ_WIDTH => 12) -- Valid values are 1-36 port map ( DO => TTC_history_do(75 downto 64), -- Output read data port, width defined by READ_WIDTH parameter DI => TTC_history_di(75 downto 64), -- Input write data port, width defined by WRITE_WIDTH parameter RDADDR => ipb_master_out.ipb_addr(10 downto 2), -- Input read address, width defined by read port depth RDCLK => sysclk, -- 1-bit input read clock RDEN => '1', -- 1-bit input read port enable REGCE => '1', -- 1-bit input read output register enable RST => '0', -- 1-bit input reset WE => "11", -- Input write enable, width defined by write port depth WRADDR => TTC_history_wa, -- Input write address, width defined by write port depth WRCLK => TTCclk, -- 1-bit input write clock WREN => TTC_history_we -- 1-bit input write port enable ); -- twinmux trigger logic process(TTCclk4x) begin if(TTCclk4x'event and TTCclk4x = '1')then catch_twinmuxSync <= catch_twinmuxSync(1 downto 0) & catch_twinmux; if(TTCclkPhase(3) = '1' and en_trig = '1' and twinmux(0) = '1')then -- if(TTCclkPhase(3) = '1' and en_trig = '1')then buffer_we <= x"f"; elsif(and_reduce(buffer_wa) = '1')then buffer_we <= x"0"; end if; if(catch_twinmuxSync(2) = '1')then en_trig <= '1'; elsif(buffer_we(0) = '1')then en_trig <= '0'; end if; if(buffer_we(0) = '0')then buffer_wa <= (others => '0'); else buffer_wa <= buffer_wa + 1; end if; TTCclk_toggle_q <= TTCclk_toggle; TTCclkPhase <= TTCclkPhase(2 downto 1) & (TTCclk_toggle_q xor TTCclk_toggle); end if; end process; process(TTCclk) begin if(TTCclk'event and TTCclk = '1')then T3_SCK_o <= not twinmux(0); TTCclk_toggle <= not TTCclk_toggle; end if; end process; i_TRIG0: trig_data PORT MAP( clk => TTCclk8x, din => T3_TCDS_aux1, din_polarity => '1', dl => delay_TRIG0, twinmux_ra => twinmux_ra(12), buffer_dinA => buffer_di(12), buffer_dinB => buffer_di(28) ); i_TRIG1: trig_data PORT MAP( clk => TTCclk8x, din => T3_TCDS_aux2, din_polarity => '1', dl => delay_TRIG1, twinmux_ra => twinmux_ra(13), buffer_dinA => buffer_di(13), buffer_dinB => buffer_di(29) ); g_trig_Twinmux : for i in 0 to 11 generate i_trig_data: trig_data PORT MAP( clk => TTCclk8x, din => RxFB_in(i+1), din_polarity => '0', dl => delay_twinmux(i), twinmux_ra => twinmux_ra(i), buffer_dinA => buffer_di(i), buffer_dinB => buffer_di(i+16) ); end generate; i_twinmux : BRAM_TDP_MACRO generic map ( BRAM_SIZE => "18Kb", -- Target BRAM, "9Kb" or "18Kb" DEVICE => "SPARTAN6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6" DOA_REG => 0, -- Optional port A output register (0 or 1) DOB_REG => 0, -- Optional port B output register (0 or 1) WRITE_WIDTH_A => 1, -- Valid values are 1-36 WRITE_WIDTH_B => 32, -- Valid values are 1-36 READ_WIDTH_A => 1, -- Valid values are 1-36 READ_WIDTH_B => 32) -- Valid values are 1-36 port map ( DOA => twinmux, -- Output port-A data DOB => twinmux_data, -- Output port-B data ADDRA => twinmux_ra, -- Input port-A address ADDRB => twinmux_wa, -- Input port-B address CLKA => TTCclk_n, -- Input port-A clock CLKB => sysclk, -- Input port-B clock DIA => "0", -- Input port-A data DIB => ipb_master_out.ipb_wdata, -- Input port-B data ENA => '1', -- Input port-A enable ENB => '1', -- Input port-B enable REGCEA => '1', -- Input port-A output register enable REGCEB => '1', -- Input port-B output register enable RSTA => '0', -- Input port-A reset RSTB => '0', -- Input port-B reset WEA => "0", -- Input port-A write enable WEB => twinmux_web -- Input port-B write enable ); TTCclk_n <= not TTCclk; twinmux_wa <= ipb_master_out.ipb_addr(8 downto 0); process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then clk_toggle <= not clk_toggle; end if; end process; process(sysclk) begin if(sysclk'event and sysclk = '1')then clk_toggle_q <= clk_toggle; if(clk_toggle_q /= clk_toggle and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and ipb_master_out.ipb_addr(15 downto 9) = twinmux_addr(15 downto 9))then twinmux_web <= x"f"; else twinmux_web <= x"0"; end if; end if; end process; i_buffer : BRAM_TDP_MACRO generic map ( BRAM_SIZE => "18Kb", -- Target BRAM, "9Kb" or "18Kb" DEVICE => "SPARTAN6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6" DOA_REG => 0, -- Optional port A output register (0 or 1) DOB_REG => 0, -- Optional port B output register (0 or 1) WRITE_WIDTH_A => 32, -- Valid values are 1-36 WRITE_WIDTH_B => 16, -- Valid values are 1-36 READ_WIDTH_A => 32, -- Valid values are 1-36 READ_WIDTH_B => 16) -- Valid values are 1-36 port map ( DOA => open, -- Output port-A data DOB => buffer_do, -- Output port-B data ADDRA => buffer_wa, -- Input port-A address ADDRB => ipb_master_out.ipb_addr(9 downto 0), -- Input port-B address CLKA => TTCclk4x, -- Input port-A clock CLKB => sysclk, -- Input port-B clock DIA => buffer_di, -- Input port-A data DIB => (others => '0'), -- Input port-B data ENA => '1', -- Input port-A enable ENB => '1', -- Input port-B enable REGCEA => '1', -- Input port-A output register enable REGCEB => '1', -- Input port-B output register enable RSTA => '0', -- Input port-A reset RSTB => '0', -- Input port-B reset WEA => buffer_we, -- Input port-A write enable WEB => "00" -- Input port-B write enable ); end Behavioral;