-------------------------------------------------------------------------------- Release 14.7 Trace (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml AMC13_T2.twx AMC13_T2.ncd -o AMC13_T2.twr AMC13_T2.pcf -ucf AMC13_T2.ucf Design file: AMC13_T2.ncd Physical constraint file: AMC13_T2.pcf Device,package,speed: xc6slx45t,fgg484,C,-2 (PRODUCTION 1.23 2013-10-13) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: NET "RxFB_in<12>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.450ns. -------------------------------------------------------------------------------- Slack: 0.550ns RxFB_in<12> Report: 2.450ns delay meets 3.000ns timing constraint by 0.550ns From To Delay(ns) Y5.I SLICE_X2Y3.AX 2.450 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<11>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.147ns. -------------------------------------------------------------------------------- Slack: 0.853ns RxFB_in<11> Report: 2.147ns delay meets 3.000ns timing constraint by 0.853ns From To Delay(ns) W6.I SLICE_X4Y2.AX 2.147 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<10>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.698ns. -------------------------------------------------------------------------------- Slack: 0.302ns RxFB_in<10> Report: 2.698ns delay meets 3.000ns timing constraint by 0.302ns From To Delay(ns) V7.I SLICE_X12Y0.DX 2.698 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<9>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.174ns. -------------------------------------------------------------------------------- Slack: 0.826ns RxFB_in<9> Report: 2.174ns delay meets 3.000ns timing constraint by 0.826ns From To Delay(ns) Y9.I SLICE_X22Y2.AX 2.174 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<8>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.147ns. -------------------------------------------------------------------------------- Slack: 0.853ns RxFB_in<8> Report: 2.147ns delay meets 3.000ns timing constraint by 0.853ns From To Delay(ns) W9.I SLICE_X16Y2.AX 2.147 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<7>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.450ns. -------------------------------------------------------------------------------- Slack: 0.550ns RxFB_in<7> Report: 2.450ns delay meets 3.000ns timing constraint by 0.550ns From To Delay(ns) V11.I SLICE_X22Y3.AX 2.450 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<6>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.450ns. -------------------------------------------------------------------------------- Slack: 0.550ns RxFB_in<6> Report: 2.450ns delay meets 3.000ns timing constraint by 0.550ns From To Delay(ns) V13.I SLICE_X38Y3.AX 2.450 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<5>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.823ns. -------------------------------------------------------------------------------- Slack: 0.177ns RxFB_in<5> Report: 2.823ns delay meets 3.000ns timing constraint by 0.177ns From To Delay(ns) AA14.I SLICE_X55Y10.AX 2.823 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<4>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.255ns. -------------------------------------------------------------------------------- Slack: 0.745ns RxFB_in<4> Report: 2.255ns delay meets 3.000ns timing constraint by 0.745ns From To Delay(ns) W14.I SLICE_X34Y0.AX 2.255 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<3>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.391ns. -------------------------------------------------------------------------------- Slack: 0.609ns RxFB_in<3> Report: 2.391ns delay meets 3.000ns timing constraint by 0.609ns From To Delay(ns) Y16.I SLICE_X40Y2.AX 2.391 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<2>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.690ns. -------------------------------------------------------------------------------- Slack: 0.310ns RxFB_in<2> Report: 2.690ns delay meets 3.000ns timing constraint by 0.310ns From To Delay(ns) W17.I SLICE_X55Y9.AX 2.690 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<1>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.378ns. -------------------------------------------------------------------------------- Slack: 0.622ns RxFB_in<1> Report: 2.378ns delay meets 3.000ns timing constraint by 0.622ns From To Delay(ns) V17.I SLICE_X56Y2.AX 2.378 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "i_TRIG1/din_polarity_din_XOR_576_o" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.314ns. -------------------------------------------------------------------------------- Slack: 0.686ns i_TRIG1/din_polarity_din_XOR_576_o Report: 2.314ns delay meets 3.000ns timing constraint by 0.686ns From To Delay(ns) K4.I SLICE_X2Y69.AX 2.314 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "i_TRIG0/din_polarity_din_XOR_576_o" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.378ns. -------------------------------------------------------------------------------- Slack: 0.622ns i_TRIG0/din_polarity_din_XOR_576_o Report: 2.378ns delay meets 3.000ns timing constraint by 0.622ns From To Delay(ns) L6.I SLICE_X2Y68.AX 2.320 L6.I SLICE_X3Y67.A6 2.378 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_REFCLK_P = PERIOD TIMEGRP "REFCLK_P" 8 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 3.703ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_REFCLK_P = PERIOD TIMEGRP "REFCLK_P" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 4.297ns (period - min period limit) Period: 8.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_CLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK00 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK00 Location pin: GTPA1_DUAL_X0Y0.CLK00 Clock network: i_GTP_if/REFCLK -------------------------------------------------------------------------------- Slack: 4.297ns (period - min period limit) Period: 8.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_CLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK01 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK01 Location pin: GTPA1_DUAL_X0Y0.CLK01 Clock network: i_GTP_if/REFCLK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 250 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 3735 paths analyzed, 666 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 16.318ns. -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_out_1 (SLICE_X2Y76.C2), 30 paths -------------------------------------------------------------------------------- Slack (setup path): 116.841ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_1 (FF) Requirement: 125.000ns Data Path Delay: 8.117ns (Levels of Logic = 3) Clock Path Skew: -0.007ns (0.295 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X23Y70.A1 net (fanout=26) 3.671 i_SPI_if/STATUS_5 SLICE_X23Y70.A Tilo 0.259 i_ipbus/my_ip_addr_udp<2> i_SPI_if/Mmux_IPADDR_i121 SLICE_X10Y74.A3 net (fanout=2) 1.486 ipaddr<1> SLICE_X10Y74.BMUX Topab 0.456 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<1>1 i_SPI_if/mux1_4 i_SPI_if/mux1_3_f7 i_SPI_if/mux1_2_f8 SLICE_X2Y76.C2 net (fanout=1) 1.476 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<1>1 SLICE_X2Y76.CLK Tas 0.339 i_SPI_if/sr_out<2> i_SPI_if/sr_out_1_glue_set i_SPI_if/sr_out_1 ------------------------------------------------- --------------------------- Total 8.117ns (1.484ns logic, 6.633ns route) (18.3% logic, 81.7% route) -------------------------------------------------------------------------------- Slack (setup path): 118.514ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_1 (FF) Requirement: 125.000ns Data Path Delay: 6.444ns (Levels of Logic = 3) Clock Path Skew: -0.007ns (0.295 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X16Y74.D1 net (fanout=26) 2.798 i_SPI_if/STATUS_5 SLICE_X16Y74.DMUX Tilo 0.298 i_ipbus/my_ip_addr_udp<9> i_SPI_if/Mmux_IPADDR_i321 SLICE_X10Y74.A6 net (fanout=2) 0.647 ipaddr<9> SLICE_X10Y74.BMUX Topab 0.456 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<1>1 i_SPI_if/mux1_4 i_SPI_if/mux1_3_f7 i_SPI_if/mux1_2_f8 SLICE_X2Y76.C2 net (fanout=1) 1.476 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<1>1 SLICE_X2Y76.CLK Tas 0.339 i_SPI_if/sr_out<2> i_SPI_if/sr_out_1_glue_set i_SPI_if/sr_out_1 ------------------------------------------------- --------------------------- Total 6.444ns (1.523ns logic, 4.921ns route) (23.6% logic, 76.4% route) -------------------------------------------------------------------------------- Slack (setup path): 118.569ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_1 (FF) Requirement: 125.000ns Data Path Delay: 6.389ns (Levels of Logic = 3) Clock Path Skew: -0.007ns (0.295 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X14Y73.C3 net (fanout=26) 2.551 i_SPI_if/STATUS_5 SLICE_X14Y73.C Tilo 0.255 i_ipbus/my_ip_addr_udp<25> i_SPI_if/Mmux_IPADDR_i181 SLICE_X10Y74.B3 net (fanout=2) 0.894 ipaddr<25> SLICE_X10Y74.BMUX Topbb 0.444 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<1>1 i_SPI_if/mux1_5 i_SPI_if/mux1_3_f7 i_SPI_if/mux1_2_f8 SLICE_X2Y76.C2 net (fanout=1) 1.476 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<1>1 SLICE_X2Y76.CLK Tas 0.339 i_SPI_if/sr_out<2> i_SPI_if/sr_out_1_glue_set i_SPI_if/sr_out_1 ------------------------------------------------- --------------------------- Total 6.389ns (1.468ns logic, 4.921ns route) (23.0% logic, 77.0% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_out_2 (SLICE_X2Y76.D5), 30 paths -------------------------------------------------------------------------------- Slack (setup path): 117.475ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_2 (FF) Requirement: 125.000ns Data Path Delay: 7.483ns (Levels of Logic = 3) Clock Path Skew: -0.007ns (0.295 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X23Y70.C1 net (fanout=26) 3.835 i_SPI_if/STATUS_5 SLICE_X23Y70.C Tilo 0.259 i_ipbus/my_ip_addr_udp<2> i_SPI_if/Mmux_IPADDR_i231 SLICE_X12Y74.A5 net (fanout=2) 1.039 ipaddr<2> SLICE_X12Y74.BMUX Topab 0.438 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<2>1 i_SPI_if/mux2_4 i_SPI_if/mux2_3_f7 i_SPI_if/mux2_2_f8 SLICE_X2Y76.D5 net (fanout=1) 1.143 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<2>1 SLICE_X2Y76.CLK Tas 0.339 i_SPI_if/sr_out<2> i_SPI_if/sr_out_2_glue_set i_SPI_if/sr_out_2 ------------------------------------------------- --------------------------- Total 7.483ns (1.466ns logic, 6.017ns route) (19.6% logic, 80.4% route) -------------------------------------------------------------------------------- Slack (setup path): 118.567ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_2 (FF) Requirement: 125.000ns Data Path Delay: 6.391ns (Levels of Logic = 3) Clock Path Skew: -0.007ns (0.295 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X16Y73.C2 net (fanout=26) 2.878 i_SPI_if/STATUS_5 SLICE_X16Y73.CMUX Tilo 0.298 i_ipbus/my_ip_addr_udp<12> i_SPI_if/Mmux_IPADDR_i21 SLICE_X12Y74.A3 net (fanout=2) 0.865 ipaddr<10> SLICE_X12Y74.BMUX Topab 0.438 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<2>1 i_SPI_if/mux2_4 i_SPI_if/mux2_3_f7 i_SPI_if/mux2_2_f8 SLICE_X2Y76.D5 net (fanout=1) 1.143 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<2>1 SLICE_X2Y76.CLK Tas 0.339 i_SPI_if/sr_out<2> i_SPI_if/sr_out_2_glue_set i_SPI_if/sr_out_2 ------------------------------------------------- --------------------------- Total 6.391ns (1.505ns logic, 4.886ns route) (23.5% logic, 76.5% route) -------------------------------------------------------------------------------- Slack (setup path): 118.846ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_2 (FF) Requirement: 125.000ns Data Path Delay: 6.112ns (Levels of Logic = 3) Clock Path Skew: -0.007ns (0.295 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X15Y74.C1 net (fanout=26) 2.906 i_SPI_if/STATUS_5 SLICE_X15Y74.C Tilo 0.259 i_ipbus/my_ip_addr_udp<26> i_SPI_if/Mmux_IPADDR_i191 SLICE_X12Y74.B3 net (fanout=2) 0.612 ipaddr<26> SLICE_X12Y74.BMUX Topbb 0.423 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<2>1 i_SPI_if/mux2_5 i_SPI_if/mux2_3_f7 i_SPI_if/mux2_2_f8 SLICE_X2Y76.D5 net (fanout=1) 1.143 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<2>1 SLICE_X2Y76.CLK Tas 0.339 i_SPI_if/sr_out<2> i_SPI_if/sr_out_2_glue_set i_SPI_if/sr_out_2 ------------------------------------------------- --------------------------- Total 6.112ns (1.451ns logic, 4.661ns route) (23.7% logic, 76.3% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_out_3 (SLICE_X2Y75.A4), 29 paths -------------------------------------------------------------------------------- Slack (setup path): 117.820ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_3 (FF) Requirement: 125.000ns Data Path Delay: 7.136ns (Levels of Logic = 3) Clock Path Skew: -0.009ns (0.293 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X18Y72.D3 net (fanout=26) 3.452 i_SPI_if/STATUS_5 SLICE_X18Y72.D Tilo 0.254 i_ipbus/my_ip_addr_udp<27> i_SPI_if/Mmux_IPADDR_i201 SLICE_X10Y75.B4 net (fanout=2) 1.148 ipaddr<27> SLICE_X10Y75.BMUX Topbb 0.444 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<3>1 i_SPI_if/mux3_5 i_SPI_if/mux3_3_f7 i_SPI_if/mux3_2_f8 SLICE_X2Y75.A4 net (fanout=1) 1.069 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<3>1 SLICE_X2Y75.CLK Tas 0.339 i_SPI_if/sr_out<4> i_SPI_if/sr_out_3_glue_set i_SPI_if/sr_out_3 ------------------------------------------------- --------------------------- Total 7.136ns (1.467ns logic, 5.669ns route) (20.6% logic, 79.4% route) -------------------------------------------------------------------------------- Slack (setup path): 119.247ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5 (FF) Destination: i_SPI_if/sr_out_3 (FF) Requirement: 125.000ns Data Path Delay: 5.709ns (Levels of Logic = 3) Clock Path Skew: -0.009ns (0.293 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5 to i_SPI_if/sr_out_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y71.BQ Tcko 0.430 i_SPI_if/STATUS_7 i_SPI_if/STATUS_5 SLICE_X15Y71.D4 net (fanout=26) 2.304 i_SPI_if/STATUS_5 SLICE_X15Y71.D Tilo 0.259 i_ipbus/my_ip_addr_udp<3> i_SPI_if/Mmux_IPADDR_i261 SLICE_X10Y75.A6 net (fanout=2) 0.852 ipaddr<3> SLICE_X10Y75.BMUX Topab 0.456 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<3>1 i_SPI_if/mux3_4 i_SPI_if/mux3_3_f7 i_SPI_if/mux3_2_f8 SLICE_X2Y75.A4 net (fanout=1) 1.069 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<3>1 SLICE_X2Y75.CLK Tas 0.339 i_SPI_if/sr_out<4> i_SPI_if/sr_out_3_glue_set i_SPI_if/sr_out_3 ------------------------------------------------- --------------------------- Total 5.709ns (1.484ns logic, 4.225ns route) (26.0% logic, 74.0% route) -------------------------------------------------------------------------------- Slack (setup path): 119.851ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/addr_1 (FF) Destination: i_SPI_if/sr_out_3 (FF) Requirement: 125.000ns Data Path Delay: 5.096ns (Levels of Logic = 2) Clock Path Skew: -0.018ns (0.293 - 0.311) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/addr_1 to i_SPI_if/sr_out_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X1Y75.BQ Tcko 0.430 i_SPI_if/addr<3> i_SPI_if/addr_1 SLICE_X10Y75.D2 net (fanout=90) 2.777 i_SPI_if/addr<1> SLICE_X10Y75.BMUX Topdb 0.481 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<3>1 i_SPI_if/mux3_6 i_SPI_if/mux3_4_f7 i_SPI_if/mux3_2_f8 SLICE_X2Y75.A4 net (fanout=1) 1.069 i_SPI_if/addr[3]_GND_15_o_wide_mux_55_OUT<3>1 SLICE_X2Y75.CLK Tas 0.339 i_SPI_if/sr_out<4> i_SPI_if/sr_out_3_glue_set i_SPI_if/sr_out_3 ------------------------------------------------- --------------------------- Total 5.096ns (1.250ns logic, 3.846ns route) (24.5% logic, 75.5% route) -------------------------------------------------------------------------------- Hold Paths: TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 250 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_in_6 (SLICE_X0Y76.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.407ns (requirement - (clock path skew + uncertainty - data path)) Source: i_SPI_if/sr_in_5 (FF) Destination: i_SPI_if/sr_in_6 (FF) Requirement: 0.000ns Data Path Delay: 0.407ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: S6_SCK rising at 250.000ns Destination Clock: S6_SCK rising at 250.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_SPI_if/sr_in_5 to i_SPI_if/sr_in_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y76.CQ Tcko 0.200 i_SPI_if/sr_in<6> i_SPI_if/sr_in_5 SLICE_X0Y76.DX net (fanout=13) 0.159 i_SPI_if/sr_in<5> SLICE_X0Y76.CLK Tckdi (-Th) -0.048 i_SPI_if/sr_in<6> i_SPI_if/sr_in_6 ------------------------------------------------- --------------------------- Total 0.407ns (0.248ns logic, 0.159ns route) (60.9% logic, 39.1% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/addr_4 (SLICE_X0Y80.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.416ns (requirement - (clock path skew + uncertainty - data path)) Source: i_SPI_if/addr_4 (FF) Destination: i_SPI_if/addr_4 (FF) Requirement: 0.000ns Data Path Delay: 0.416ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: S6_SCK rising at 250.000ns Destination Clock: S6_SCK rising at 250.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_SPI_if/addr_4 to i_SPI_if/addr_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y80.AQ Tcko 0.200 i_SPI_if/addr<7> i_SPI_if/addr_4 SLICE_X0Y80.A6 net (fanout=4) 0.026 i_SPI_if/addr<4> SLICE_X0Y80.CLK Tah (-Th) -0.190 i_SPI_if/addr<7> i_SPI_if/Mmux_addr[15]_sr_in[6]_mux_41_OUT111 i_SPI_if/addr_4 ------------------------------------------------- --------------------------- Total 0.416ns (0.390ns logic, 0.026ns route) (93.8% logic, 6.2% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/addr_7 (SLICE_X0Y80.D6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.416ns (requirement - (clock path skew + uncertainty - data path)) Source: i_SPI_if/addr_7 (FF) Destination: i_SPI_if/addr_7 (FF) Requirement: 0.000ns Data Path Delay: 0.416ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: S6_SCK rising at 250.000ns Destination Clock: S6_SCK rising at 250.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_SPI_if/addr_7 to i_SPI_if/addr_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y80.DQ Tcko 0.200 i_SPI_if/addr<7> i_SPI_if/addr_7 SLICE_X0Y80.D6 net (fanout=4) 0.026 i_SPI_if/addr<7> SLICE_X0Y80.CLK Tah (-Th) -0.190 i_SPI_if/addr<7> i_SPI_if/Mmux_addr[15]_sr_in[6]_mux_41_OUT141 i_SPI_if/addr_7 ------------------------------------------------- --------------------------- Total 0.416ns (0.390ns logic, 0.026ns route) (93.8% logic, 6.2% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 250 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 247.334ns (period - min period limit) Period: 250.000ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: i_S6_SCK/I0 Logical resource: i_S6_SCK/I0 Location pin: BUFGMUX_X3Y15.I0 Clock network: T1_SCK_OBUF -------------------------------------------------------------------------------- Slack: 248.134ns (period - min period limit) Period: 250.000ns Min period limit: 1.866ns (535.906MHz) (Tickper) Physical resource: T1_MOSI_OBUF/CLK0 Logical resource: i_SPI_if/sr_in_0/CLK0 Location pin: ILOGIC_X0Y68.CLK0 Clock network: S6_SCK -------------------------------------------------------------------------------- Slack: 249.520ns (period - min period limit) Period: 250.000ns Min period limit: 0.480ns (2083.333MHz) (Tcp) Physical resource: S6_MISO/CLK Logical resource: i_SPI_if/sr_out_7/CK Location pin: SLICE_X2Y71.CLK Clock network: S6_SCK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTC_REFCLK = PERIOD TIMEGRP "TTC_REFCLK" 24.9 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 10.000ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTC_REFCLK = PERIOD TIMEGRP "TTC_REFCLK" 24.9 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 5.173ns (period - min period limit) Period: 6.225ns Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax)) Physical resource: i_DCM_TTCclk/PLL_ADV/CLKOUT1 Logical resource: i_DCM_TTCclk/PLL_ADV/CLKOUT1 Location pin: PLL_ADV_X0Y2.CLKOUT1 Clock network: TTCclk4x_dcm -------------------------------------------------------------------------------- Slack: 14.900ns (period - (min low pulse limit / (low pulse / period))) Period: 24.900ns Low pulse: 12.450ns Low pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50) Physical resource: i_DCM_TTCclk/PLL_ADV/CLKIN1 Logical resource: i_DCM_TTCclk/PLL_ADV/CLKIN1 Location pin: PLL_ADV_X0Y2.CLKIN2 Clock network: i_DCM_TTCclk/PLL_ADV_ML_NEW_DIVCLK -------------------------------------------------------------------------------- Slack: 14.900ns (period - (min high pulse limit / (high pulse / period))) Period: 24.900ns High pulse: 12.450ns High pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50) Physical resource: i_DCM_TTCclk/PLL_ADV/CLKIN1 Logical resource: i_DCM_TTCclk/PLL_ADV/CLKIN1 Location pin: PLL_ADV_X0Y2.CLKIN2 Clock network: i_DCM_TTCclk/PLL_ADV_ML_NEW_DIVCLK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclk_p = PERIOD TIMEGRP "TTCclk_p" 24.9 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 16.000ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclk_p = PERIOD TIMEGRP "TTCclk_p" 24.9 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 8.900ns (period - (min low pulse limit / (low pulse / period))) Period: 24.900ns Low pulse: 12.450ns Low pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50) Physical resource: g_TTCclkOut[0].i_DCM_TTCclkOut/CLKIN Logical resource: g_TTCclkOut[0].i_DCM_TTCclkOut/CLKIN Location pin: DCM_X0Y3.CLKIN Clock network: g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK -------------------------------------------------------------------------------- Slack: 8.900ns (period - (min high pulse limit / (high pulse / period))) Period: 24.900ns High pulse: 12.450ns High pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50) Physical resource: g_TTCclkOut[0].i_DCM_TTCclkOut/CLKIN Logical resource: g_TTCclkOut[0].i_DCM_TTCclkOut/CLKIN Location pin: DCM_X0Y3.CLKIN Clock network: g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK -------------------------------------------------------------------------------- Slack: 8.900ns (period - (min low pulse limit / (low pulse / period))) Period: 24.900ns Low pulse: 12.450ns Low pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50) Physical resource: g_TTCclkOut[1].i_DCM_TTCclkOut/CLKIN Logical resource: g_TTCclkOut[1].i_DCM_TTCclkOut/CLKIN Location pin: DCM_X0Y1.CLKIN Clock network: g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 62790 paths analyzed, 16162 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 8.000ns. -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/status_buffer/history_121 (SLICE_X34Y86.SR), 13 paths -------------------------------------------------------------------------------- Slack (setup path): 0.453ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdvld (FF) Destination: i_ipbus/udp_if/status_buffer/history_121 (FF) Requirement: 8.000ns Data Path Delay: 7.324ns (Levels of Logic = 3) Clock Path Skew: -0.088ns (0.584 - 0.672) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdvld to i_ipbus/udp_if/status_buffer/history_121 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y65.AQ Tcko 0.430 GbErxdvld i_GTP_if/i_mac/emacclientrxdvld SLICE_X16Y63.A5 net (fanout=218) 0.661 GbErxdvld SLICE_X16Y63.A Tilo 0.235 i_ipbus/udp_if/rx_packet_parser/ping.pkt_data<19> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X29Y79.A1 net (fanout=675) 3.035 i_ipbus/udp_if/rx_reset SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X35Y86.B5 net (fanout=15) 1.332 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X35Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history<108> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X34Y86.SR net (fanout=4) 0.569 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X34Y86.CLK Tsrck 0.544 i_ipbus/udp_if/status_buffer/history<113> i_ipbus/udp_if/status_buffer/history_121 ------------------------------------------------- --------------------------- Total 7.324ns (1.727ns logic, 5.597ns route) (23.6% logic, 76.4% route) -------------------------------------------------------------------------------- Slack (setup path): 0.626ns (requirement - (data path - clock path skew + uncertainty)) Source: rst_ipbus (FF) Destination: i_ipbus/udp_if/status_buffer/history_121 (FF) Requirement: 8.000ns Data Path Delay: 7.173ns (Levels of Logic = 4) Clock Path Skew: -0.066ns (0.584 - 0.650) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: rst_ipbus to i_ipbus/udp_if/status_buffer/history_121 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y95.BMUX Tshcko 0.518 N61 rst_ipbus SLICE_X33Y86.B6 net (fanout=2) 1.460 rst_ipbus SLICE_X33Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.async_pending GbEGTPreset1 SLICE_X26Y79.A5 net (fanout=702) 1.285 GbEGTPreset SLICE_X26Y79.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X29Y79.A5 net (fanout=1) 0.434 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_138_o_MUX_1259_o SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X35Y86.B5 net (fanout=15) 1.332 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X35Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history<108> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X34Y86.SR net (fanout=4) 0.569 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X34Y86.CLK Tsrck 0.544 i_ipbus/udp_if/status_buffer/history<113> i_ipbus/udp_if/status_buffer/history_121 ------------------------------------------------- --------------------------- Total 7.173ns (2.093ns logic, 5.080ns route) (29.2% logic, 70.8% route) -------------------------------------------------------------------------------- Slack (setup path): 0.683ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/udp_if/rx_reset_block/rx_reset_sig (FF) Destination: i_ipbus/udp_if/status_buffer/history_121 (FF) Requirement: 8.000ns Data Path Delay: 7.094ns (Levels of Logic = 3) Clock Path Skew: -0.088ns (0.584 - 0.672) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/udp_if/rx_reset_block/rx_reset_sig to i_ipbus/udp_if/status_buffer/history_121 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X16Y65.AQ Tcko 0.476 i_ipbus/udp_if/rx_reset_block/rx_reset_sig i_ipbus/udp_if/rx_reset_block/rx_reset_sig SLICE_X16Y63.A6 net (fanout=1) 0.385 i_ipbus/udp_if/rx_reset_block/rx_reset_sig SLICE_X16Y63.A Tilo 0.235 i_ipbus/udp_if/rx_packet_parser/ping.pkt_data<19> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X29Y79.A1 net (fanout=675) 3.035 i_ipbus/udp_if/rx_reset SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X35Y86.B5 net (fanout=15) 1.332 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X35Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history<108> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X34Y86.SR net (fanout=4) 0.569 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X34Y86.CLK Tsrck 0.544 i_ipbus/udp_if/status_buffer/history<113> i_ipbus/udp_if/status_buffer/history_121 ------------------------------------------------- --------------------------- Total 7.094ns (1.773ns logic, 5.321ns route) (25.0% logic, 75.0% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/status_buffer/history_54 (SLICE_X25Y78.SR), 13 paths -------------------------------------------------------------------------------- Slack (setup path): 0.476ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdvld (FF) Destination: i_ipbus/udp_if/status_buffer/history_54 (FF) Requirement: 8.000ns Data Path Delay: 7.376ns (Levels of Logic = 3) Clock Path Skew: -0.013ns (0.301 - 0.314) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdvld to i_ipbus/udp_if/status_buffer/history_54 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y65.AQ Tcko 0.430 GbErxdvld i_GTP_if/i_mac/emacclientrxdvld SLICE_X16Y63.A5 net (fanout=218) 0.661 GbErxdvld SLICE_X16Y63.A Tilo 0.235 i_ipbus/udp_if/rx_packet_parser/ping.pkt_data<19> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X29Y79.A1 net (fanout=675) 3.035 i_ipbus/udp_if/rx_reset SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X25Y79.C4 net (fanout=15) 0.629 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X25Y79.CMUX Tilo 0.337 i_ipbus/udp_if/status_buffer/history_block.async_payload<4> i_ipbus/udp_if/status_buffer/_n02111_1 SLICE_X25Y78.SR net (fanout=5) 1.322 i_ipbus/udp_if/status_buffer/_n02111 SLICE_X25Y78.CLK Tsrck 0.468 i_ipbus/udp_if/status_buffer/history<54> i_ipbus/udp_if/status_buffer/history_54 ------------------------------------------------- --------------------------- Total 7.376ns (1.729ns logic, 5.647ns route) (23.4% logic, 76.6% route) -------------------------------------------------------------------------------- Slack (setup path): 0.633ns (requirement - (data path - clock path skew + uncertainty)) Source: rst_ipbus (FF) Destination: i_ipbus/udp_if/status_buffer/history_54 (FF) Requirement: 8.000ns Data Path Delay: 7.225ns (Levels of Logic = 4) Clock Path Skew: -0.007ns (0.643 - 0.650) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: rst_ipbus to i_ipbus/udp_if/status_buffer/history_54 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y95.BMUX Tshcko 0.518 N61 rst_ipbus SLICE_X33Y86.B6 net (fanout=2) 1.460 rst_ipbus SLICE_X33Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.async_pending GbEGTPreset1 SLICE_X26Y79.A5 net (fanout=702) 1.285 GbEGTPreset SLICE_X26Y79.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X29Y79.A5 net (fanout=1) 0.434 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_138_o_MUX_1259_o SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X25Y79.C4 net (fanout=15) 0.629 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X25Y79.CMUX Tilo 0.337 i_ipbus/udp_if/status_buffer/history_block.async_payload<4> i_ipbus/udp_if/status_buffer/_n02111_1 SLICE_X25Y78.SR net (fanout=5) 1.322 i_ipbus/udp_if/status_buffer/_n02111 SLICE_X25Y78.CLK Tsrck 0.468 i_ipbus/udp_if/status_buffer/history<54> i_ipbus/udp_if/status_buffer/history_54 ------------------------------------------------- --------------------------- Total 7.225ns (2.095ns logic, 5.130ns route) (29.0% logic, 71.0% route) -------------------------------------------------------------------------------- Slack (setup path): 0.706ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/udp_if/rx_reset_block/rx_reset_sig (FF) Destination: i_ipbus/udp_if/status_buffer/history_54 (FF) Requirement: 8.000ns Data Path Delay: 7.146ns (Levels of Logic = 3) Clock Path Skew: -0.013ns (0.301 - 0.314) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/udp_if/rx_reset_block/rx_reset_sig to i_ipbus/udp_if/status_buffer/history_54 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X16Y65.AQ Tcko 0.476 i_ipbus/udp_if/rx_reset_block/rx_reset_sig i_ipbus/udp_if/rx_reset_block/rx_reset_sig SLICE_X16Y63.A6 net (fanout=1) 0.385 i_ipbus/udp_if/rx_reset_block/rx_reset_sig SLICE_X16Y63.A Tilo 0.235 i_ipbus/udp_if/rx_packet_parser/ping.pkt_data<19> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X29Y79.A1 net (fanout=675) 3.035 i_ipbus/udp_if/rx_reset SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X25Y79.C4 net (fanout=15) 0.629 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X25Y79.CMUX Tilo 0.337 i_ipbus/udp_if/status_buffer/history_block.async_payload<4> i_ipbus/udp_if/status_buffer/_n02111_1 SLICE_X25Y78.SR net (fanout=5) 1.322 i_ipbus/udp_if/status_buffer/_n02111 SLICE_X25Y78.CLK Tsrck 0.468 i_ipbus/udp_if/status_buffer/history<54> i_ipbus/udp_if/status_buffer/history_54 ------------------------------------------------- --------------------------- Total 7.146ns (1.775ns logic, 5.371ns route) (24.8% logic, 75.2% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/status_buffer/history_120 (SLICE_X34Y86.SR), 13 paths -------------------------------------------------------------------------------- Slack (setup path): 0.493ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdvld (FF) Destination: i_ipbus/udp_if/status_buffer/history_120 (FF) Requirement: 8.000ns Data Path Delay: 7.284ns (Levels of Logic = 3) Clock Path Skew: -0.088ns (0.584 - 0.672) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdvld to i_ipbus/udp_if/status_buffer/history_120 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y65.AQ Tcko 0.430 GbErxdvld i_GTP_if/i_mac/emacclientrxdvld SLICE_X16Y63.A5 net (fanout=218) 0.661 GbErxdvld SLICE_X16Y63.A Tilo 0.235 i_ipbus/udp_if/rx_packet_parser/ping.pkt_data<19> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X29Y79.A1 net (fanout=675) 3.035 i_ipbus/udp_if/rx_reset SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X35Y86.B5 net (fanout=15) 1.332 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X35Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history<108> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X34Y86.SR net (fanout=4) 0.569 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X34Y86.CLK Tsrck 0.504 i_ipbus/udp_if/status_buffer/history<113> i_ipbus/udp_if/status_buffer/history_120 ------------------------------------------------- --------------------------- Total 7.284ns (1.687ns logic, 5.597ns route) (23.2% logic, 76.8% route) -------------------------------------------------------------------------------- Slack (setup path): 0.666ns (requirement - (data path - clock path skew + uncertainty)) Source: rst_ipbus (FF) Destination: i_ipbus/udp_if/status_buffer/history_120 (FF) Requirement: 8.000ns Data Path Delay: 7.133ns (Levels of Logic = 4) Clock Path Skew: -0.066ns (0.584 - 0.650) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: rst_ipbus to i_ipbus/udp_if/status_buffer/history_120 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y95.BMUX Tshcko 0.518 N61 rst_ipbus SLICE_X33Y86.B6 net (fanout=2) 1.460 rst_ipbus SLICE_X33Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.async_pending GbEGTPreset1 SLICE_X26Y79.A5 net (fanout=702) 1.285 GbEGTPreset SLICE_X26Y79.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X29Y79.A5 net (fanout=1) 0.434 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_138_o_MUX_1259_o SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X35Y86.B5 net (fanout=15) 1.332 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X35Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history<108> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X34Y86.SR net (fanout=4) 0.569 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X34Y86.CLK Tsrck 0.504 i_ipbus/udp_if/status_buffer/history<113> i_ipbus/udp_if/status_buffer/history_120 ------------------------------------------------- --------------------------- Total 7.133ns (2.053ns logic, 5.080ns route) (28.8% logic, 71.2% route) -------------------------------------------------------------------------------- Slack (setup path): 0.723ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/udp_if/rx_reset_block/rx_reset_sig (FF) Destination: i_ipbus/udp_if/status_buffer/history_120 (FF) Requirement: 8.000ns Data Path Delay: 7.054ns (Levels of Logic = 3) Clock Path Skew: -0.088ns (0.584 - 0.672) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/udp_if/rx_reset_block/rx_reset_sig to i_ipbus/udp_if/status_buffer/history_120 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X16Y65.AQ Tcko 0.476 i_ipbus/udp_if/rx_reset_block/rx_reset_sig i_ipbus/udp_if/rx_reset_block/rx_reset_sig SLICE_X16Y63.A6 net (fanout=1) 0.385 i_ipbus/udp_if/rx_reset_block/rx_reset_sig SLICE_X16Y63.A Tilo 0.235 i_ipbus/udp_if/rx_packet_parser/ping.pkt_data<19> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X29Y79.A1 net (fanout=675) 3.035 i_ipbus/udp_if/rx_reset SLICE_X29Y79.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history<63> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1266_o141 SLICE_X35Y86.B5 net (fanout=15) 1.332 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1270_o SLICE_X35Y86.B Tilo 0.259 i_ipbus/udp_if/status_buffer/history<108> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X34Y86.SR net (fanout=4) 0.569 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X34Y86.CLK Tsrck 0.504 i_ipbus/udp_if/status_buffer/history<113> i_ipbus/udp_if/status_buffer/history_120 ------------------------------------------------- --------------------------- Total 7.054ns (1.733ns logic, 5.321ns route) (24.6% logic, 75.4% route) -------------------------------------------------------------------------------- Hold Paths: TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y22.WEB1), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.295ns (requirement - (clock path skew + uncertainty - data path)) Source: i_flash/web_1 (FF) Destination: i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 0.000ns Data Path Delay: 0.298ns (Levels of Logic = 0) Clock Path Skew: 0.003ns (0.076 - 0.073) Source Clock: sysclk rising at 8.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_flash/web_1 to i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X40Y45.BQ Tcko 0.200 i_flash/web<3> i_flash/web_1 RAMB16_X2Y22.WEB1 net (fanout=1) 0.151 i_flash/web<1> RAMB16_X2Y22.CLKB Trckc_WEB (-Th) 0.053 i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 0.298ns (0.147ns logic, 0.151ns route) (49.3% logic, 50.7% route) -------------------------------------------------------------------------------- Paths for end point i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i (GTPA1_DUAL_X0Y0.TXDATA17), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.299ns (requirement - (clock path skew + uncertainty - data path)) Source: i_GTP_if/i_GbE_pcs_pma/BU2/U0/TXDATA_7 (FF) Destination: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i (HSIO) Requirement: 0.000ns Data Path Delay: 0.349ns (Levels of Logic = 0) Clock Path Skew: 0.050ns (0.120 - 0.070) Source Clock: sysclk rising at 8.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_GTP_if/i_GbE_pcs_pma/BU2/U0/TXDATA_7 to i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------------- ------------------- SLICE_X29Y115.DMUX Tshcko 0.244 i_GTP_if/GbEtxdata<3> i_GTP_if/i_GbE_pcs_pma/BU2/U0/TXDATA_7 GTPA1_DUAL_X0Y0.TXDATA17 net (fanout=1) 0.605 i_GTP_if/GbEtxdata<7> GTPA1_DUAL_X0Y0.TXUSRCLK21 Tgtpckc_TXDATA(-Th) 0.500 i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i ------------------------------------------------------- --------------------------- Total 0.349ns (-0.256ns logic, 0.605ns route) (-73.4% logic, 173.4% route) -------------------------------------------------------------------------------- Paths for end point i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y50.ADDRB4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.306ns (requirement - (clock path skew + uncertainty - data path)) Source: i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 (FF) Destination: i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM) Requirement: 0.000ns Data Path Delay: 0.312ns (Levels of Logic = 0) Clock Path Skew: 0.006ns (0.071 - 0.065) Source Clock: sysclk rising at 8.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 to i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X39Y102.AQ Tcko 0.198 i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8> i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 RAMB16_X2Y50.ADDRB4 net (fanout=4) 0.180 i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1> RAMB16_X2Y50.CLKB Trckc_ADDRB (-Th) 0.066 i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram ------------------------------------------------- --------------------------- Total 0.312ns (0.132ns logic, 0.180ns route) (42.3% logic, 57.7% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 0.000ns (period - min period limit) Period: 8.000ns Min period limit: 8.000ns (125.000MHz) (Tgtpcper_RXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK20 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK20 Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK20 Clock network: sysclk -------------------------------------------------------------------------------- Slack: 0.000ns (period - min period limit) Period: 8.000ns Min period limit: 8.000ns (125.000MHz) (Tgtpcper_RXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK21 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK21 Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK21 Clock network: sysclk -------------------------------------------------------------------------------- Slack: 0.000ns (period - min period limit) Period: 8.000ns Min period limit: 8.000ns (125.000MHz) (Tgtpcper_TXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK20 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK20 Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK20 Clock network: sysclk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_sysclk2x = PERIOD TIMEGRP "sysclk2x" 4 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 3.703ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_sysclk2x = PERIOD TIMEGRP "sysclk2x" 4 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 0.297ns (period - min period limit) Period: 4.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_RXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK0 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK0 Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK0 Clock network: sysclk2x -------------------------------------------------------------------------------- Slack: 0.297ns (period - min period limit) Period: 4.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_TXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK0 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK0 Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK0 Clock network: sysclk2x -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 25799 paths analyzed, 3339 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 18.084ns. -------------------------------------------------------------------------------- Paths for end point i_FLASH_C_ddr (OLOGIC_X26Y1.D2), 2 paths -------------------------------------------------------------------------------- Slack (setup path): 6.958ns (requirement - (data path - clock path skew + uncertainty)) Source: en_conf (FF) Destination: i_FLASH_C_ddr (FF) Requirement: 16.000ns Data Path Delay: 9.315ns (Levels of Logic = 1) Clock Path Skew: 0.458ns (1.203 - 0.745) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk falling at 16.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: en_conf to i_FLASH_C_ddr Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y67.CQ Tcko 0.430 rst_CRC en_conf SLICE_X45Y42.A5 net (fanout=35) 3.748 en_conf SLICE_X45Y42.A Tilo 0.259 i_flash/en_FLASH_inv en_flash_c1 OLOGIC_X26Y1.D2 net (fanout=1) 3.909 en_flash_c OLOGIC_X26Y1.CLK1 Todck 0.969 FLASH_C_OBUF i_FLASH_C_ddr ------------------------------------------------- --------------------------- Total 9.315ns (1.658ns logic, 7.657ns route) (17.8% logic, 82.2% route) -------------------------------------------------------------------------------- Slack (setup path): 9.501ns (requirement - (data path - clock path skew + uncertainty)) Source: i_flash/MCS_1 (FF) Destination: i_FLASH_C_ddr (FF) Requirement: 16.000ns Data Path Delay: 6.806ns (Levels of Logic = 1) Clock Path Skew: 0.492ns (1.111 - 0.619) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk falling at 16.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_flash/MCS_1 to i_FLASH_C_ddr Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y42.BQ Tcko 0.430 flash_mcs<1> i_flash/MCS_1 SLICE_X45Y42.A4 net (fanout=2) 1.239 flash_mcs<1> SLICE_X45Y42.A Tilo 0.259 i_flash/en_FLASH_inv en_flash_c1 OLOGIC_X26Y1.D2 net (fanout=1) 3.909 en_flash_c OLOGIC_X26Y1.CLK1 Todck 0.969 FLASH_C_OBUF i_FLASH_C_ddr ------------------------------------------------- --------------------------- Total 6.806ns (1.658ns logic, 5.148ns route) (24.4% logic, 75.6% route) -------------------------------------------------------------------------------- Paths for end point i_V6CCLK_ddr (OLOGIC_X26Y119.D2), 1 path -------------------------------------------------------------------------------- Slack (setup path): 9.250ns (requirement - (data path - clock path skew + uncertainty)) Source: en_CCLK (FF) Destination: i_V6CCLK_ddr (FF) Requirement: 16.000ns Data Path Delay: 7.009ns (Levels of Logic = 0) Clock Path Skew: 0.444ns (1.096 - 0.652) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk falling at 16.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: en_CCLK to i_V6CCLK_ddr Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X35Y65.BMUX Tshcko 0.518 calc_CRC en_CCLK OLOGIC_X26Y119.D2 net (fanout=2) 5.522 en_CCLK OLOGIC_X26Y119.CLK1 Todck 0.969 V6_CCLK_OBUF i_V6CCLK_ddr ------------------------------------------------- --------------------------- Total 7.009ns (1.487ns logic, 5.522ns route) (21.2% logic, 78.8% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 (RAMB16_X2Y42.DIA0), 126 paths -------------------------------------------------------------------------------- Slack (setup path): 16.482ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/trans/sm/addr_1 (FF) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 (RAM) Requirement: 32.000ns Data Path Delay: 15.296ns (Levels of Logic = 7) Clock Path Skew: -0.037ns (0.676 - 0.713) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/trans/sm/addr_1 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y41.BQ Tcko 0.476 ipb_master_out_ipb_addr<3> i_ipbus/trans/sm/addr_1 SLICE_X21Y21.A3 net (fanout=230) 4.136 ipb_master_out_ipb_addr<1> SLICE_X21Y21.A Tilo 0.259 delay_twinmux_10<3> Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_161_OUT_81 SLICE_X32Y27.B6 net (fanout=1) 1.361 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_161_OUT_81 SLICE_X32Y27.B Tilo 0.235 delay_TRIG0<3> Mmux_ipb_master_in_ipb_rdata492 SLICE_X40Y38.B5 net (fanout=2) 1.396 Mmux_ipb_master_in_ipb_rdata491 SLICE_X40Y38.B Tilo 0.235 N95 Mmux_ipb_master_in_ipb_rdata495_SW1 SLICE_X41Y44.B2 net (fanout=1) 1.197 N95 SLICE_X41Y44.B Tilo 0.259 i_ipbus/trans/sm/rmw_input<3> Mmux_ipb_master_in_ipb_rdata496 SLICE_X41Y44.A5 net (fanout=1) 0.230 Mmux_ipb_master_in_ipb_rdata495 SLICE_X41Y44.A Tilo 0.259 i_ipbus/trans/sm/rmw_input<3> Mmux_ipb_master_in_ipb_rdata497 SLICE_X34Y58.B5 net (fanout=1) 1.401 ipb_master_in_ipb_rdata<2> SLICE_X34Y58.B Tilo 0.254 i_ipbus/trans/cfg_dout<29> i_ipbus/trans/sm/mux101121 SLICE_X34Y58.A5 net (fanout=1) 0.247 i_ipbus/trans/tx_data<2> SLICE_X34Y58.A Tilo 0.254 i_ipbus/trans/cfg_dout<29> i_ipbus/trans/iface/Mmux_trans_out_wdata231 RAMB16_X2Y42.DIA0 net (fanout=1) 2.797 i_ipbus/trans_out_wdata<2> RAMB16_X2Y42.CLKA Trdck_DIA 0.300 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 ------------------------------------------------- --------------------------- Total 15.296ns (2.531ns logic, 12.765ns route) (16.5% logic, 83.5% route) -------------------------------------------------------------------------------- Slack (setup path): 16.638ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/trans/sm/addr_0 (FF) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 (RAM) Requirement: 32.000ns Data Path Delay: 15.140ns (Levels of Logic = 7) Clock Path Skew: -0.037ns (0.676 - 0.713) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/trans/sm/addr_0 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y41.AQ Tcko 0.476 ipb_master_out_ipb_addr<3> i_ipbus/trans/sm/addr_0 SLICE_X21Y21.A6 net (fanout=250) 3.980 ipb_master_out_ipb_addr<0> SLICE_X21Y21.A Tilo 0.259 delay_twinmux_10<3> Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_161_OUT_81 SLICE_X32Y27.B6 net (fanout=1) 1.361 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_161_OUT_81 SLICE_X32Y27.B Tilo 0.235 delay_TRIG0<3> Mmux_ipb_master_in_ipb_rdata492 SLICE_X40Y38.B5 net (fanout=2) 1.396 Mmux_ipb_master_in_ipb_rdata491 SLICE_X40Y38.B Tilo 0.235 N95 Mmux_ipb_master_in_ipb_rdata495_SW1 SLICE_X41Y44.B2 net (fanout=1) 1.197 N95 SLICE_X41Y44.B Tilo 0.259 i_ipbus/trans/sm/rmw_input<3> Mmux_ipb_master_in_ipb_rdata496 SLICE_X41Y44.A5 net (fanout=1) 0.230 Mmux_ipb_master_in_ipb_rdata495 SLICE_X41Y44.A Tilo 0.259 i_ipbus/trans/sm/rmw_input<3> Mmux_ipb_master_in_ipb_rdata497 SLICE_X34Y58.B5 net (fanout=1) 1.401 ipb_master_in_ipb_rdata<2> SLICE_X34Y58.B Tilo 0.254 i_ipbus/trans/cfg_dout<29> i_ipbus/trans/sm/mux101121 SLICE_X34Y58.A5 net (fanout=1) 0.247 i_ipbus/trans/tx_data<2> SLICE_X34Y58.A Tilo 0.254 i_ipbus/trans/cfg_dout<29> i_ipbus/trans/iface/Mmux_trans_out_wdata231 RAMB16_X2Y42.DIA0 net (fanout=1) 2.797 i_ipbus/trans_out_wdata<2> RAMB16_X2Y42.CLKA Trdck_DIA 0.300 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 ------------------------------------------------- --------------------------- Total 15.140ns (2.531ns logic, 12.609ns route) (16.7% logic, 83.3% route) -------------------------------------------------------------------------------- Slack (setup path): 16.879ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/trans/sm/addr_1 (FF) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 (RAM) Requirement: 32.000ns Data Path Delay: 14.899ns (Levels of Logic = 7) Clock Path Skew: -0.037ns (0.676 - 0.713) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/trans/sm/addr_1 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y41.BQ Tcko 0.476 ipb_master_out_ipb_addr<3> i_ipbus/trans/sm/addr_1 SLICE_X21Y21.A3 net (fanout=230) 4.136 ipb_master_out_ipb_addr<1> SLICE_X21Y21.A Tilo 0.259 delay_twinmux_10<3> Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_161_OUT_81 SLICE_X32Y27.B6 net (fanout=1) 1.361 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_161_OUT_81 SLICE_X32Y27.B Tilo 0.235 delay_TRIG0<3> Mmux_ipb_master_in_ipb_rdata492 SLICE_X32Y27.A5 net (fanout=2) 0.205 Mmux_ipb_master_in_ipb_rdata491 SLICE_X32Y27.A Tilo 0.235 delay_TRIG0<3> Mmux_ipb_master_in_ipb_rdata495_SW0 SLICE_X41Y44.B3 net (fanout=1) 1.991 N94 SLICE_X41Y44.B Tilo 0.259 i_ipbus/trans/sm/rmw_input<3> Mmux_ipb_master_in_ipb_rdata496 SLICE_X41Y44.A5 net (fanout=1) 0.230 Mmux_ipb_master_in_ipb_rdata495 SLICE_X41Y44.A Tilo 0.259 i_ipbus/trans/sm/rmw_input<3> Mmux_ipb_master_in_ipb_rdata497 SLICE_X34Y58.B5 net (fanout=1) 1.401 ipb_master_in_ipb_rdata<2> SLICE_X34Y58.B Tilo 0.254 i_ipbus/trans/cfg_dout<29> i_ipbus/trans/sm/mux101121 SLICE_X34Y58.A5 net (fanout=1) 0.247 i_ipbus/trans/tx_data<2> SLICE_X34Y58.A Tilo 0.254 i_ipbus/trans/cfg_dout<29> i_ipbus/trans/iface/Mmux_trans_out_wdata231 RAMB16_X2Y42.DIA0 net (fanout=1) 2.797 i_ipbus/trans_out_wdata<2> RAMB16_X2Y42.CLKA Trdck_DIA 0.300 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram2 ------------------------------------------------- --------------------------- Total 14.899ns (2.531ns logic, 12.368ns route) (17.0% logic, 83.0% route) -------------------------------------------------------------------------------- Hold Paths: TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/clock_crossing_if/req_send_buf_2 (SLICE_X31Y63.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.399ns (requirement - (clock path skew + uncertainty - data path)) Source: i_ipbus/udp_if/clock_crossing_if/req_send_buf_1 (FF) Destination: i_ipbus/udp_if/clock_crossing_if/req_send_buf_2 (FF) Requirement: 0.000ns Data Path Delay: 0.399ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_ipbus/udp_if/clock_crossing_if/req_send_buf_1 to i_ipbus/udp_if/clock_crossing_if/req_send_buf_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X31Y63.CQ Tcko 0.198 i_ipbus/udp_if/clock_crossing_if/req_send_buf<2> i_ipbus/udp_if/clock_crossing_if/req_send_buf_1 SLICE_X31Y63.DX net (fanout=2) 0.142 i_ipbus/udp_if/clock_crossing_if/req_send_buf<1> SLICE_X31Y63.CLK Tckdi (-Th) -0.059 i_ipbus/udp_if/clock_crossing_if/req_send_buf<2> i_ipbus/udp_if/clock_crossing_if/req_send_buf_2 ------------------------------------------------- --------------------------- Total 0.399ns (0.257ns logic, 0.142ns route) (64.4% logic, 35.6% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/clock_crossing_if/rx_read_buffer_2 (SLICE_X25Y71.C5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.405ns (requirement - (clock path skew + uncertainty - data path)) Source: i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf_2 (FF) Destination: i_ipbus/udp_if/clock_crossing_if/rx_read_buffer_2 (FF) Requirement: 0.000ns Data Path Delay: 0.405ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf_2 to i_ipbus/udp_if/clock_crossing_if/rx_read_buffer_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X25Y71.CQ Tcko 0.198 i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf<3> i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf_2 SLICE_X25Y71.C5 net (fanout=1) 0.052 i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf<2> SLICE_X25Y71.CLK Tah (-Th) -0.155 i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf<3> i_ipbus/udp_if/clock_crossing_if/rx_read_buf_buf<2>_rt i_ipbus/udp_if/clock_crossing_if/rx_read_buffer_2 ------------------------------------------------- --------------------------- Total 0.405ns (0.353ns logic, 0.052ns route) (87.2% logic, 12.8% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/clock_crossing_if/tx_write_buffer_2 (SLICE_X37Y83.C5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.405ns (requirement - (clock path skew + uncertainty - data path)) Source: i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf_2 (FF) Destination: i_ipbus/udp_if/clock_crossing_if/tx_write_buffer_2 (FF) Requirement: 0.000ns Data Path Delay: 0.405ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf_2 to i_ipbus/udp_if/clock_crossing_if/tx_write_buffer_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X37Y83.CQ Tcko 0.198 i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf<3> i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf_2 SLICE_X37Y83.C5 net (fanout=1) 0.052 i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf<2> SLICE_X37Y83.CLK Tah (-Th) -0.155 i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf<3> i_ipbus/udp_if/clock_crossing_if/tx_write_buf_buf<2>_rt i_ipbus/udp_if/clock_crossing_if/tx_write_buffer_2 ------------------------------------------------- --------------------------- Total 0.405ns (0.353ns logic, 0.052ns route) (87.2% logic, 12.8% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 28.430ns (period - min period limit) Period: 32.000ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) Physical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKB Logical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKB Location pin: RAMB16_X0Y28.CLKB Clock network: ipb_clk -------------------------------------------------------------------------------- Slack: 28.430ns (period - min period limit) Period: 32.000ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) Physical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram12/CLKB Logical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram12/CLKB Location pin: RAMB16_X0Y26.CLKB Clock network: ipb_clk -------------------------------------------------------------------------------- Slack: 28.430ns (period - min period limit) Period: 32.000ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) Physical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram21/CLKB Logical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram21/CLKB Location pin: RAMB16_X1Y28.CLKB Clock network: ipb_clk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclk4x_dcm = PERIOD TIMEGRP "TTCclk4x_dcm" TS_TTC_REFCLK / 4 PHASE -3.890625 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 169 paths analyzed, 104 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 6.211ns. -------------------------------------------------------------------------------- Paths for end point i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y16.DIA27), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.007ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[11].i_trig_data/buffer_dinB (FF) Destination: i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 3.113ns Data Path Delay: 2.434ns (Levels of Logic = 0) Clock Path Skew: -0.454ns (2.131 - 2.585) Source Clock: TTCclk8x rising at 5.447ns Destination Clock: TTCclk4x rising at 8.560ns Clock Uncertainty: 0.218ns Clock Uncertainty: 0.218ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.183ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[11].i_trig_data/buffer_dinB to i_buffer/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X22Y28.AMUX Tshcko 0.576 g_trig_Twinmux[11].i_trig_data/o_2 g_trig_Twinmux[11].i_trig_data/buffer_dinB RAMB16_X2Y16.DIA27 net (fanout=1) 1.558 buffer_di<27> RAMB16_X2Y16.CLKA Trdck_DIA 0.300 i_buffer/ramb_st.ramb18_dp_st.ram18_st i_buffer/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 2.434ns (0.876ns logic, 1.558ns route) (36.0% logic, 64.0% route) -------------------------------------------------------------------------------- Paths for end point i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y16.DIA26), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.019ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[10].i_trig_data/buffer_dinB (FF) Destination: i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 3.113ns Data Path Delay: 2.423ns (Levels of Logic = 0) Clock Path Skew: -0.453ns (2.131 - 2.584) Source Clock: TTCclk8x rising at 5.447ns Destination Clock: TTCclk4x rising at 8.560ns Clock Uncertainty: 0.218ns Clock Uncertainty: 0.218ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.183ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[10].i_trig_data/buffer_dinB to i_buffer/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y32.AQ Tcko 0.430 buffer_di<26> g_trig_Twinmux[10].i_trig_data/buffer_dinB RAMB16_X2Y16.DIA26 net (fanout=1) 1.693 buffer_di<26> RAMB16_X2Y16.CLKA Trdck_DIA 0.300 i_buffer/ramb_st.ramb18_dp_st.ram18_st i_buffer/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 2.423ns (0.730ns logic, 1.693ns route) (30.1% logic, 69.9% route) -------------------------------------------------------------------------------- Paths for end point i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y16.DIA28), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.072ns (requirement - (data path - clock path skew + uncertainty)) Source: i_TRIG0/buffer_dinB (FF) Destination: i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 3.113ns Data Path Delay: 2.381ns (Levels of Logic = 0) Clock Path Skew: -0.442ns (2.131 - 2.573) Source Clock: TTCclk8x rising at 5.447ns Destination Clock: TTCclk4x rising at 8.560ns Clock Uncertainty: 0.218ns Clock Uncertainty: 0.218ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.183ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: i_TRIG0/buffer_dinB to i_buffer/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X22Y40.CQ Tcko 0.525 buffer_di<28> i_TRIG0/buffer_dinB RAMB16_X2Y16.DIA28 net (fanout=1) 1.556 buffer_di<28> RAMB16_X2Y16.CLKA Trdck_DIA 0.300 i_buffer/ramb_st.ramb18_dp_st.ram18_st i_buffer/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 2.381ns (0.825ns logic, 1.556ns route) (34.6% logic, 65.4% route) -------------------------------------------------------------------------------- Hold Paths: TS_TTCclk4x_dcm = PERIOD TIMEGRP "TTCclk4x_dcm" TS_TTC_REFCLK / 4 PHASE -3.890625 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y16.DIA7), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.182ns (requirement - (clock path skew + uncertainty - data path)) Source: g_trig_Twinmux[7].i_trig_data/buffer_dinA (FF) Destination: i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 0.000ns Data Path Delay: 0.442ns (Levels of Logic = 0) Clock Path Skew: 0.042ns (0.971 - 0.929) Source Clock: TTCclk8x rising at 8.560ns Destination Clock: TTCclk4x rising at 8.560ns Clock Uncertainty: 0.218ns Clock Uncertainty: 0.218ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.183ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: g_trig_Twinmux[7].i_trig_data/buffer_dinA to i_buffer/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y29.DQ Tcko 0.234 buffer_di<7> g_trig_Twinmux[7].i_trig_data/buffer_dinA RAMB16_X2Y16.DIA7 net (fanout=1) 0.261 buffer_di<7> RAMB16_X2Y16.CLKA Trckd_DIA (-Th) 0.053 i_buffer/ramb_st.ramb18_dp_st.ram18_st i_buffer/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 0.442ns (0.181ns logic, 0.261ns route) (41.0% logic, 59.0% route) -------------------------------------------------------------------------------- Paths for end point i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y16.DIA2), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.206ns (requirement - (clock path skew + uncertainty - data path)) Source: g_trig_Twinmux[2].i_trig_data/buffer_dinA (FF) Destination: i_buffer/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 0.000ns Data Path Delay: 0.465ns (Levels of Logic = 0) Clock Path Skew: 0.041ns (0.971 - 0.930) Source Clock: TTCclk8x rising at 8.560ns Destination Clock: TTCclk4x rising at 8.560ns Clock Uncertainty: 0.218ns Clock Uncertainty: 0.218ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.183ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: g_trig_Twinmux[2].i_trig_data/buffer_dinA to i_buffer/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X41Y30.CQ Tcko 0.198 buffer_di<3> g_trig_Twinmux[2].i_trig_data/buffer_dinA RAMB16_X2Y16.DIA2 net (fanout=1) 0.320 buffer_di<2> RAMB16_X2Y16.CLKA Trckd_DIA (-Th) 0.053 i_buffer/ramb_st.ramb18_dp_st.ram18_st i_buffer/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 0.465ns (0.145ns logic, 0.320ns route) (31.2% logic, 68.8% route) -------------------------------------------------------------------------------- Paths for end point TTCclk_toggle_q (SLICE_X34Y43.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.226ns (requirement - (clock path skew + uncertainty - data path)) Source: TTCclk_toggle (FF) Destination: TTCclk_toggle_q (FF) Requirement: 0.000ns Data Path Delay: 0.513ns (Levels of Logic = 1) Clock Path Skew: 0.045ns (0.967 - 0.922) Source Clock: TTCclk rising at -3.890ns Destination Clock: TTCclk4x rising at -3.890ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: TTCclk_toggle to TTCclk_toggle_q Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y43.AQ Tcko 0.198 TTCclk_toggle TTCclk_toggle SLICE_X34Y43.A5 net (fanout=2) 0.184 TTCclk_toggle SLICE_X34Y43.CLK Tah (-Th) -0.131 TTCclkPhase<3> TTCclk_toggle_rt TTCclk_toggle_q ------------------------------------------------- --------------------------- Total 0.513ns (0.329ns logic, 0.184ns route) (64.1% logic, 35.9% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclk4x_dcm = PERIOD TIMEGRP "TTCclk4x_dcm" TS_TTC_REFCLK / 4 PHASE -3.890625 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 2.655ns (period - min period limit) Period: 6.225ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax)) Physical resource: i_buffer/ramb_st.ramb18_dp_st.ram18_st/CLKA Logical resource: i_buffer/ramb_st.ramb18_dp_st.ram18_st/CLKA Location pin: RAMB16_X2Y16.CLKA Clock network: TTCclk4x -------------------------------------------------------------------------------- Slack: 3.559ns (period - min period limit) Period: 6.225ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: i_TTCclk4x/I0 Logical resource: i_TTCclk4x/I0 Location pin: BUFGMUX_X2Y10.I0 Clock network: TTCclk4x_dcm -------------------------------------------------------------------------------- Slack: 5.745ns (period - (min high pulse limit / (high pulse / period))) Period: 6.225ns High pulse: 3.112ns High pulse limit: 0.240ns (Trpw) Physical resource: TTCclkPhase[3]_twinmux[0]_AND_483_o/SR Logical resource: buffer_we_3/SR Location pin: SLICE_X38Y40.SR Clock network: _n1438 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dcm" TS_TTC_REFCLK PHASE -3.890625 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 6120 paths analyzed, 2554 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 24.772ns. -------------------------------------------------------------------------------- Paths for end point i_twinmux/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y20.ADDRA8), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.016ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[9].i_trig_data/twinmux_ra (FF) Destination: i_twinmux/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 3.113ns Data Path Delay: 2.404ns (Levels of Logic = 0) Clock Path Skew: -0.451ns (2.122 - 2.573) Source Clock: TTCclk8x rising at 5.447ns Destination Clock: TTCclk falling at 8.560ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[9].i_trig_data/twinmux_ra to i_twinmux/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X27Y39.BQ Tcko 0.430 twinmux_ra<11> g_trig_Twinmux[9].i_trig_data/twinmux_ra RAMB16_X2Y20.ADDRA8 net (fanout=1) 1.574 twinmux_ra<9> RAMB16_X2Y20.CLKA Trcck_ADDRA 0.400 i_twinmux/ramb_st.ramb18_dp_st.ram18_st i_twinmux/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 2.404ns (0.830ns logic, 1.574ns route) (34.5% logic, 65.5% route) -------------------------------------------------------------------------------- Paths for end point i_twinmux/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y20.ADDRA4), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.047ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[5].i_trig_data/twinmux_ra (FF) Destination: i_twinmux/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 3.113ns Data Path Delay: 2.385ns (Levels of Logic = 0) Clock Path Skew: -0.439ns (2.122 - 2.561) Source Clock: TTCclk8x rising at 5.447ns Destination Clock: TTCclk falling at 8.560ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[5].i_trig_data/twinmux_ra to i_twinmux/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X40Y27.BQ Tcko 0.476 twinmux_ra<7> g_trig_Twinmux[5].i_trig_data/twinmux_ra RAMB16_X2Y20.ADDRA4 net (fanout=1) 1.509 twinmux_ra<5> RAMB16_X2Y20.CLKA Trcck_ADDRA 0.400 i_twinmux/ramb_st.ramb18_dp_st.ram18_st i_twinmux/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 2.385ns (0.876ns logic, 1.509ns route) (36.7% logic, 63.3% route) -------------------------------------------------------------------------------- Paths for end point i_twinmux/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X2Y20.ADDRA3), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.052ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[3].i_trig_data/twinmux_ra (FF) Destination: i_twinmux/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 3.113ns Data Path Delay: 2.374ns (Levels of Logic = 0) Clock Path Skew: -0.445ns (2.122 - 2.567) Source Clock: TTCclk8x rising at 5.447ns Destination Clock: TTCclk falling at 8.560ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[3].i_trig_data/twinmux_ra to i_twinmux/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X41Y31.DQ Tcko 0.430 twinmux_ra<3> g_trig_Twinmux[3].i_trig_data/twinmux_ra RAMB16_X2Y20.ADDRA3 net (fanout=1) 1.544 twinmux_ra<3> RAMB16_X2Y20.CLKA Trcck_ADDRA 0.400 i_twinmux/ramb_st.ramb18_dp_st.ram18_st i_twinmux/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 2.374ns (0.830ns logic, 1.544ns route) (35.0% logic, 65.0% route) -------------------------------------------------------------------------------- Hold Paths: TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dcm" TS_TTC_REFCLK PHASE -3.890625 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point TTCcmdCntr_5_3 (SLICE_X34Y24.CE), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.226ns (requirement - (clock path skew + uncertainty - data path)) Source: inc_TTCcmdCntr_5 (FF) Destination: TTCcmdCntr_5_3 (FF) Requirement: 0.000ns Data Path Delay: 0.225ns (Levels of Logic = 0) Clock Path Skew: -0.001ns (0.031 - 0.032) Source Clock: TTCclk rising at 21.010ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: inc_TTCcmdCntr_5 to TTCcmdCntr_5_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X35Y25.AQ Tcko 0.198 inc_TTCcmdCntr<8> inc_TTCcmdCntr_5 SLICE_X34Y24.CE net (fanout=5) 0.135 inc_TTCcmdCntr<5> SLICE_X34Y24.CLK Tckce (-Th) 0.108 TTCcmdCntr_5<3> TTCcmdCntr_5_3 ------------------------------------------------- --------------------------- Total 0.225ns (0.090ns logic, 0.135ns route) (40.0% logic, 60.0% route) -------------------------------------------------------------------------------- Paths for end point TTCcmdCntr_5_2 (SLICE_X34Y24.CE), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.230ns (requirement - (clock path skew + uncertainty - data path)) Source: inc_TTCcmdCntr_5 (FF) Destination: TTCcmdCntr_5_2 (FF) Requirement: 0.000ns Data Path Delay: 0.229ns (Levels of Logic = 0) Clock Path Skew: -0.001ns (0.031 - 0.032) Source Clock: TTCclk rising at 21.010ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: inc_TTCcmdCntr_5 to TTCcmdCntr_5_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X35Y25.AQ Tcko 0.198 inc_TTCcmdCntr<8> inc_TTCcmdCntr_5 SLICE_X34Y24.CE net (fanout=5) 0.135 inc_TTCcmdCntr<5> SLICE_X34Y24.CLK Tckce (-Th) 0.104 TTCcmdCntr_5<3> TTCcmdCntr_5_2 ------------------------------------------------- --------------------------- Total 0.229ns (0.094ns logic, 0.135ns route) (41.0% logic, 59.0% route) -------------------------------------------------------------------------------- Paths for end point TTCcmdCntr_5_1 (SLICE_X34Y24.CE), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.232ns (requirement - (clock path skew + uncertainty - data path)) Source: inc_TTCcmdCntr_5 (FF) Destination: TTCcmdCntr_5_1 (FF) Requirement: 0.000ns Data Path Delay: 0.231ns (Levels of Logic = 0) Clock Path Skew: -0.001ns (0.031 - 0.032) Source Clock: TTCclk rising at 21.010ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: inc_TTCcmdCntr_5 to TTCcmdCntr_5_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X35Y25.AQ Tcko 0.198 inc_TTCcmdCntr<8> inc_TTCcmdCntr_5 SLICE_X34Y24.CE net (fanout=5) 0.135 inc_TTCcmdCntr<5> SLICE_X34Y24.CLK Tckce (-Th) 0.102 TTCcmdCntr_5<3> TTCcmdCntr_5_1 ------------------------------------------------- --------------------------- Total 0.231ns (0.096ns logic, 0.135ns route) (41.6% logic, 58.4% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dcm" TS_TTC_REFCLK PHASE -3.890625 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 21.330ns (period - min period limit) Period: 24.900ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax)) Physical resource: i_TTC_history1/ramb_st.ramb18_sdp_st.ram18_st/CLKA Logical resource: i_TTC_history1/ramb_st.ramb18_sdp_st.ram18_st/CLKA Location pin: RAMB16_X3Y24.CLKA Clock network: TTCclk -------------------------------------------------------------------------------- Slack: 21.330ns (period - min period limit) Period: 24.900ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax)) Physical resource: i_TTC_history0/ramb_st.ramb18_sdp_st.ram18_st/CLKA Logical resource: i_TTC_history0/ramb_st.ramb18_sdp_st.ram18_st/CLKA Location pin: RAMB16_X3Y26.CLKA Clock network: TTCclk -------------------------------------------------------------------------------- Slack: 21.330ns (period - min period limit) Period: 24.900ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax)) Physical resource: i_twinmux/ramb_st.ramb18_dp_st.ram18_st/CLKA Logical resource: i_twinmux/ramb_st.ramb18_dp_st.ram18_st/CLKA Location pin: RAMB16_X2Y20.CLKA Clock network: TTCclk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclk8x_dcm = PERIOD TIMEGRP "TTCclk8x_dcm" TS_TTC_REFCLK / 8 PHASE -0.778125 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 287 paths analyzed, 287 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 2.784ns. -------------------------------------------------------------------------------- Paths for end point g_trig_Twinmux[3].i_trig_data/o_2 (SLICE_X38Y13.AX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.328ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[3].i_trig_data/i_delay_buffer (FF) Destination: g_trig_Twinmux[3].i_trig_data/o_2 (FF) Requirement: 3.112ns Data Path Delay: 2.694ns (Levels of Logic = 0) Clock Path Skew: -0.001ns (0.623 - 0.624) Source Clock: TTCclk8x rising at -0.778ns Destination Clock: TTCclk8x rising at 2.334ns Clock Uncertainty: 0.089ns Clock Uncertainty: 0.089ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.162ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[3].i_trig_data/i_delay_buffer to g_trig_Twinmux[3].i_trig_data/o_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y20.B Treg 1.549 buffer_di<21> g_trig_Twinmux[3].i_trig_data/i_delay_buffer SLICE_X38Y13.AX net (fanout=1) 1.060 g_trig_Twinmux[3].i_trig_data/o<1> SLICE_X38Y13.CLK Tdick 0.085 g_trig_Twinmux[3].i_trig_data/o_0 g_trig_Twinmux[3].i_trig_data/o_2 ------------------------------------------------- --------------------------- Total 2.694ns (1.634ns logic, 1.060ns route) (60.7% logic, 39.3% route) -------------------------------------------------------------------------------- Paths for end point g_trig_Twinmux[0].i_trig_data/i_delay0 (SLICE_X52Y22.BX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.356ns (requirement - (data path - clock path skew + uncertainty)) Source: g_trig_Twinmux[0].i_trig_data/d_0 (FF) Destination: g_trig_Twinmux[0].i_trig_data/i_delay0 (FF) Requirement: 3.112ns Data Path Delay: 2.597ns (Levels of Logic = 0) Clock Path Skew: -0.070ns (0.583 - 0.653) Source Clock: TTCclk8x rising at -0.778ns Destination Clock: TTCclk8x rising at 2.334ns Clock Uncertainty: 0.089ns Clock Uncertainty: 0.089ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.162ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: g_trig_Twinmux[0].i_trig_data/d_0 to g_trig_Twinmux[0].i_trig_data/i_delay0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X56Y2.AQ Tcko 0.525 g_trig_Twinmux[0].i_trig_data/d<0> g_trig_Twinmux[0].i_trig_data/d_0 SLICE_X52Y22.BX net (fanout=1) 2.152 g_trig_Twinmux[0].i_trig_data/d<0> SLICE_X52Y22.CLK Tds -0.080 g_trig_Twinmux[0].i_trig_data/d<1> g_trig_Twinmux[0].i_trig_data/i_delay0 ------------------------------------------------- --------------------------- Total 2.597ns (0.445ns logic, 2.152ns route) (17.1% logic, 82.9% route) -------------------------------------------------------------------------------- Paths for end point i_TRIG0/i_delay0 (SLICE_X14Y54.BX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.359ns (requirement - (data path - clock path skew + uncertainty)) Source: i_TRIG0/d_0 (FF) Destination: i_TRIG0/i_delay0 (FF) Requirement: 3.112ns Data Path Delay: 2.620ns (Levels of Logic = 0) Clock Path Skew: -0.044ns (0.720 - 0.764) Source Clock: TTCclk8x rising at -0.778ns Destination Clock: TTCclk8x rising at 2.334ns Clock Uncertainty: 0.089ns Clock Uncertainty: 0.089ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.162ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_TRIG0/d_0 to i_TRIG0/i_delay0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y68.AQ Tcko 0.525 i_TRIG0/d<0> i_TRIG0/d_0 SLICE_X14Y54.BX net (fanout=1) 2.175 i_TRIG0/d<0> SLICE_X14Y54.CLK Tds -0.080 i_TRIG0/d<1> i_TRIG0/i_delay0 ------------------------------------------------- --------------------------- Total 2.620ns (0.445ns logic, 2.175ns route) (17.0% logic, 83.0% route) -------------------------------------------------------------------------------- Hold Paths: TS_TTCclk8x_dcm = PERIOD TIMEGRP "TTCclk8x_dcm" TS_TTC_REFCLK / 8 PHASE -0.778125 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point g_trig_Twinmux[11].i_trig_data/g_delay[6].i_delay (SLICE_X14Y21.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.303ns (requirement - (clock path skew + uncertainty - data path)) Source: g_trig_Twinmux[11].i_trig_data/d_6 (FF) Destination: g_trig_Twinmux[11].i_trig_data/g_delay[6].i_delay (FF) Requirement: 0.000ns Data Path Delay: 0.303ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: TTCclk8x rising at -0.778ns Destination Clock: TTCclk8x rising at -0.778ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: g_trig_Twinmux[11].i_trig_data/d_6 to g_trig_Twinmux[11].i_trig_data/g_delay[6].i_delay Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y21.CQ Tcko 0.234 g_trig_Twinmux[11].i_trig_data/d<7> g_trig_Twinmux[11].i_trig_data/d_6 SLICE_X14Y21.DX net (fanout=2) 0.169 g_trig_Twinmux[11].i_trig_data/d<6> SLICE_X14Y21.CLK Tdh (-Th) 0.100 g_trig_Twinmux[11].i_trig_data/d<7> g_trig_Twinmux[11].i_trig_data/g_delay[6].i_delay ------------------------------------------------- --------------------------- Total 0.303ns (0.134ns logic, 0.169ns route) (44.2% logic, 55.8% route) -------------------------------------------------------------------------------- Paths for end point i_TRIG1/g_delay[6].i_delay (SLICE_X14Y45.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.303ns (requirement - (clock path skew + uncertainty - data path)) Source: i_TRIG1/d_6 (FF) Destination: i_TRIG1/g_delay[6].i_delay (FF) Requirement: 0.000ns Data Path Delay: 0.303ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: TTCclk8x rising at -0.778ns Destination Clock: TTCclk8x rising at -0.778ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_TRIG1/d_6 to i_TRIG1/g_delay[6].i_delay Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y45.CQ Tcko 0.234 i_TRIG1/d<7> i_TRIG1/d_6 SLICE_X14Y45.DX net (fanout=2) 0.169 i_TRIG1/d<6> SLICE_X14Y45.CLK Tdh (-Th) 0.100 i_TRIG1/d<7> i_TRIG1/g_delay[6].i_delay ------------------------------------------------- --------------------------- Total 0.303ns (0.134ns logic, 0.169ns route) (44.2% logic, 55.8% route) -------------------------------------------------------------------------------- Paths for end point i_TRIG0/g_delay[6].i_delay (SLICE_X18Y46.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.303ns (requirement - (clock path skew + uncertainty - data path)) Source: i_TRIG0/d_6 (FF) Destination: i_TRIG0/g_delay[6].i_delay (FF) Requirement: 0.000ns Data Path Delay: 0.303ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: TTCclk8x rising at -0.778ns Destination Clock: TTCclk8x rising at -0.778ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_TRIG0/d_6 to i_TRIG0/g_delay[6].i_delay Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y46.CQ Tcko 0.234 i_TRIG0/d<7> i_TRIG0/d_6 SLICE_X18Y46.DX net (fanout=2) 0.169 i_TRIG0/d<6> SLICE_X18Y46.CLK Tdh (-Th) 0.100 i_TRIG0/d<7> i_TRIG0/g_delay[6].i_delay ------------------------------------------------- --------------------------- Total 0.303ns (0.134ns logic, 0.169ns route) (44.2% logic, 55.8% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclk8x_dcm = PERIOD TIMEGRP "TTCclk8x_dcm" TS_TTC_REFCLK / 8 PHASE -0.778125 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 0.446ns (period - min period limit) Period: 3.112ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: i_TTCclk8x/I0 Logical resource: i_TTCclk8x/I0 Location pin: BUFGMUX_X2Y12.I0 Clock network: TTCclk8x_dcm -------------------------------------------------------------------------------- Slack: 1.713ns (period - min period limit) Period: 3.112ns Min period limit: 1.399ns (714.796MHz) (Tcp) Physical resource: g_trig_Twinmux[10].i_trig_data/d<2>/CLK Logical resource: g_trig_Twinmux[10].i_trig_data/g_delay[1].i_delay/CLK Location pin: SLICE_X6Y28.CLK Clock network: TTCclk8x -------------------------------------------------------------------------------- Slack: 1.713ns (period - min period limit) Period: 3.112ns Min period limit: 1.399ns (714.796MHz) (Tcp) Physical resource: g_trig_Twinmux[10].i_trig_data/d<7>/CLK Logical resource: g_trig_Twinmux[10].i_trig_data/g_delay[3].i_delay/CLK Location pin: SLICE_X6Y30.CLK Clock network: TTCclk8x -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclkOut_dcm_0_ = PERIOD TIMEGRP "TTCclkOut_dcm_0_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 2.666ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclkOut_dcm_0_ = PERIOD TIMEGRP "TTCclkOut_dcm_0_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 22.234ns (period - min period limit) Period: 24.900ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: g_TTCclkOut[0].i_TTCclk_buf/I0 Logical resource: g_TTCclkOut[0].i_TTCclk_buf/I0 Location pin: BUFGMUX_X2Y1.I0 Clock network: TTCclkOut_dcm<0> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<1>/CLK0 Logical resource: g_TxFB[0].i_TxFB/CK0 Location pin: OLOGIC_X20Y3.CLK0 Clock network: TTCclkOut<0> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<2>/CLK0 Logical resource: g_TxFB[1].i_TxFB/CK0 Location pin: OLOGIC_X19Y1.CLK0 Clock network: TTCclkOut<0> -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclkOut_dcm_1_ = PERIOD TIMEGRP "TTCclkOut_dcm_1_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 2.666ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclkOut_dcm_1_ = PERIOD TIMEGRP "TTCclkOut_dcm_1_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 22.234ns (period - min period limit) Period: 24.900ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: g_TTCclkOut[1].i_TTCclk_buf/I0 Logical resource: g_TTCclkOut[1].i_TTCclk_buf/I0 Location pin: BUFGMUX_X2Y4.I0 Clock network: TTCclkOut_dcm<1> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<4>/CLK0 Logical resource: g_TxFB[3].i_TxFB/CK0 Location pin: OLOGIC_X16Y3.CLK0 Clock network: TTCclkOut<1> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<5>/CLK0 Logical resource: g_TxFB[4].i_TxFB/CK0 Location pin: OLOGIC_X14Y3.CLK0 Clock network: TTCclkOut<1> -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclkOut_dcm_2_ = PERIOD TIMEGRP "TTCclkOut_dcm_2_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 2.666ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclkOut_dcm_2_ = PERIOD TIMEGRP "TTCclkOut_dcm_2_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 22.234ns (period - min period limit) Period: 24.900ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: g_TTCclkOut[2].i_TTCclk_buf/I0 Logical resource: g_TTCclkOut[2].i_TTCclk_buf/I0 Location pin: BUFGMUX_X2Y2.I0 Clock network: TTCclkOut_dcm<2> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<7>/CLK0 Logical resource: g_TxFB[6].i_TxFB/CK0 Location pin: OLOGIC_X13Y3.CLK0 Clock network: TTCclkOut<2> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<8>/CLK0 Logical resource: g_TxFB[7].i_TxFB/CK0 Location pin: OLOGIC_X12Y3.CLK0 Clock network: TTCclkOut<2> -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclkOut_dcm_3_ = PERIOD TIMEGRP "TTCclkOut_dcm_3_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 2.666ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclkOut_dcm_3_ = PERIOD TIMEGRP "TTCclkOut_dcm_3_" TS_TTCclk_p PHASE 3.40429688 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 22.234ns (period - min period limit) Period: 24.900ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: g_TTCclkOut[3].i_TTCclk_buf/I0 Logical resource: g_TTCclkOut[3].i_TTCclk_buf/I0 Location pin: BUFGMUX_X3Y13.I0 Clock network: TTCclkOut_dcm<3> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<10>/CLK0 Logical resource: g_TxFB[9].i_TxFB/CK0 Location pin: OLOGIC_X8Y1.CLK0 Clock network: TTCclkOut<3> -------------------------------------------------------------------------------- Slack: 22.651ns (period - min period limit) Period: 24.900ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: TxFB<11>/CLK0 Logical resource: g_TxFB[10].i_TxFB/CK0 Location pin: OLOGIC_X7Y1.CLK0 Clock network: TTCclkOut<3> -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP "TO_TTC_data_1_LD" TS_TTCclk_dcm DATAPATHONLY; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 18.004ns. -------------------------------------------------------------------------------- Paths for end point TTC_data_1_LD (SLICE_X25Y68.CLK), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 6.896ns (requirement - data path) Source: V6_DONE (PAD) Destination: TTC_data_1_LD (LATCH) Requirement: 24.900ns Data Path Delay: 18.004ns (Levels of Logic = 4) Maximum Data Path at Slow Process Corner: V6_DONE to TTC_data_1_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C19.I Tiopi 1.070 V6_DONE V6_DONE V6_DONE_IBUF ProtoComp417.IINV ProtoComp417.IMUX SLICE_X15Y71.A5 net (fanout=7) 8.811 V6_DONE_inv SLICE_X15Y71.AMUX Tilo 0.337 i_ipbus/my_ip_addr_udp<3> rst_TTC1 PLL_ADV_X0Y2.RST net (fanout=5) 3.063 rst_TTC PLL_ADV_X0Y2.LOCKED Tplldo_LOCKED 1.300 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV SLICE_X25Y82.A4 net (fanout=1) 1.326 TTC_lock SLICE_X25Y82.A Tilo 0.259 i_ipbus/udp_if/tx_transactor/pkt_id_buf_10<11> TTC_lock_inv1_INV_0 SLICE_X25Y68.CLK net (fanout=3) 1.838 TTC_lock_inv ------------------------------------------------- --------------------------- Total 18.004ns (2.966ns logic, 15.038ns route) (16.5% logic, 83.5% route) -------------------------------------------------------------------------------- Slack (slowest paths): 14.894ns (requirement - data path) Source: i_rst_TTC (FF) Destination: TTC_data_1_LD (LATCH) Requirement: 24.900ns Data Path Delay: 10.006ns (Levels of Logic = 3) Source Clock: TTC_REFCLK_in rising at 0.000ns Maximum Data Path at Slow Process Corner: i_rst_TTC to TTC_data_1_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y71.A Treg 1.459 rst_TTC1 i_rst_TTC SLICE_X15Y71.A4 net (fanout=1) 0.424 rst_TTC1 SLICE_X15Y71.AMUX Tilo 0.337 i_ipbus/my_ip_addr_udp<3> rst_TTC1 PLL_ADV_X0Y2.RST net (fanout=5) 3.063 rst_TTC PLL_ADV_X0Y2.LOCKED Tplldo_LOCKED 1.300 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV SLICE_X25Y82.A4 net (fanout=1) 1.326 TTC_lock SLICE_X25Y82.A Tilo 0.259 i_ipbus/udp_if/tx_transactor/pkt_id_buf_10<11> TTC_lock_inv1_INV_0 SLICE_X25Y68.CLK net (fanout=3) 1.838 TTC_lock_inv ------------------------------------------------- --------------------------- Total 10.006ns (3.355ns logic, 6.651ns route) (33.5% logic, 66.5% route) -------------------------------------------------------------------------------- Hold Paths: TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP "TO_TTC_data_1_LD" TS_TTCclk_dcm DATAPATHONLY; -------------------------------------------------------------------------------- Paths for end point TTC_data_1_LD (SLICE_X25Y68.CLK), 2 paths -------------------------------------------------------------------------------- Delay (fastest path): 5.009ns (data path) Source: i_rst_TTC (FF) Destination: TTC_data_1_LD (LATCH) Data Path Delay: 5.009ns (Levels of Logic = 3) Source Clock: TTC_REFCLK_in rising at 0.000ns Minimum Data Path at Fast Process Corner: i_rst_TTC to TTC_data_1_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y71.A Treg 0.539 rst_TTC1 i_rst_TTC SLICE_X15Y71.A4 net (fanout=1) 0.162 rst_TTC1 SLICE_X15Y71.AMUX Tilo 0.203 i_ipbus/my_ip_addr_udp<3> rst_TTC1 PLL_ADV_X0Y2.RST net (fanout=5) 1.807 rst_TTC PLL_ADV_X0Y2.LOCKED Tplldo_LOCKED 0.541 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV SLICE_X25Y82.A4 net (fanout=1) 0.667 TTC_lock SLICE_X25Y82.A Tilo 0.156 i_ipbus/udp_if/tx_transactor/pkt_id_buf_10<11> TTC_lock_inv1_INV_0 SLICE_X25Y68.CLK net (fanout=3) 0.934 TTC_lock_inv ------------------------------------------------- --------------------------- Total 5.009ns (1.439ns logic, 3.570ns route) (28.7% logic, 71.3% route) -------------------------------------------------------------------------------- Delay (fastest path): 9.588ns (data path) Source: V6_DONE (PAD) Destination: TTC_data_1_LD (LATCH) Data Path Delay: 9.588ns (Levels of Logic = 4) Minimum Data Path at Fast Process Corner: V6_DONE to TTC_data_1_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C19.I Tiopi 0.331 V6_DONE V6_DONE V6_DONE_IBUF ProtoComp417.IINV ProtoComp417.IMUX SLICE_X15Y71.A5 net (fanout=7) 4.949 V6_DONE_inv SLICE_X15Y71.AMUX Tilo 0.203 i_ipbus/my_ip_addr_udp<3> rst_TTC1 PLL_ADV_X0Y2.RST net (fanout=5) 1.807 rst_TTC PLL_ADV_X0Y2.LOCKED Tplldo_LOCKED 0.541 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV SLICE_X25Y82.A4 net (fanout=1) 0.667 TTC_lock SLICE_X25Y82.A Tilo 0.156 i_ipbus/udp_if/tx_transactor/pkt_id_buf_10<11> TTC_lock_inv1_INV_0 SLICE_X25Y68.CLK net (fanout=3) 0.934 TTC_lock_inv ------------------------------------------------- --------------------------- Total 9.588ns (1.231ns logic, 8.357ns route) (12.8% logic, 87.2% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TO_CRC_0_LD = MAXDELAY TO TIMEGRP "TO_CRC_0_LD" TS_ipb_clk DATAPATHONLY; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 3.122ns. -------------------------------------------------------------------------------- Paths for end point CRC_0_LD (SLICE_X33Y49.CLK), 1 path -------------------------------------------------------------------------------- Slack (slowest paths): 28.878ns (requirement - data path) Source: reprogV6 (FF) Destination: CRC_0_LD (LATCH) Requirement: 32.000ns Data Path Delay: 3.122ns (Levels of Logic = 1) Source Clock: ipb_clk rising at 0.000ns Maximum Data Path at Slow Process Corner: reprogV6 to CRC_0_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X31Y55.BMUX Tshcko 0.518 V6_PROG_B_OBUF reprogV6 SLICE_X31Y57.D2 net (fanout=5) 1.018 reprogV6 SLICE_X31Y57.D Tilo 0.259 sysclk_dcm_locked_reprogV6_OR_106_o sysclk_dcm_locked_reprogV6_OR_106_o1 SLICE_X33Y49.CLK net (fanout=33) 1.327 sysclk_dcm_locked_reprogV6_OR_106_o ------------------------------------------------- --------------------------- Total 3.122ns (0.777ns logic, 2.345ns route) (24.9% logic, 75.1% route) -------------------------------------------------------------------------------- Hold Paths: TS_TO_CRC_0_LD = MAXDELAY TO TIMEGRP "TO_CRC_0_LD" TS_ipb_clk DATAPATHONLY; -------------------------------------------------------------------------------- Paths for end point CRC_0_LD (SLICE_X33Y49.CLK), 1 path -------------------------------------------------------------------------------- Delay (fastest path): 1.658ns (data path) Source: reprogV6 (FF) Destination: CRC_0_LD (LATCH) Data Path Delay: 1.658ns (Levels of Logic = 1) Source Clock: ipb_clk rising at 0.000ns Minimum Data Path at Fast Process Corner: reprogV6 to CRC_0_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X31Y55.BMUX Tshcko 0.244 V6_PROG_B_OBUF reprogV6 SLICE_X31Y57.D2 net (fanout=5) 0.563 reprogV6 SLICE_X31Y57.D Tilo 0.156 sysclk_dcm_locked_reprogV6_OR_106_o sysclk_dcm_locked_reprogV6_OR_106_o1 SLICE_X33Y49.CLK net (fanout=33) 0.695 sysclk_dcm_locked_reprogV6_OR_106_o ------------------------------------------------- --------------------------- Total 1.658ns (0.400ns logic, 1.258ns route) (24.1% logic, 75.9% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "RISING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 7.333ns. -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.667ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk rising at -3.890ns Requirement: 10.000ns Data Path Delay: 3.134ns (Levels of Logic = 2) Clock Path Delay: -0.014ns (Levels of Logic = 4) Clock Uncertainty: 0.295ns Clock Uncertainty: 0.295ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.175ns Maximum Data Path at Slow Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 1.387 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp395.IMUX.3 ILOGIC_X0Y117.D net (fanout=1) 0.399 TTCdata_in ILOGIC_X0Y117.CLK0 Tidock 1.348 TTCdata<1> ProtoComp421.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 3.134ns (2.735ns logic, 0.399ns route) (87.3% logic, 12.7% route) Minimum Clock Path at Slow Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 1.344 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp407.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.373 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 PLL_ADV_X0Y2.CLKIN2 net (fanout=1) 0.762 i_DCM_TTCclk/PLL_ADV_ML_NEW_DIVCLK PLL_ADV_X0Y2.CLKOUT0 Tpllcko_CLK -5.398 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV BUFGMUX_X3Y6.I0 net (fanout=1) 0.560 TTCclk_dcm BUFGMUX_X3Y6.O Tgi0o 0.197 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK0 net (fanout=191) 1.969 TTCclk ------------------------------------------------- --------------------------- Total -0.014ns (-3.678ns logic, 3.664ns route) -------------------------------------------------------------------------------- Hold Paths: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "RISING"; -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.915ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk rising at -3.890ns Requirement: -3.000ns Data Path Delay: 1.300ns (Levels of Logic = 2) Clock Path Delay: -0.020ns (Levels of Logic = 4) Clock Uncertainty: 0.295ns Clock Uncertainty: 0.295ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.175ns Minimum Data Path at Fast Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 0.618 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp395.IMUX.3 ILOGIC_X0Y117.D net (fanout=1) 0.181 TTCdata_in ILOGIC_X0Y117.CLK0 Tiockd (-Th) -0.501 TTCdata<1> ProtoComp421.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 1.300ns (1.119ns logic, 0.181ns route) (86.1% logic, 13.9% route) Maximum Clock Path at Fast Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 0.887 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp407.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.235 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 PLL_ADV_X0Y2.CLKIN2 net (fanout=1) 0.325 i_DCM_TTCclk/PLL_ADV_ML_NEW_DIVCLK PLL_ADV_X0Y2.CLKOUT0 Tpllcko_CLK -2.866 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV BUFGMUX_X3Y6.I0 net (fanout=1) 0.212 TTCclk_dcm BUFGMUX_X3Y6.O Tgi0o 0.063 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK0 net (fanout=191) 0.994 TTCclk ------------------------------------------------- --------------------------- Total -0.020ns (-1.786ns logic, 1.766ns route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "FALLING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 7.393ns. -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.607ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk falling at -3.890ns Requirement: 10.000ns Data Path Delay: 3.134ns (Levels of Logic = 2) Clock Path Delay: -0.074ns (Levels of Logic = 4) Clock Uncertainty: 0.295ns Clock Uncertainty: 0.295ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.175ns Maximum Data Path at Slow Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 1.387 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp395.IMUX.3 ILOGIC_X0Y117.D net (fanout=1) 0.399 TTCdata_in ILOGIC_X0Y117.CLK1 Tidock 1.348 TTCdata<1> ProtoComp421.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 3.134ns (2.735ns logic, 0.399ns route) (87.3% logic, 12.7% route) Minimum Clock Path at Slow Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 1.344 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp407.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.373 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 PLL_ADV_X0Y2.CLKIN2 net (fanout=1) 0.762 i_DCM_TTCclk/PLL_ADV_ML_NEW_DIVCLK PLL_ADV_X0Y2.CLKOUT0 Tpllcko_CLK -5.398 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV BUFGMUX_X3Y6.I0 net (fanout=1) 0.560 TTCclk_dcm BUFGMUX_X3Y6.O Tgi0o 0.197 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK1 net (fanout=191) 1.909 TTCclk ------------------------------------------------- --------------------------- Total -0.074ns (-3.678ns logic, 3.604ns route) -------------------------------------------------------------------------------- Hold Paths: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "FALLING"; -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.990ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk falling at -3.890ns Requirement: -3.000ns Data Path Delay: 1.300ns (Levels of Logic = 2) Clock Path Delay: -0.095ns (Levels of Logic = 4) Clock Uncertainty: 0.295ns Clock Uncertainty: 0.295ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.233ns Phase Error (PE): 0.175ns Minimum Data Path at Fast Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 0.618 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp395.IMUX.3 ILOGIC_X0Y117.D net (fanout=1) 0.181 TTCdata_in ILOGIC_X0Y117.CLK1 Tiockd (-Th) -0.501 TTCdata<1> ProtoComp421.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 1.300ns (1.119ns logic, 0.181ns route) (86.1% logic, 13.9% route) Maximum Clock Path at Fast Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 0.887 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp407.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.235 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_4 PLL_ADV_X0Y2.CLKIN2 net (fanout=1) 0.325 i_DCM_TTCclk/PLL_ADV_ML_NEW_DIVCLK PLL_ADV_X0Y2.CLKOUT0 Tpllcko_CLK -2.866 i_DCM_TTCclk/PLL_ADV i_DCM_TTCclk/PLL_ADV BUFGMUX_X3Y6.I0 net (fanout=1) 0.212 TTCclk_dcm BUFGMUX_X3Y6.O Tgi0o 0.063 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK1 net (fanout=191) 0.919 TTCclk ------------------------------------------------- --------------------------- Total -0.095ns (-1.786ns logic, 1.691ns route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<0>" "RISING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 7.078ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<3> (AB16.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.122ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[2].i_TxFB (FF) Destination: TxFB_n<3> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.133ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[2].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X17Y3.CLK0 net (fanout=7) 2.382 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.133ns (-5.305ns logic, 5.172ns route) Maximum Data Path at Slow Process Corner: g_TxFB[2].i_TxFB to TxFB_n<3> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X17Y3.OQ Tockq 1.158 TxFB<3> g_TxFB[2].i_TxFB AA16.O net (fanout=1) 0.438 TxFB<3> AA16.DIFFO_OUT Tiood 1.909 TxFB_p<3> g_FB[3].i_TxFB/OBUFTDS AB16.DIFFO_IN net (fanout=1) 0.000 g_FB[3].i_TxFB/SLAVEBUF.DIFFOUT AB16.PAD Tiodop 0.027 TxFB_n<3> ProtoComp397.DIFFO_INUSED.6 TxFB_n<3> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.540ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[2].i_TxFB_T (FF) Destination: TxFB_n<3> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.133ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[2].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X17Y3.CLK0 net (fanout=7) 2.382 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.133ns (-5.305ns logic, 5.172ns route) Maximum Data Path at Slow Process Corner: g_TxFB[2].i_TxFB_T to TxFB_n<3> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X17Y3.TQ Tockq 0.740 TxFB<3> g_TxFB[2].i_TxFB_T AA16.T net (fanout=1) 0.438 TxFB_T<3> AA16.DIFFO_OUT Tiotd 1.909 TxFB_p<3> g_FB[3].i_TxFB/OBUFTDS AB16.DIFFO_IN net (fanout=1) 0.000 g_FB[3].i_TxFB/SLAVEBUF.DIFFOUT AB16.PAD Tiodop 0.027 TxFB_n<3> ProtoComp397.DIFFO_INUSED.6 TxFB_n<3> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<1> (AB18.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.124ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[0].i_TxFB (FF) Destination: TxFB_n<1> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.135ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK0 net (fanout=7) 2.380 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.135ns (-5.305ns logic, 5.170ns route) Maximum Data Path at Slow Process Corner: g_TxFB[0].i_TxFB to TxFB_n<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.OQ Tockq 1.158 TxFB<1> g_TxFB[0].i_TxFB AA18.O net (fanout=1) 0.438 TxFB<1> AA18.DIFFO_OUT Tiood 1.909 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS AB18.DIFFO_IN net (fanout=1) 0.000 g_FB[1].i_TxFB/SLAVEBUF.DIFFOUT AB18.PAD Tiodop 0.027 TxFB_n<1> ProtoComp397.DIFFO_INUSED.4 TxFB_n<1> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.542ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[0].i_TxFB_T (FF) Destination: TxFB_n<1> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.135ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK0 net (fanout=7) 2.380 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.135ns (-5.305ns logic, 5.170ns route) Maximum Data Path at Slow Process Corner: g_TxFB[0].i_TxFB_T to TxFB_n<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.TQ Tockq 0.740 TxFB<1> g_TxFB[0].i_TxFB_T AA18.T net (fanout=1) 0.438 TxFB_T<1> AA18.DIFFO_OUT Tiotd 1.909 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS AB18.DIFFO_IN net (fanout=1) 0.000 g_FB[1].i_TxFB/SLAVEBUF.DIFFOUT AB18.PAD Tiodop 0.027 TxFB_n<1> ProtoComp397.DIFFO_INUSED.4 TxFB_n<1> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<2> (AB17.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.174ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[1].i_TxFB (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.134ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK0 net (fanout=7) 2.381 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.134ns (-5.305ns logic, 5.171ns route) Maximum Data Path at Slow Process Corner: g_TxFB[1].i_TxFB to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.OQ Tockq 1.158 TxFB<2> g_TxFB[1].i_TxFB Y17.O net (fanout=1) 0.387 TxFB<2> Y17.DIFFO_OUT Tiood 1.909 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.027 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.592ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[1].i_TxFB_T (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.134ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK0 net (fanout=7) 2.381 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.134ns (-5.305ns logic, 5.171ns route) Maximum Data Path at Slow Process Corner: g_TxFB[1].i_TxFB_T to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.TQ Tockq 0.740 TxFB<2> g_TxFB[1].i_TxFB_T Y17.T net (fanout=1) 0.387 TxFB_T<2> Y17.DIFFO_OUT Tiotd 1.909 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.027 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<0>" "RISING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<2> (Y17.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.580ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB (FF) Destination: TxFB_p<2> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Data Path Delay: 1.292ns (Levels of Logic = 1) Clock Path Delay: 0.159ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK0 net (fanout=7) 0.933 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.159ns (-1.644ns logic, 1.803ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB to TxFB_p<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.OQ Tockq 0.419 TxFB<2> g_TxFB[1].i_TxFB Y17.O net (fanout=1) 0.268 TxFB<2> Y17.PAD Tioop 0.605 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS TxFB_p<2> ------------------------------------------------- --------------------------- Total 1.292ns (1.024ns logic, 0.268ns route) (79.3% logic, 20.7% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.406ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB_T (FF) Destination: TxFB_p<2> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Data Path Delay: 1.118ns (Levels of Logic = 1) Clock Path Delay: 0.159ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK0 net (fanout=7) 0.933 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.159ns (-1.644ns logic, 1.803ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB_T to TxFB_p<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.TQ Tockq 0.245 TxFB<2> g_TxFB[1].i_TxFB_T Y17.T net (fanout=1) 0.268 TxFB_T<2> Y17.PAD Tiotp 0.605 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS TxFB_p<2> ------------------------------------------------- --------------------------- Total 1.118ns (0.850ns logic, 0.268ns route) (76.0% logic, 24.0% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<2> (AB17.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.596ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Data Path Delay: 1.308ns (Levels of Logic = 2) Clock Path Delay: 0.159ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK0 net (fanout=7) 0.933 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.159ns (-1.644ns logic, 1.803ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.OQ Tockq 0.419 TxFB<2> g_TxFB[1].i_TxFB Y17.O net (fanout=1) 0.268 TxFB<2> Y17.DIFFO_OUT Tiood 0.613 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.008 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 1.308ns (1.040ns logic, 0.268ns route) (79.5% logic, 20.5% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.422ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB_T (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Data Path Delay: 1.134ns (Levels of Logic = 2) Clock Path Delay: 0.159ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK0 net (fanout=7) 0.933 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.159ns (-1.644ns logic, 1.803ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB_T to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.TQ Tockq 0.245 TxFB<2> g_TxFB[1].i_TxFB_T Y17.T net (fanout=1) 0.268 TxFB_T<2> Y17.DIFFO_OUT Tiotd 0.613 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.008 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 1.134ns (0.866ns logic, 0.268ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<1> (AA18.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.630ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[0].i_TxFB (FF) Destination: TxFB_p<1> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Data Path Delay: 1.343ns (Levels of Logic = 1) Clock Path Delay: 0.158ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK0 net (fanout=7) 0.932 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.158ns (-1.644ns logic, 1.802ns route) Minimum Data Path at Fast Process Corner: g_TxFB[0].i_TxFB to TxFB_p<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.OQ Tockq 0.419 TxFB<1> g_TxFB[0].i_TxFB AA18.O net (fanout=1) 0.319 TxFB<1> AA18.PAD Tioop 0.605 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS TxFB_p<1> ------------------------------------------------- --------------------------- Total 1.343ns (1.024ns logic, 0.319ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.456ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[0].i_TxFB_T (FF) Destination: TxFB_p<1> (PAD) Source Clock: TTCclkOut<0> rising at 3.404ns Data Path Delay: 1.169ns (Levels of Logic = 1) Clock Path Delay: 0.158ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK0 net (fanout=7) 0.932 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.158ns (-1.644ns logic, 1.802ns route) Minimum Data Path at Fast Process Corner: g_TxFB[0].i_TxFB_T to TxFB_p<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.TQ Tockq 0.245 TxFB<1> g_TxFB[0].i_TxFB_T AA18.T net (fanout=1) 0.319 TxFB_T<1> AA18.PAD Tiotp 0.605 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS TxFB_p<1> ------------------------------------------------- --------------------------- Total 1.169ns (0.850ns logic, 0.319ns route) (72.7% logic, 27.3% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<0>" "FALLING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 7.016ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<3> (AB16.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.184ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[2].i_TxFB (FF) Destination: TxFB_n<3> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.195ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[2].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X17Y3.CLK1 net (fanout=7) 2.320 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.195ns (-5.305ns logic, 5.110ns route) Maximum Data Path at Slow Process Corner: g_TxFB[2].i_TxFB to TxFB_n<3> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X17Y3.OQ Tockq 1.158 TxFB<3> g_TxFB[2].i_TxFB AA16.O net (fanout=1) 0.438 TxFB<3> AA16.DIFFO_OUT Tiood 1.909 TxFB_p<3> g_FB[3].i_TxFB/OBUFTDS AB16.DIFFO_IN net (fanout=1) 0.000 g_FB[3].i_TxFB/SLAVEBUF.DIFFOUT AB16.PAD Tiodop 0.027 TxFB_n<3> ProtoComp397.DIFFO_INUSED.6 TxFB_n<3> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.602ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[2].i_TxFB_T (FF) Destination: TxFB_n<3> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.195ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[2].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X17Y3.CLK1 net (fanout=7) 2.320 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.195ns (-5.305ns logic, 5.110ns route) Maximum Data Path at Slow Process Corner: g_TxFB[2].i_TxFB_T to TxFB_n<3> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X17Y3.TQ Tockq 0.740 TxFB<3> g_TxFB[2].i_TxFB_T AA16.T net (fanout=1) 0.438 TxFB_T<3> AA16.DIFFO_OUT Tiotd 1.909 TxFB_p<3> g_FB[3].i_TxFB/OBUFTDS AB16.DIFFO_IN net (fanout=1) 0.000 g_FB[3].i_TxFB/SLAVEBUF.DIFFOUT AB16.PAD Tiodop 0.027 TxFB_n<3> ProtoComp397.DIFFO_INUSED.6 TxFB_n<3> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<1> (AB18.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.185ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[0].i_TxFB (FF) Destination: TxFB_n<1> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.196ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK1 net (fanout=7) 2.319 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.196ns (-5.305ns logic, 5.109ns route) Maximum Data Path at Slow Process Corner: g_TxFB[0].i_TxFB to TxFB_n<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.OQ Tockq 1.158 TxFB<1> g_TxFB[0].i_TxFB AA18.O net (fanout=1) 0.438 TxFB<1> AA18.DIFFO_OUT Tiood 1.909 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS AB18.DIFFO_IN net (fanout=1) 0.000 g_FB[1].i_TxFB/SLAVEBUF.DIFFOUT AB18.PAD Tiodop 0.027 TxFB_n<1> ProtoComp397.DIFFO_INUSED.4 TxFB_n<1> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.603ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[0].i_TxFB_T (FF) Destination: TxFB_n<1> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.196ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK1 net (fanout=7) 2.319 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.196ns (-5.305ns logic, 5.109ns route) Maximum Data Path at Slow Process Corner: g_TxFB[0].i_TxFB_T to TxFB_n<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.TQ Tockq 0.740 TxFB<1> g_TxFB[0].i_TxFB_T AA18.T net (fanout=1) 0.438 TxFB_T<1> AA18.DIFFO_OUT Tiotd 1.909 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS AB18.DIFFO_IN net (fanout=1) 0.000 g_FB[1].i_TxFB/SLAVEBUF.DIFFOUT AB18.PAD Tiodop 0.027 TxFB_n<1> ProtoComp397.DIFFO_INUSED.4 TxFB_n<1> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<2> (AB17.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.235ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[1].i_TxFB (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.195ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK1 net (fanout=7) 2.320 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.195ns (-5.305ns logic, 5.110ns route) Maximum Data Path at Slow Process Corner: g_TxFB[1].i_TxFB to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.OQ Tockq 1.158 TxFB<2> g_TxFB[1].i_TxFB Y17.O net (fanout=1) 0.387 TxFB<2> Y17.DIFFO_OUT Tiood 1.909 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.027 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.653ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[1].i_TxFB_T (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.195ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 1.387 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.628 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 1.262 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -7.091 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.900 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.209 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK1 net (fanout=7) 2.320 TTCclkOut<0> ------------------------------------------------- --------------------------- Total -0.195ns (-5.305ns logic, 5.110ns route) Maximum Data Path at Slow Process Corner: g_TxFB[1].i_TxFB_T to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.TQ Tockq 0.740 TxFB<2> g_TxFB[1].i_TxFB_T Y17.T net (fanout=1) 0.387 TxFB_T<2> Y17.DIFFO_OUT Tiotd 1.909 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.027 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<0>" "FALLING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<2> (Y17.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.515ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB (FF) Destination: TxFB_p<2> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Data Path Delay: 1.298ns (Levels of Logic = 1) Clock Path Delay: 0.088ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK1 net (fanout=7) 0.862 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.088ns (-1.644ns logic, 1.732ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB to TxFB_p<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.OQ Tockq 0.425 TxFB<2> g_TxFB[1].i_TxFB Y17.O net (fanout=1) 0.268 TxFB<2> Y17.PAD Tioop 0.605 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS TxFB_p<2> ------------------------------------------------- --------------------------- Total 1.298ns (1.030ns logic, 0.268ns route) (79.4% logic, 20.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.341ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB_T (FF) Destination: TxFB_p<2> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Data Path Delay: 1.124ns (Levels of Logic = 1) Clock Path Delay: 0.088ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK1 net (fanout=7) 0.862 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.088ns (-1.644ns logic, 1.732ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB_T to TxFB_p<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.TQ Tockq 0.251 TxFB<2> g_TxFB[1].i_TxFB_T Y17.T net (fanout=1) 0.268 TxFB_T<2> Y17.PAD Tiotp 0.605 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS TxFB_p<2> ------------------------------------------------- --------------------------- Total 1.124ns (0.856ns logic, 0.268ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<2> (AB17.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.531ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Data Path Delay: 1.314ns (Levels of Logic = 2) Clock Path Delay: 0.088ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK1 net (fanout=7) 0.862 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.088ns (-1.644ns logic, 1.732ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.OQ Tockq 0.425 TxFB<2> g_TxFB[1].i_TxFB Y17.O net (fanout=1) 0.268 TxFB<2> Y17.DIFFO_OUT Tiood 0.613 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.008 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 1.314ns (1.046ns logic, 0.268ns route) (79.6% logic, 20.4% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.357ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[1].i_TxFB_T (FF) Destination: TxFB_n<2> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Data Path Delay: 1.140ns (Levels of Logic = 2) Clock Path Delay: 0.088ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[1].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X19Y1.CLK1 net (fanout=7) 0.862 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.088ns (-1.644ns logic, 1.732ns route) Minimum Data Path at Fast Process Corner: g_TxFB[1].i_TxFB_T to TxFB_n<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X19Y1.TQ Tockq 0.251 TxFB<2> g_TxFB[1].i_TxFB_T Y17.T net (fanout=1) 0.268 TxFB_T<2> Y17.DIFFO_OUT Tiotd 0.613 TxFB_p<2> g_FB[2].i_TxFB/OBUFTDS AB17.DIFFO_IN net (fanout=1) 0.000 g_FB[2].i_TxFB/SLAVEBUF.DIFFOUT AB17.PAD Tiodop 0.008 TxFB_n<2> ProtoComp397.DIFFO_INUSED.5 TxFB_n<2> ------------------------------------------------- --------------------------- Total 1.140ns (0.872ns logic, 0.268ns route) (76.5% logic, 23.5% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<1> (AA18.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.565ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[0].i_TxFB (FF) Destination: TxFB_p<1> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Data Path Delay: 1.349ns (Levels of Logic = 1) Clock Path Delay: 0.087ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK1 net (fanout=7) 0.861 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.087ns (-1.644ns logic, 1.731ns route) Minimum Data Path at Fast Process Corner: g_TxFB[0].i_TxFB to TxFB_p<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.OQ Tockq 0.425 TxFB<1> g_TxFB[0].i_TxFB AA18.O net (fanout=1) 0.319 TxFB<1> AA18.PAD Tioop 0.605 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS TxFB_p<1> ------------------------------------------------- --------------------------- Total 1.349ns (1.030ns logic, 0.319ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.391ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[0].i_TxFB_T (FF) Destination: TxFB_p<1> (PAD) Source Clock: TTCclkOut<0> falling at 3.404ns Data Path Delay: 1.175ns (Levels of Logic = 1) Clock Path Delay: 0.087ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<0> to g_TxFB[0].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- M20.I Tiopi 0.618 TTC_CLK_p<0> TTC_CLK_p<0> g_TTCclkOut[0].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.4 BUFIO2_X3Y12.I net (fanout=1) 0.205 TTCclk_in<0> BUFIO2_X3Y12.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y3.CLKIN net (fanout=1) 0.402 g_TTCclkOut[0].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y3.CLK0 Tdmcko_CLK -2.443 g_TTCclkOut[0].i_DCM_TTCclkOut g_TTCclkOut[0].i_DCM_TTCclkOut BUFGMUX_X2Y1.I0 net (fanout=1) 0.263 TTCclkOut_dcm<0> BUFGMUX_X2Y1.O Tgi0o 0.059 g_TTCclkOut[0].i_TTCclk_buf g_TTCclkOut[0].i_TTCclk_buf OLOGIC_X20Y3.CLK1 net (fanout=7) 0.861 TTCclkOut<0> ------------------------------------------------- --------------------------- Total 0.087ns (-1.644ns logic, 1.731ns route) Minimum Data Path at Fast Process Corner: g_TxFB[0].i_TxFB_T to TxFB_p<1> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X20Y3.TQ Tockq 0.251 TxFB<1> g_TxFB[0].i_TxFB_T AA18.T net (fanout=1) 0.319 TxFB_T<1> AA18.PAD Tiotp 0.605 TxFB_p<1> g_FB[1].i_TxFB/OBUFTDS TxFB_p<1> ------------------------------------------------- --------------------------- Total 1.175ns (0.856ns logic, 0.319ns route) (72.9% logic, 27.1% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<1>" "RISING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 7.011ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<4> (AB15.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.189ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[3].i_TxFB (FF) Destination: TxFB_n<4> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.200ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK0 net (fanout=7) 2.382 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.200ns (-5.678ns logic, 5.478ns route) Maximum Data Path at Slow Process Corner: g_TxFB[3].i_TxFB to TxFB_n<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.OQ Tockq 1.158 TxFB<4> g_TxFB[3].i_TxFB Y15.O net (fanout=1) 0.438 TxFB<4> Y15.DIFFO_OUT Tiood 1.909 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS AB15.DIFFO_IN net (fanout=1) 0.000 g_FB[4].i_TxFB/SLAVEBUF.DIFFOUT AB15.PAD Tiodop 0.027 TxFB_n<4> ProtoComp397.DIFFO_INUSED.7 TxFB_n<4> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.607ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[3].i_TxFB_T (FF) Destination: TxFB_n<4> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.200ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK0 net (fanout=7) 2.382 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.200ns (-5.678ns logic, 5.478ns route) Maximum Data Path at Slow Process Corner: g_TxFB[3].i_TxFB_T to TxFB_n<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.TQ Tockq 0.740 TxFB<4> g_TxFB[3].i_TxFB_T Y15.T net (fanout=1) 0.438 TxFB_T<4> Y15.DIFFO_OUT Tiotd 1.909 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS AB15.DIFFO_IN net (fanout=1) 0.000 g_FB[4].i_TxFB/SLAVEBUF.DIFFOUT AB15.PAD Tiodop 0.027 TxFB_n<4> ProtoComp397.DIFFO_INUSED.7 TxFB_n<4> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<5> (AB13.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.189ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[4].i_TxFB (FF) Destination: TxFB_n<5> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.200ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[4].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X14Y3.CLK0 net (fanout=7) 2.382 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.200ns (-5.678ns logic, 5.478ns route) Maximum Data Path at Slow Process Corner: g_TxFB[4].i_TxFB to TxFB_n<5> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X14Y3.OQ Tockq 1.158 TxFB<5> g_TxFB[4].i_TxFB Y13.O net (fanout=1) 0.438 TxFB<5> Y13.DIFFO_OUT Tiood 1.909 TxFB_p<5> g_FB[5].i_TxFB/OBUFTDS AB13.DIFFO_IN net (fanout=1) 0.000 g_FB[5].i_TxFB/SLAVEBUF.DIFFOUT AB13.PAD Tiodop 0.027 TxFB_n<5> ProtoComp397.DIFFO_INUSED.8 TxFB_n<5> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.607ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[4].i_TxFB_T (FF) Destination: TxFB_n<5> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.200ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[4].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X14Y3.CLK0 net (fanout=7) 2.382 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.200ns (-5.678ns logic, 5.478ns route) Maximum Data Path at Slow Process Corner: g_TxFB[4].i_TxFB_T to TxFB_n<5> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X14Y3.TQ Tockq 0.740 TxFB<5> g_TxFB[4].i_TxFB_T Y13.T net (fanout=1) 0.438 TxFB_T<5> Y13.DIFFO_OUT Tiotd 1.909 TxFB_p<5> g_FB[5].i_TxFB/OBUFTDS AB13.DIFFO_IN net (fanout=1) 0.000 g_FB[5].i_TxFB/SLAVEBUF.DIFFOUT AB13.PAD Tiodop 0.027 TxFB_n<5> ProtoComp397.DIFFO_INUSED.8 TxFB_n<5> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<6> (AB12.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.218ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[5].i_TxFB (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.178ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK0 net (fanout=7) 2.404 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.178ns (-5.678ns logic, 5.500ns route) Maximum Data Path at Slow Process Corner: g_TxFB[5].i_TxFB to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.OQ Tockq 1.158 TxFB<6> g_TxFB[5].i_TxFB AA12.O net (fanout=1) 0.387 TxFB<6> AA12.DIFFO_OUT Tiood 1.909 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.027 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.636ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[5].i_TxFB_T (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.178ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK0 net (fanout=7) 2.404 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.178ns (-5.678ns logic, 5.500ns route) Maximum Data Path at Slow Process Corner: g_TxFB[5].i_TxFB_T to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.TQ Tockq 0.740 TxFB<6> g_TxFB[5].i_TxFB_T AA12.T net (fanout=1) 0.387 TxFB_T<6> AA12.DIFFO_OUT Tiotd 1.909 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.027 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<1>" "RISING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<6> (AA12.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.536ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB (FF) Destination: TxFB_p<6> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Data Path Delay: 1.292ns (Levels of Logic = 1) Clock Path Delay: 0.115ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK0 net (fanout=7) 0.956 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.115ns (-1.841ns logic, 1.956ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB to TxFB_p<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.OQ Tockq 0.419 TxFB<6> g_TxFB[5].i_TxFB AA12.O net (fanout=1) 0.268 TxFB<6> AA12.PAD Tioop 0.605 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS TxFB_p<6> ------------------------------------------------- --------------------------- Total 1.292ns (1.024ns logic, 0.268ns route) (79.3% logic, 20.7% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.362ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB_T (FF) Destination: TxFB_p<6> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Data Path Delay: 1.118ns (Levels of Logic = 1) Clock Path Delay: 0.115ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK0 net (fanout=7) 0.956 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.115ns (-1.841ns logic, 1.956ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB_T to TxFB_p<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.TQ Tockq 0.245 TxFB<6> g_TxFB[5].i_TxFB_T AA12.T net (fanout=1) 0.268 TxFB_T<6> AA12.PAD Tiotp 0.605 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS TxFB_p<6> ------------------------------------------------- --------------------------- Total 1.118ns (0.850ns logic, 0.268ns route) (76.0% logic, 24.0% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<6> (AB12.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.552ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Data Path Delay: 1.308ns (Levels of Logic = 2) Clock Path Delay: 0.115ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK0 net (fanout=7) 0.956 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.115ns (-1.841ns logic, 1.956ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.OQ Tockq 0.419 TxFB<6> g_TxFB[5].i_TxFB AA12.O net (fanout=1) 0.268 TxFB<6> AA12.DIFFO_OUT Tiood 0.613 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.008 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 1.308ns (1.040ns logic, 0.268ns route) (79.5% logic, 20.5% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.378ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB_T (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Data Path Delay: 1.134ns (Levels of Logic = 2) Clock Path Delay: 0.115ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK0 net (fanout=7) 0.956 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.115ns (-1.841ns logic, 1.956ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB_T to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.TQ Tockq 0.245 TxFB<6> g_TxFB[5].i_TxFB_T AA12.T net (fanout=1) 0.268 TxFB_T<6> AA12.DIFFO_OUT Tiotd 0.613 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.008 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 1.134ns (0.866ns logic, 0.268ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<4> (Y15.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.565ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[3].i_TxFB (FF) Destination: TxFB_p<4> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Data Path Delay: 1.343ns (Levels of Logic = 1) Clock Path Delay: 0.093ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK0 net (fanout=7) 0.934 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.093ns (-1.841ns logic, 1.934ns route) Minimum Data Path at Fast Process Corner: g_TxFB[3].i_TxFB to TxFB_p<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.OQ Tockq 0.419 TxFB<4> g_TxFB[3].i_TxFB Y15.O net (fanout=1) 0.319 TxFB<4> Y15.PAD Tioop 0.605 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS TxFB_p<4> ------------------------------------------------- --------------------------- Total 1.343ns (1.024ns logic, 0.319ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.391ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[3].i_TxFB_T (FF) Destination: TxFB_p<4> (PAD) Source Clock: TTCclkOut<1> rising at 3.404ns Data Path Delay: 1.169ns (Levels of Logic = 1) Clock Path Delay: 0.093ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK0 net (fanout=7) 0.934 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.093ns (-1.841ns logic, 1.934ns route) Minimum Data Path at Fast Process Corner: g_TxFB[3].i_TxFB_T to TxFB_p<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.TQ Tockq 0.245 TxFB<4> g_TxFB[3].i_TxFB_T Y15.T net (fanout=1) 0.319 TxFB_T<4> Y15.PAD Tiotp 0.605 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS TxFB_p<4> ------------------------------------------------- --------------------------- Total 1.169ns (0.850ns logic, 0.319ns route) (72.7% logic, 27.3% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<1>" "FALLING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 6.949ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<4> (AB15.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.251ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[3].i_TxFB (FF) Destination: TxFB_n<4> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.262ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK1 net (fanout=7) 2.320 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.262ns (-5.678ns logic, 5.416ns route) Maximum Data Path at Slow Process Corner: g_TxFB[3].i_TxFB to TxFB_n<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.OQ Tockq 1.158 TxFB<4> g_TxFB[3].i_TxFB Y15.O net (fanout=1) 0.438 TxFB<4> Y15.DIFFO_OUT Tiood 1.909 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS AB15.DIFFO_IN net (fanout=1) 0.000 g_FB[4].i_TxFB/SLAVEBUF.DIFFOUT AB15.PAD Tiodop 0.027 TxFB_n<4> ProtoComp397.DIFFO_INUSED.7 TxFB_n<4> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.669ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[3].i_TxFB_T (FF) Destination: TxFB_n<4> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.262ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK1 net (fanout=7) 2.320 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.262ns (-5.678ns logic, 5.416ns route) Maximum Data Path at Slow Process Corner: g_TxFB[3].i_TxFB_T to TxFB_n<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.TQ Tockq 0.740 TxFB<4> g_TxFB[3].i_TxFB_T Y15.T net (fanout=1) 0.438 TxFB_T<4> Y15.DIFFO_OUT Tiotd 1.909 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS AB15.DIFFO_IN net (fanout=1) 0.000 g_FB[4].i_TxFB/SLAVEBUF.DIFFOUT AB15.PAD Tiodop 0.027 TxFB_n<4> ProtoComp397.DIFFO_INUSED.7 TxFB_n<4> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<5> (AB13.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.251ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[4].i_TxFB (FF) Destination: TxFB_n<5> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.262ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[4].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X14Y3.CLK1 net (fanout=7) 2.320 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.262ns (-5.678ns logic, 5.416ns route) Maximum Data Path at Slow Process Corner: g_TxFB[4].i_TxFB to TxFB_n<5> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X14Y3.OQ Tockq 1.158 TxFB<5> g_TxFB[4].i_TxFB Y13.O net (fanout=1) 0.438 TxFB<5> Y13.DIFFO_OUT Tiood 1.909 TxFB_p<5> g_FB[5].i_TxFB/OBUFTDS AB13.DIFFO_IN net (fanout=1) 0.000 g_FB[5].i_TxFB/SLAVEBUF.DIFFOUT AB13.PAD Tiodop 0.027 TxFB_n<5> ProtoComp397.DIFFO_INUSED.8 TxFB_n<5> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.669ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[4].i_TxFB_T (FF) Destination: TxFB_n<5> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.262ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[4].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X14Y3.CLK1 net (fanout=7) 2.320 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.262ns (-5.678ns logic, 5.416ns route) Maximum Data Path at Slow Process Corner: g_TxFB[4].i_TxFB_T to TxFB_n<5> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X14Y3.TQ Tockq 0.740 TxFB<5> g_TxFB[4].i_TxFB_T Y13.T net (fanout=1) 0.438 TxFB_T<5> Y13.DIFFO_OUT Tiotd 1.909 TxFB_p<5> g_FB[5].i_TxFB/OBUFTDS AB13.DIFFO_IN net (fanout=1) 0.000 g_FB[5].i_TxFB/SLAVEBUF.DIFFOUT AB13.PAD Tiodop 0.027 TxFB_n<5> ProtoComp397.DIFFO_INUSED.8 TxFB_n<5> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<6> (AB12.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.279ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[5].i_TxFB (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.239ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK1 net (fanout=7) 2.343 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.239ns (-5.678ns logic, 5.439ns route) Maximum Data Path at Slow Process Corner: g_TxFB[5].i_TxFB to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.OQ Tockq 1.158 TxFB<6> g_TxFB[5].i_TxFB AA12.O net (fanout=1) 0.387 TxFB<6> AA12.DIFFO_OUT Tiood 1.909 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.027 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.697ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[5].i_TxFB_T (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.239ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 1.387 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.627 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 1.262 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -7.464 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 1.207 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.209 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK1 net (fanout=7) 2.343 TTCclkOut<1> ------------------------------------------------- --------------------------- Total -0.239ns (-5.678ns logic, 5.439ns route) Maximum Data Path at Slow Process Corner: g_TxFB[5].i_TxFB_T to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.TQ Tockq 0.740 TxFB<6> g_TxFB[5].i_TxFB_T AA12.T net (fanout=1) 0.387 TxFB_T<6> AA12.DIFFO_OUT Tiotd 1.909 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.027 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<1>" "FALLING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<6> (AA12.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.471ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB (FF) Destination: TxFB_p<6> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Data Path Delay: 1.298ns (Levels of Logic = 1) Clock Path Delay: 0.044ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK1 net (fanout=7) 0.885 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.044ns (-1.841ns logic, 1.885ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB to TxFB_p<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.OQ Tockq 0.425 TxFB<6> g_TxFB[5].i_TxFB AA12.O net (fanout=1) 0.268 TxFB<6> AA12.PAD Tioop 0.605 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS TxFB_p<6> ------------------------------------------------- --------------------------- Total 1.298ns (1.030ns logic, 0.268ns route) (79.4% logic, 20.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.297ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB_T (FF) Destination: TxFB_p<6> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Data Path Delay: 1.124ns (Levels of Logic = 1) Clock Path Delay: 0.044ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK1 net (fanout=7) 0.885 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.044ns (-1.841ns logic, 1.885ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB_T to TxFB_p<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.TQ Tockq 0.251 TxFB<6> g_TxFB[5].i_TxFB_T AA12.T net (fanout=1) 0.268 TxFB_T<6> AA12.PAD Tiotp 0.605 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS TxFB_p<6> ------------------------------------------------- --------------------------- Total 1.124ns (0.856ns logic, 0.268ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<6> (AB12.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.487ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Data Path Delay: 1.314ns (Levels of Logic = 2) Clock Path Delay: 0.044ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK1 net (fanout=7) 0.885 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.044ns (-1.841ns logic, 1.885ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.OQ Tockq 0.425 TxFB<6> g_TxFB[5].i_TxFB AA12.O net (fanout=1) 0.268 TxFB<6> AA12.DIFFO_OUT Tiood 0.613 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.008 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 1.314ns (1.046ns logic, 0.268ns route) (79.6% logic, 20.4% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.313ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[5].i_TxFB_T (FF) Destination: TxFB_n<6> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Data Path Delay: 1.140ns (Levels of Logic = 2) Clock Path Delay: 0.044ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[5].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X13Y1.CLK1 net (fanout=7) 0.885 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.044ns (-1.841ns logic, 1.885ns route) Minimum Data Path at Fast Process Corner: g_TxFB[5].i_TxFB_T to TxFB_n<6> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y1.TQ Tockq 0.251 TxFB<6> g_TxFB[5].i_TxFB_T AA12.T net (fanout=1) 0.268 TxFB_T<6> AA12.DIFFO_OUT Tiotd 0.613 TxFB_p<6> g_FB[6].i_TxFB/OBUFTDS AB12.DIFFO_IN net (fanout=1) 0.000 g_FB[6].i_TxFB/SLAVEBUF.DIFFOUT AB12.PAD Tiodop 0.008 TxFB_n<6> ProtoComp397.DIFFO_INUSED.9 TxFB_n<6> ------------------------------------------------- --------------------------- Total 1.140ns (0.872ns logic, 0.268ns route) (76.5% logic, 23.5% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<4> (Y15.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.499ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[3].i_TxFB (FF) Destination: TxFB_p<4> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Data Path Delay: 1.349ns (Levels of Logic = 1) Clock Path Delay: 0.021ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK1 net (fanout=7) 0.862 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.021ns (-1.841ns logic, 1.862ns route) Minimum Data Path at Fast Process Corner: g_TxFB[3].i_TxFB to TxFB_p<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.OQ Tockq 0.425 TxFB<4> g_TxFB[3].i_TxFB Y15.O net (fanout=1) 0.319 TxFB<4> Y15.PAD Tioop 0.605 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS TxFB_p<4> ------------------------------------------------- --------------------------- Total 1.349ns (1.030ns logic, 0.319ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.325ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[3].i_TxFB_T (FF) Destination: TxFB_p<4> (PAD) Source Clock: TTCclkOut<1> falling at 3.404ns Data Path Delay: 1.175ns (Levels of Logic = 1) Clock Path Delay: 0.021ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<1> to g_TxFB[3].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K21.I Tiopi 0.618 TTC_CLK_p<1> TTC_CLK_p<1> g_TTCclkOut[1].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.5 BUFIO2_X3Y10.I net (fanout=1) 0.204 TTCclk_in<1> BUFIO2_X3Y10.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 SP6_BUFIO_INSERT_ML_BUFIO2_1 DCM_X0Y1.CLKIN net (fanout=1) 0.402 g_TTCclkOut[1].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y1.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[1].i_DCM_TTCclkOut g_TTCclkOut[1].i_DCM_TTCclkOut BUFGMUX_X2Y4.I0 net (fanout=1) 0.394 TTCclkOut_dcm<1> BUFGMUX_X2Y4.O Tgi0o 0.059 g_TTCclkOut[1].i_TTCclk_buf g_TTCclkOut[1].i_TTCclk_buf OLOGIC_X16Y3.CLK1 net (fanout=7) 0.862 TTCclkOut<1> ------------------------------------------------- --------------------------- Total 0.021ns (-1.841ns logic, 1.862ns route) Minimum Data Path at Fast Process Corner: g_TxFB[3].i_TxFB_T to TxFB_p<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X16Y3.TQ Tockq 0.251 TxFB<4> g_TxFB[3].i_TxFB_T Y15.T net (fanout=1) 0.319 TxFB_T<4> Y15.PAD Tiotp 0.605 TxFB_p<4> g_FB[4].i_TxFB/OBUFTDS TxFB_p<4> ------------------------------------------------- --------------------------- Total 1.175ns (0.856ns logic, 0.319ns route) (72.9% logic, 27.1% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<2>" "RISING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 6.963ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<7> (AB11.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.237ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[6].i_TxFB (FF) Destination: TxFB_n<7> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.248ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK0 net (fanout=7) 2.404 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.248ns (-5.288ns logic, 5.040ns route) Maximum Data Path at Slow Process Corner: g_TxFB[6].i_TxFB to TxFB_n<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.OQ Tockq 1.158 TxFB<7> g_TxFB[6].i_TxFB Y11.O net (fanout=1) 0.438 TxFB<7> Y11.DIFFO_OUT Tiood 1.909 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS AB11.DIFFO_IN net (fanout=1) 0.000 g_FB[7].i_TxFB/SLAVEBUF.DIFFOUT AB11.PAD Tiodop 0.027 TxFB_n<7> ProtoComp397.DIFFO_INUSED.10 TxFB_n<7> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.655ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[6].i_TxFB_T (FF) Destination: TxFB_n<7> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.248ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK0 net (fanout=7) 2.404 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.248ns (-5.288ns logic, 5.040ns route) Maximum Data Path at Slow Process Corner: g_TxFB[6].i_TxFB_T to TxFB_n<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.TQ Tockq 0.740 TxFB<7> g_TxFB[6].i_TxFB_T Y11.T net (fanout=1) 0.438 TxFB_T<7> Y11.DIFFO_OUT Tiotd 1.909 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS AB11.DIFFO_IN net (fanout=1) 0.000 g_FB[7].i_TxFB/SLAVEBUF.DIFFOUT AB11.PAD Tiodop 0.027 TxFB_n<7> ProtoComp397.DIFFO_INUSED.10 TxFB_n<7> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<8> (AB10.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.237ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[7].i_TxFB (FF) Destination: TxFB_n<8> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.248ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK0 net (fanout=7) 2.404 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.248ns (-5.288ns logic, 5.040ns route) Maximum Data Path at Slow Process Corner: g_TxFB[7].i_TxFB to TxFB_n<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.OQ Tockq 1.158 TxFB<8> g_TxFB[7].i_TxFB AA10.O net (fanout=1) 0.438 TxFB<8> AA10.DIFFO_OUT Tiood 1.909 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS AB10.DIFFO_IN net (fanout=1) 0.000 g_FB[8].i_TxFB/SLAVEBUF.DIFFOUT AB10.PAD Tiodop 0.027 TxFB_n<8> ProtoComp397.DIFFO_INUSED.11 TxFB_n<8> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.655ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[7].i_TxFB_T (FF) Destination: TxFB_n<8> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.248ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK0 net (fanout=7) 2.404 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.248ns (-5.288ns logic, 5.040ns route) Maximum Data Path at Slow Process Corner: g_TxFB[7].i_TxFB_T to TxFB_n<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.TQ Tockq 0.740 TxFB<8> g_TxFB[7].i_TxFB_T AA10.T net (fanout=1) 0.438 TxFB_T<8> AA10.DIFFO_OUT Tiotd 1.909 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS AB10.DIFFO_IN net (fanout=1) 0.000 g_FB[8].i_TxFB/SLAVEBUF.DIFFOUT AB10.PAD Tiodop 0.027 TxFB_n<8> ProtoComp397.DIFFO_INUSED.11 TxFB_n<8> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<9> (AB8.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.238ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[8].i_TxFB (FF) Destination: TxFB_n<9> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.249ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK0 net (fanout=7) 2.403 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.249ns (-5.288ns logic, 5.039ns route) Maximum Data Path at Slow Process Corner: g_TxFB[8].i_TxFB to TxFB_n<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.OQ Tockq 1.158 TxFB<9> g_TxFB[8].i_TxFB AA8.O net (fanout=1) 0.438 TxFB<9> AA8.DIFFO_OUT Tiood 1.909 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS AB8.DIFFO_IN net (fanout=1) 0.000 g_FB[9].i_TxFB/SLAVEBUF.DIFFOUT AB8.PAD Tiodop 0.027 TxFB_n<9> ProtoComp397.DIFFO_INUSED.12 TxFB_n<9> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.656ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[8].i_TxFB_T (FF) Destination: TxFB_n<9> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.249ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK0 net (fanout=7) 2.403 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.249ns (-5.288ns logic, 5.039ns route) Maximum Data Path at Slow Process Corner: g_TxFB[8].i_TxFB_T to TxFB_n<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.TQ Tockq 0.740 TxFB<9> g_TxFB[8].i_TxFB_T AA8.T net (fanout=1) 0.438 TxFB_T<9> AA8.DIFFO_OUT Tiotd 1.909 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS AB8.DIFFO_IN net (fanout=1) 0.000 g_FB[9].i_TxFB/SLAVEBUF.DIFFOUT AB8.PAD Tiodop 0.027 TxFB_n<9> ProtoComp397.DIFFO_INUSED.12 TxFB_n<9> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<2>" "RISING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<9> (AA8.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.516ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[8].i_TxFB (FF) Destination: TxFB_p<9> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Data Path Delay: 1.343ns (Levels of Logic = 1) Clock Path Delay: 0.044ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK0 net (fanout=7) 0.955 TTCclkOut<2> ------------------------------------------------- --------------------------- Total 0.044ns (-1.715ns logic, 1.759ns route) Minimum Data Path at Fast Process Corner: g_TxFB[8].i_TxFB to TxFB_p<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.OQ Tockq 0.419 TxFB<9> g_TxFB[8].i_TxFB AA8.O net (fanout=1) 0.319 TxFB<9> AA8.PAD Tioop 0.605 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS TxFB_p<9> ------------------------------------------------- --------------------------- Total 1.343ns (1.024ns logic, 0.319ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.342ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[8].i_TxFB_T (FF) Destination: TxFB_p<9> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Data Path Delay: 1.169ns (Levels of Logic = 1) Clock Path Delay: 0.044ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK0 net (fanout=7) 0.955 TTCclkOut<2> ------------------------------------------------- --------------------------- Total 0.044ns (-1.715ns logic, 1.759ns route) Minimum Data Path at Fast Process Corner: g_TxFB[8].i_TxFB_T to TxFB_p<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.TQ Tockq 0.245 TxFB<9> g_TxFB[8].i_TxFB_T AA8.T net (fanout=1) 0.319 TxFB_T<9> AA8.PAD Tiotp 0.605 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS TxFB_p<9> ------------------------------------------------- --------------------------- Total 1.169ns (0.850ns logic, 0.319ns route) (72.7% logic, 27.3% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<7> (Y11.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.517ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[6].i_TxFB (FF) Destination: TxFB_p<7> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Data Path Delay: 1.343ns (Levels of Logic = 1) Clock Path Delay: 0.045ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK0 net (fanout=7) 0.956 TTCclkOut<2> ------------------------------------------------- --------------------------- Total 0.045ns (-1.715ns logic, 1.760ns route) Minimum Data Path at Fast Process Corner: g_TxFB[6].i_TxFB to TxFB_p<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.OQ Tockq 0.419 TxFB<7> g_TxFB[6].i_TxFB Y11.O net (fanout=1) 0.319 TxFB<7> Y11.PAD Tioop 0.605 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS TxFB_p<7> ------------------------------------------------- --------------------------- Total 1.343ns (1.024ns logic, 0.319ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.343ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[6].i_TxFB_T (FF) Destination: TxFB_p<7> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Data Path Delay: 1.169ns (Levels of Logic = 1) Clock Path Delay: 0.045ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK0 net (fanout=7) 0.956 TTCclkOut<2> ------------------------------------------------- --------------------------- Total 0.045ns (-1.715ns logic, 1.760ns route) Minimum Data Path at Fast Process Corner: g_TxFB[6].i_TxFB_T to TxFB_p<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.TQ Tockq 0.245 TxFB<7> g_TxFB[6].i_TxFB_T Y11.T net (fanout=1) 0.319 TxFB_T<7> Y11.PAD Tiotp 0.605 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS TxFB_p<7> ------------------------------------------------- --------------------------- Total 1.169ns (0.850ns logic, 0.319ns route) (72.7% logic, 27.3% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<8> (AA10.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.517ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[7].i_TxFB (FF) Destination: TxFB_p<8> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Data Path Delay: 1.343ns (Levels of Logic = 1) Clock Path Delay: 0.045ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK0 net (fanout=7) 0.956 TTCclkOut<2> ------------------------------------------------- --------------------------- Total 0.045ns (-1.715ns logic, 1.760ns route) Minimum Data Path at Fast Process Corner: g_TxFB[7].i_TxFB to TxFB_p<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.OQ Tockq 0.419 TxFB<8> g_TxFB[7].i_TxFB AA10.O net (fanout=1) 0.319 TxFB<8> AA10.PAD Tioop 0.605 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS TxFB_p<8> ------------------------------------------------- --------------------------- Total 1.343ns (1.024ns logic, 0.319ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.343ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[7].i_TxFB_T (FF) Destination: TxFB_p<8> (PAD) Source Clock: TTCclkOut<2> rising at 3.404ns Data Path Delay: 1.169ns (Levels of Logic = 1) Clock Path Delay: 0.045ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK0 net (fanout=7) 0.956 TTCclkOut<2> ------------------------------------------------- --------------------------- Total 0.045ns (-1.715ns logic, 1.760ns route) Minimum Data Path at Fast Process Corner: g_TxFB[7].i_TxFB_T to TxFB_p<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.TQ Tockq 0.245 TxFB<8> g_TxFB[7].i_TxFB_T AA10.T net (fanout=1) 0.319 TxFB_T<8> AA10.PAD Tiotp 0.605 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS TxFB_p<8> ------------------------------------------------- --------------------------- Total 1.169ns (0.850ns logic, 0.319ns route) (72.7% logic, 27.3% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<2>" "FALLING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 6.901ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<7> (AB11.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.299ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[6].i_TxFB (FF) Destination: TxFB_n<7> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.310ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK1 net (fanout=7) 2.342 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.310ns (-5.288ns logic, 4.978ns route) Maximum Data Path at Slow Process Corner: g_TxFB[6].i_TxFB to TxFB_n<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.OQ Tockq 1.158 TxFB<7> g_TxFB[6].i_TxFB Y11.O net (fanout=1) 0.438 TxFB<7> Y11.DIFFO_OUT Tiood 1.909 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS AB11.DIFFO_IN net (fanout=1) 0.000 g_FB[7].i_TxFB/SLAVEBUF.DIFFOUT AB11.PAD Tiodop 0.027 TxFB_n<7> ProtoComp397.DIFFO_INUSED.10 TxFB_n<7> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.717ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[6].i_TxFB_T (FF) Destination: TxFB_n<7> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.310ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK1 net (fanout=7) 2.342 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.310ns (-5.288ns logic, 4.978ns route) Maximum Data Path at Slow Process Corner: g_TxFB[6].i_TxFB_T to TxFB_n<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.TQ Tockq 0.740 TxFB<7> g_TxFB[6].i_TxFB_T Y11.T net (fanout=1) 0.438 TxFB_T<7> Y11.DIFFO_OUT Tiotd 1.909 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS AB11.DIFFO_IN net (fanout=1) 0.000 g_FB[7].i_TxFB/SLAVEBUF.DIFFOUT AB11.PAD Tiodop 0.027 TxFB_n<7> ProtoComp397.DIFFO_INUSED.10 TxFB_n<7> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<8> (AB10.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.299ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[7].i_TxFB (FF) Destination: TxFB_n<8> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.310ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK1 net (fanout=7) 2.342 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.310ns (-5.288ns logic, 4.978ns route) Maximum Data Path at Slow Process Corner: g_TxFB[7].i_TxFB to TxFB_n<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.OQ Tockq 1.158 TxFB<8> g_TxFB[7].i_TxFB AA10.O net (fanout=1) 0.438 TxFB<8> AA10.DIFFO_OUT Tiood 1.909 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS AB10.DIFFO_IN net (fanout=1) 0.000 g_FB[8].i_TxFB/SLAVEBUF.DIFFOUT AB10.PAD Tiodop 0.027 TxFB_n<8> ProtoComp397.DIFFO_INUSED.11 TxFB_n<8> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.717ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[7].i_TxFB_T (FF) Destination: TxFB_n<8> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.310ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK1 net (fanout=7) 2.342 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.310ns (-5.288ns logic, 4.978ns route) Maximum Data Path at Slow Process Corner: g_TxFB[7].i_TxFB_T to TxFB_n<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.TQ Tockq 0.740 TxFB<8> g_TxFB[7].i_TxFB_T AA10.T net (fanout=1) 0.438 TxFB_T<8> AA10.DIFFO_OUT Tiotd 1.909 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS AB10.DIFFO_IN net (fanout=1) 0.000 g_FB[8].i_TxFB/SLAVEBUF.DIFFOUT AB10.PAD Tiodop 0.027 TxFB_n<8> ProtoComp397.DIFFO_INUSED.11 TxFB_n<8> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<9> (AB8.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.299ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[8].i_TxFB (FF) Destination: TxFB_n<9> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.310ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK1 net (fanout=7) 2.342 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.310ns (-5.288ns logic, 4.978ns route) Maximum Data Path at Slow Process Corner: g_TxFB[8].i_TxFB to TxFB_n<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.OQ Tockq 1.158 TxFB<9> g_TxFB[8].i_TxFB AA8.O net (fanout=1) 0.438 TxFB<9> AA8.DIFFO_OUT Tiood 1.909 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS AB8.DIFFO_IN net (fanout=1) 0.000 g_FB[9].i_TxFB/SLAVEBUF.DIFFOUT AB8.PAD Tiodop 0.027 TxFB_n<9> ProtoComp397.DIFFO_INUSED.12 TxFB_n<9> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.717ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[8].i_TxFB_T (FF) Destination: TxFB_n<9> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.310ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 1.387 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.645 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 1.248 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -7.074 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.743 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.209 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK1 net (fanout=7) 2.342 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.310ns (-5.288ns logic, 4.978ns route) Maximum Data Path at Slow Process Corner: g_TxFB[8].i_TxFB_T to TxFB_n<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.TQ Tockq 0.740 TxFB<9> g_TxFB[8].i_TxFB_T AA8.T net (fanout=1) 0.438 TxFB_T<9> AA8.DIFFO_OUT Tiotd 1.909 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS AB8.DIFFO_IN net (fanout=1) 0.000 g_FB[9].i_TxFB/SLAVEBUF.DIFFOUT AB8.PAD Tiodop 0.027 TxFB_n<9> ProtoComp397.DIFFO_INUSED.12 TxFB_n<9> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<2>" "FALLING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<7> (Y11.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.451ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[6].i_TxFB (FF) Destination: TxFB_p<7> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Data Path Delay: 1.349ns (Levels of Logic = 1) Clock Path Delay: -0.027ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK1 net (fanout=7) 0.884 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.027ns (-1.715ns logic, 1.688ns route) Minimum Data Path at Fast Process Corner: g_TxFB[6].i_TxFB to TxFB_p<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.OQ Tockq 0.425 TxFB<7> g_TxFB[6].i_TxFB Y11.O net (fanout=1) 0.319 TxFB<7> Y11.PAD Tioop 0.605 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS TxFB_p<7> ------------------------------------------------- --------------------------- Total 1.349ns (1.030ns logic, 0.319ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.277ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[6].i_TxFB_T (FF) Destination: TxFB_p<7> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Data Path Delay: 1.175ns (Levels of Logic = 1) Clock Path Delay: -0.027ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[6].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X13Y3.CLK1 net (fanout=7) 0.884 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.027ns (-1.715ns logic, 1.688ns route) Minimum Data Path at Fast Process Corner: g_TxFB[6].i_TxFB_T to TxFB_p<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X13Y3.TQ Tockq 0.251 TxFB<7> g_TxFB[6].i_TxFB_T Y11.T net (fanout=1) 0.319 TxFB_T<7> Y11.PAD Tiotp 0.605 TxFB_p<7> g_FB[7].i_TxFB/OBUFTDS TxFB_p<7> ------------------------------------------------- --------------------------- Total 1.175ns (0.856ns logic, 0.319ns route) (72.9% logic, 27.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<8> (AA10.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.451ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[7].i_TxFB (FF) Destination: TxFB_p<8> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Data Path Delay: 1.349ns (Levels of Logic = 1) Clock Path Delay: -0.027ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK1 net (fanout=7) 0.884 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.027ns (-1.715ns logic, 1.688ns route) Minimum Data Path at Fast Process Corner: g_TxFB[7].i_TxFB to TxFB_p<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.OQ Tockq 0.425 TxFB<8> g_TxFB[7].i_TxFB AA10.O net (fanout=1) 0.319 TxFB<8> AA10.PAD Tioop 0.605 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS TxFB_p<8> ------------------------------------------------- --------------------------- Total 1.349ns (1.030ns logic, 0.319ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.277ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[7].i_TxFB_T (FF) Destination: TxFB_p<8> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Data Path Delay: 1.175ns (Levels of Logic = 1) Clock Path Delay: -0.027ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[7].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X12Y3.CLK1 net (fanout=7) 0.884 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.027ns (-1.715ns logic, 1.688ns route) Minimum Data Path at Fast Process Corner: g_TxFB[7].i_TxFB_T to TxFB_p<8> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X12Y3.TQ Tockq 0.251 TxFB<8> g_TxFB[7].i_TxFB_T AA10.T net (fanout=1) 0.319 TxFB_T<8> AA10.PAD Tiotp 0.605 TxFB_p<8> g_FB[8].i_TxFB/OBUFTDS TxFB_p<8> ------------------------------------------------- --------------------------- Total 1.175ns (0.856ns logic, 0.319ns route) (72.9% logic, 27.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<9> (AA8.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.451ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[8].i_TxFB (FF) Destination: TxFB_p<9> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Data Path Delay: 1.349ns (Levels of Logic = 1) Clock Path Delay: -0.027ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK1 net (fanout=7) 0.884 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.027ns (-1.715ns logic, 1.688ns route) Minimum Data Path at Fast Process Corner: g_TxFB[8].i_TxFB to TxFB_p<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.OQ Tockq 0.425 TxFB<9> g_TxFB[8].i_TxFB AA8.O net (fanout=1) 0.319 TxFB<9> AA8.PAD Tioop 0.605 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS TxFB_p<9> ------------------------------------------------- --------------------------- Total 1.349ns (1.030ns logic, 0.319ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.277ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[8].i_TxFB_T (FF) Destination: TxFB_p<9> (PAD) Source Clock: TTCclkOut<2> falling at 3.404ns Data Path Delay: 1.175ns (Levels of Logic = 1) Clock Path Delay: -0.027ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<2> to g_TxFB[8].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L3.I Tiopi 0.618 TTC_CLK_p<2> TTC_CLK_p<2> g_TTCclkOut[2].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.6 BUFIO2_X0Y16.I net (fanout=1) 0.222 TTCclk_in<2> BUFIO2_X0Y16.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_2 SP6_BUFIO_INSERT_ML_BUFIO2_2 DCM_X0Y4.CLKIN net (fanout=1) 0.388 g_TTCclkOut[2].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y4.CLK0 Tdmcko_CLK -2.514 g_TTCclkOut[2].i_DCM_TTCclkOut g_TTCclkOut[2].i_DCM_TTCclkOut BUFGMUX_X2Y2.I0 net (fanout=1) 0.194 TTCclkOut_dcm<2> BUFGMUX_X2Y2.O Tgi0o 0.059 g_TTCclkOut[2].i_TTCclk_buf g_TTCclkOut[2].i_TTCclk_buf OLOGIC_X10Y3.CLK1 net (fanout=7) 0.884 TTCclkOut<2> ------------------------------------------------- --------------------------- Total -0.027ns (-1.715ns logic, 1.688ns route) Minimum Data Path at Fast Process Corner: g_TxFB[8].i_TxFB_T to TxFB_p<9> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X10Y3.TQ Tockq 0.251 TxFB<9> g_TxFB[8].i_TxFB_T AA8.T net (fanout=1) 0.319 TxFB_T<9> AA8.PAD Tiotp 0.605 TxFB_p<9> g_FB[9].i_TxFB/OBUFTDS TxFB_p<9> ------------------------------------------------- --------------------------- Total 1.175ns (0.856ns logic, 0.319ns route) (72.9% logic, 27.1% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<3>" "RISING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 6.902ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<12> (AB4.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.298ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[11].i_TxFB (FF) Destination: TxFB_n<12> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[11].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X2Y3.CLK0 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[11].i_TxFB to TxFB_n<12> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X2Y3.OQ Tockq 1.158 TxFB<12> g_TxFB[11].i_TxFB AA4.O net (fanout=1) 0.438 TxFB<12> AA4.DIFFO_OUT Tiood 1.909 TxFB_p<12> g_FB[12].i_TxFB/OBUFTDS AB4.DIFFO_IN net (fanout=1) 0.000 g_FB[12].i_TxFB/SLAVEBUF.DIFFOUT AB4.PAD Tiodop 0.027 TxFB_n<12> ProtoComp397.DIFFO_INUSED.3 TxFB_n<12> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.716ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[11].i_TxFB_T (FF) Destination: TxFB_n<12> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[11].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X2Y3.CLK0 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[11].i_TxFB_T to TxFB_n<12> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X2Y3.TQ Tockq 0.740 TxFB<12> g_TxFB[11].i_TxFB_T AA4.T net (fanout=1) 0.438 TxFB_T<12> AA4.DIFFO_OUT Tiotd 1.909 TxFB_p<12> g_FB[12].i_TxFB/OBUFTDS AB4.DIFFO_IN net (fanout=1) 0.000 g_FB[12].i_TxFB/SLAVEBUF.DIFFOUT AB4.PAD Tiodop 0.027 TxFB_n<12> ProtoComp397.DIFFO_INUSED.3 TxFB_n<12> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<10> (AB7.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.349ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[9].i_TxFB (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK0 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[9].i_TxFB to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.OQ Tockq 1.158 TxFB<10> g_TxFB[9].i_TxFB Y7.O net (fanout=1) 0.387 TxFB<10> Y7.DIFFO_OUT Tiood 1.909 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.027 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.767ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[9].i_TxFB_T (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK0 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[9].i_TxFB_T to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.TQ Tockq 0.740 TxFB<10> g_TxFB[9].i_TxFB_T Y7.T net (fanout=1) 0.387 TxFB_T<10> Y7.DIFFO_OUT Tiotd 1.909 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.027 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<11> (AB6.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.349ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[10].i_TxFB (FF) Destination: TxFB_n<11> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK0 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[10].i_TxFB to TxFB_n<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.OQ Tockq 1.158 TxFB<11> g_TxFB[10].i_TxFB AA6.O net (fanout=1) 0.387 TxFB<11> AA6.DIFFO_OUT Tiood 1.909 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS AB6.DIFFO_IN net (fanout=1) 0.000 g_FB[11].i_TxFB/SLAVEBUF.DIFFOUT AB6.PAD Tiodop 0.027 TxFB_n<11> ProtoComp397.DIFFO_INUSED.2 TxFB_n<11> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.767ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[10].i_TxFB_T (FF) Destination: TxFB_n<11> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK0 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[10].i_TxFB_T to TxFB_n<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.TQ Tockq 0.740 TxFB<11> g_TxFB[10].i_TxFB_T AA6.T net (fanout=1) 0.387 TxFB_T<11> AA6.DIFFO_OUT Tiotd 1.909 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS AB6.DIFFO_IN net (fanout=1) 0.000 g_FB[11].i_TxFB/SLAVEBUF.DIFFOUT AB6.PAD Tiodop 0.027 TxFB_n<11> ProtoComp397.DIFFO_INUSED.2 TxFB_n<11> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<3>" "RISING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<10> (Y7.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.405ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB (FF) Destination: TxFB_p<10> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Data Path Delay: 1.292ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK0 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB to TxFB_p<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.OQ Tockq 0.419 TxFB<10> g_TxFB[9].i_TxFB Y7.O net (fanout=1) 0.268 TxFB<10> Y7.PAD Tioop 0.605 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS TxFB_p<10> ------------------------------------------------- --------------------------- Total 1.292ns (1.024ns logic, 0.268ns route) (79.3% logic, 20.7% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.231ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB_T (FF) Destination: TxFB_p<10> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Data Path Delay: 1.118ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK0 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB_T to TxFB_p<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.TQ Tockq 0.245 TxFB<10> g_TxFB[9].i_TxFB_T Y7.T net (fanout=1) 0.268 TxFB_T<10> Y7.PAD Tiotp 0.605 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS TxFB_p<10> ------------------------------------------------- --------------------------- Total 1.118ns (0.850ns logic, 0.268ns route) (76.0% logic, 24.0% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<11> (AA6.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.405ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[10].i_TxFB (FF) Destination: TxFB_p<11> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Data Path Delay: 1.292ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK0 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[10].i_TxFB to TxFB_p<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.OQ Tockq 0.419 TxFB<11> g_TxFB[10].i_TxFB AA6.O net (fanout=1) 0.268 TxFB<11> AA6.PAD Tioop 0.605 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS TxFB_p<11> ------------------------------------------------- --------------------------- Total 1.292ns (1.024ns logic, 0.268ns route) (79.3% logic, 20.7% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.231ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[10].i_TxFB_T (FF) Destination: TxFB_p<11> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Data Path Delay: 1.118ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK0 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[10].i_TxFB_T to TxFB_p<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.TQ Tockq 0.245 TxFB<11> g_TxFB[10].i_TxFB_T AA6.T net (fanout=1) 0.268 TxFB_T<11> AA6.PAD Tiotp 0.605 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS TxFB_p<11> ------------------------------------------------- --------------------------- Total 1.118ns (0.850ns logic, 0.268ns route) (76.0% logic, 24.0% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<10> (AB7.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.421ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Data Path Delay: 1.308ns (Levels of Logic = 2) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK0 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.OQ Tockq 0.419 TxFB<10> g_TxFB[9].i_TxFB Y7.O net (fanout=1) 0.268 TxFB<10> Y7.DIFFO_OUT Tiood 0.613 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.008 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 1.308ns (1.040ns logic, 0.268ns route) (79.5% logic, 20.5% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.247ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB_T (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> rising at 3.404ns Data Path Delay: 1.134ns (Levels of Logic = 2) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK0 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB_T to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.TQ Tockq 0.245 TxFB<10> g_TxFB[9].i_TxFB_T Y7.T net (fanout=1) 0.268 TxFB_T<10> Y7.DIFFO_OUT Tiotd 0.613 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.008 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 1.134ns (0.866ns logic, 0.268ns route) (76.4% logic, 23.6% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<3>" "FALLING"; For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). 12 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. Minimum allowable offset is 6.902ns. -------------------------------------------------------------------------------- Paths for end point TxFB_n<12> (AB4.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.298ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[11].i_TxFB (FF) Destination: TxFB_n<12> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.532ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[11].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X2Y3.CLK1 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[11].i_TxFB to TxFB_n<12> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X2Y3.OQ Tockq 1.158 TxFB<12> g_TxFB[11].i_TxFB AA4.O net (fanout=1) 0.438 TxFB<12> AA4.DIFFO_OUT Tiood 1.909 TxFB_p<12> g_FB[12].i_TxFB/OBUFTDS AB4.DIFFO_IN net (fanout=1) 0.000 g_FB[12].i_TxFB/SLAVEBUF.DIFFOUT AB4.PAD Tiodop 0.027 TxFB_n<12> ProtoComp397.DIFFO_INUSED.3 TxFB_n<12> ------------------------------------------------- --------------------------- Total 3.532ns (3.094ns logic, 0.438ns route) (87.6% logic, 12.4% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.716ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[11].i_TxFB_T (FF) Destination: TxFB_n<12> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.114ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[11].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X2Y3.CLK1 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[11].i_TxFB_T to TxFB_n<12> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X2Y3.TQ Tockq 0.740 TxFB<12> g_TxFB[11].i_TxFB_T AA4.T net (fanout=1) 0.438 TxFB_T<12> AA4.DIFFO_OUT Tiotd 1.909 TxFB_p<12> g_FB[12].i_TxFB/OBUFTDS AB4.DIFFO_IN net (fanout=1) 0.000 g_FB[12].i_TxFB/SLAVEBUF.DIFFOUT AB4.PAD Tiodop 0.027 TxFB_n<12> ProtoComp397.DIFFO_INUSED.3 TxFB_n<12> ------------------------------------------------- --------------------------- Total 3.114ns (2.676ns logic, 0.438ns route) (85.9% logic, 14.1% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<10> (AB7.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.349ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[9].i_TxFB (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK1 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[9].i_TxFB to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.OQ Tockq 1.158 TxFB<10> g_TxFB[9].i_TxFB Y7.O net (fanout=1) 0.387 TxFB<10> Y7.DIFFO_OUT Tiood 1.909 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.027 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.767ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[9].i_TxFB_T (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK1 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[9].i_TxFB_T to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.TQ Tockq 0.740 TxFB<10> g_TxFB[9].i_TxFB_T Y7.T net (fanout=1) 0.387 TxFB_T<10> Y7.DIFFO_OUT Tiotd 1.909 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.027 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<11> (AB6.PAD), 2 paths -------------------------------------------------------------------------------- Slack (slowest paths): 0.349ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[10].i_TxFB (FF) Destination: TxFB_n<11> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.481ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK1 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[10].i_TxFB to TxFB_n<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.OQ Tockq 1.158 TxFB<11> g_TxFB[10].i_TxFB AA6.O net (fanout=1) 0.387 TxFB<11> AA6.DIFFO_OUT Tiood 1.909 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS AB6.DIFFO_IN net (fanout=1) 0.000 g_FB[11].i_TxFB/SLAVEBUF.DIFFOUT AB6.PAD Tiodop 0.027 TxFB_n<11> ProtoComp397.DIFFO_INUSED.2 TxFB_n<11> ------------------------------------------------- --------------------------- Total 3.481ns (3.094ns logic, 0.387ns route) (88.9% logic, 11.1% route) -------------------------------------------------------------------------------- Slack (slowest paths): 0.767ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: g_TxFB[10].i_TxFB_T (FF) Destination: TxFB_n<11> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Requirement: 7.200ns Data Path Delay: 3.063ns (Levels of Logic = 2) Clock Path Delay: -0.309ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Clock Path at Slow Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 1.387 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.643 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 1.248 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -7.386 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 1.050 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.209 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK1 net (fanout=7) 2.350 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.309ns (-5.600ns logic, 5.291ns route) Maximum Data Path at Slow Process Corner: g_TxFB[10].i_TxFB_T to TxFB_n<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.TQ Tockq 0.740 TxFB<11> g_TxFB[10].i_TxFB_T AA6.T net (fanout=1) 0.387 TxFB_T<11> AA6.DIFFO_OUT Tiotd 1.909 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS AB6.DIFFO_IN net (fanout=1) 0.000 g_FB[11].i_TxFB/SLAVEBUF.DIFFOUT AB6.PAD Tiodop 0.027 TxFB_n<11> ProtoComp397.DIFFO_INUSED.2 TxFB_n<11> ------------------------------------------------- --------------------------- Total 3.063ns (2.676ns logic, 0.387ns route) (87.4% logic, 12.6% route) -------------------------------------------------------------------------------- Fastest Paths: OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<3>" "FALLING"; -------------------------------------------------------------------------------- Paths for end point TxFB_p<10> (Y7.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.411ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB (FF) Destination: TxFB_p<10> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Data Path Delay: 1.298ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK1 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB to TxFB_p<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.OQ Tockq 0.425 TxFB<10> g_TxFB[9].i_TxFB Y7.O net (fanout=1) 0.268 TxFB<10> Y7.PAD Tioop 0.605 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS TxFB_p<10> ------------------------------------------------- --------------------------- Total 1.298ns (1.030ns logic, 0.268ns route) (79.4% logic, 20.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.237ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB_T (FF) Destination: TxFB_p<10> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Data Path Delay: 1.124ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK1 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB_T to TxFB_p<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.TQ Tockq 0.251 TxFB<10> g_TxFB[9].i_TxFB_T Y7.T net (fanout=1) 0.268 TxFB_T<10> Y7.PAD Tiotp 0.605 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS TxFB_p<10> ------------------------------------------------- --------------------------- Total 1.124ns (0.856ns logic, 0.268ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Paths for end point TxFB_p<11> (AA6.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.411ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[10].i_TxFB (FF) Destination: TxFB_p<11> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Data Path Delay: 1.298ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK1 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[10].i_TxFB to TxFB_p<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.OQ Tockq 0.425 TxFB<11> g_TxFB[10].i_TxFB AA6.O net (fanout=1) 0.268 TxFB<11> AA6.PAD Tioop 0.605 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS TxFB_p<11> ------------------------------------------------- --------------------------- Total 1.298ns (1.030ns logic, 0.268ns route) (79.4% logic, 20.6% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.237ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[10].i_TxFB_T (FF) Destination: TxFB_p<11> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Data Path Delay: 1.124ns (Levels of Logic = 1) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[10].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X7Y1.CLK1 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[10].i_TxFB_T to TxFB_p<11> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X7Y1.TQ Tockq 0.251 TxFB<11> g_TxFB[10].i_TxFB_T AA6.T net (fanout=1) 0.268 TxFB_T<11> AA6.PAD Tiotp 0.605 TxFB_p<11> g_FB[11].i_TxFB/OBUFTDS TxFB_p<11> ------------------------------------------------- --------------------------- Total 1.124ns (0.856ns logic, 0.268ns route) (76.2% logic, 23.8% route) -------------------------------------------------------------------------------- Paths for end point TxFB_n<10> (AB7.PAD), 2 paths -------------------------------------------------------------------------------- Delay (fastest paths): 4.427ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Data Path Delay: 1.314ns (Levels of Logic = 2) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK1 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.OQ Tockq 0.425 TxFB<10> g_TxFB[9].i_TxFB Y7.O net (fanout=1) 0.268 TxFB<10> Y7.DIFFO_OUT Tiood 0.613 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.008 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 1.314ns (1.046ns logic, 0.268ns route) (79.6% logic, 20.4% route) -------------------------------------------------------------------------------- Delay (fastest paths): 4.253ns (clock arrival + clock path + data path - uncertainty) Source: g_TxFB[9].i_TxFB_T (FF) Destination: TxFB_n<10> (PAD) Source Clock: TTCclkOut<3> falling at 3.404ns Data Path Delay: 1.140ns (Levels of Logic = 2) Clock Path Delay: -0.016ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Clock Path at Fast Process Corner: TTC_CLK_p<3> to g_TxFB[9].i_TxFB_T Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- P3.I Tiopi 0.618 TTC_CLK_p<3> TTC_CLK_p<3> g_TTCclkOut[3].i_TTCclk_in/IBUFDS ProtoComp395.IMUX.7 BUFIO2_X0Y22.I net (fanout=1) 0.220 TTCclk_in<3> BUFIO2_X0Y22.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_3 SP6_BUFIO_INSERT_ML_BUFIO2_3 DCM_X0Y6.CLKIN net (fanout=1) 0.388 g_TTCclkOut[3].i_DCM_TTCclkOut_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.640 g_TTCclkOut[3].i_DCM_TTCclkOut g_TTCclkOut[3].i_DCM_TTCclkOut BUFGMUX_X3Y13.I0 net (fanout=1) 0.325 TTCclkOut_dcm<3> BUFGMUX_X3Y13.O Tgi0o 0.059 g_TTCclkOut[3].i_TTCclk_buf g_TTCclkOut[3].i_TTCclk_buf OLOGIC_X8Y1.CLK1 net (fanout=7) 0.892 TTCclkOut<3> ------------------------------------------------- --------------------------- Total -0.016ns (-1.841ns logic, 1.825ns route) Minimum Data Path at Fast Process Corner: g_TxFB[9].i_TxFB_T to TxFB_n<10> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- OLOGIC_X8Y1.TQ Tockq 0.251 TxFB<10> g_TxFB[9].i_TxFB_T Y7.T net (fanout=1) 0.268 TxFB_T<10> Y7.DIFFO_OUT Tiotd 0.613 TxFB_p<10> g_FB[10].i_TxFB/OBUFTDS AB7.DIFFO_IN net (fanout=1) 0.000 g_FB[10].i_TxFB/SLAVEBUF.DIFFOUT AB7.PAD Tiodop 0.008 TxFB_n<10> ProtoComp397.DIFFO_INUSED.1 TxFB_n<10> ------------------------------------------------- --------------------------- Total 1.140ns (0.872ns logic, 0.268ns route) (76.5% logic, 23.5% route) -------------------------------------------------------------------------------- Derived Constraint Report Derived Constraints for TS_TTC_REFCLK +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_TTC_REFCLK | 24.900ns| 10.000ns| 24.844ns| 0| 0| 0| 6578| | TS_TTCclk4x_dcm | 6.225ns| 6.211ns| N/A| 0| 0| 169| 0| | TS_TTCclk_dcm | 24.900ns| 24.772ns| 18.004ns| 0| 0| 6120| 2| | TS_TO_TTC_data_1_LD | 24.900ns| 18.004ns| N/A| 0| 0| 2| 0| | TS_TTCclk8x_dcm | 3.113ns| 2.784ns| N/A| 0| 0| 287| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_TTCclk_p +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_TTCclk_p | 24.900ns| 16.000ns| 2.666ns| 0| 0| 0| 0| | TS_TTCclkOut_dcm_0_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| | TS_TTCclkOut_dcm_1_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| | TS_TTCclkOut_dcm_2_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| | TS_TTCclkOut_dcm_3_ | 24.900ns| 2.666ns| N/A| 0| 0| 0| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_ipb_clk +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_ipb_clk | 32.000ns| 18.084ns| 3.122ns| 0| 0| 25799| 1| | TS_TO_CRC_0_LD | 32.000ns| 3.122ns| N/A| 0| 0| 1| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock TTC_REFCLK ------------+------------+------------+------------+------------+------------------+--------+ |Max Setup to| Process |Max Hold to | Process | | Clock | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | ------------+------------+------------+------------+------------+------------------+--------+ TTCdata_p | 7.333(R)| SLOW | -4.915(R)| FAST |TTCclk | -3.890| | 7.393(F)| SLOW | -4.990(F)| FAST |TTCclk | -3.890| ------------+------------+------------+------------+------------+------------------+--------+ Clock TTC_CLK_p<0> to Pad ------------+-----------------+------------+-----------------+------------+------------------+--------+ |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | ------------+-----------------+------------+-----------------+------------+------------------+--------+ TxFB_n<1> | 7.076(R)| SLOW | 4.472(R)| FAST |TTCclkOut<0> | 3.404| | 7.015(F)| SLOW | 4.407(F)| FAST |TTCclkOut<0> | 3.404| TxFB_n<2> | 7.026(R)| SLOW | 4.422(R)| FAST |TTCclkOut<0> | 3.404| | 6.965(F)| SLOW | 4.357(F)| FAST |TTCclkOut<0> | 3.404| TxFB_n<3> | 7.078(R)| SLOW | 4.474(R)| FAST |TTCclkOut<0> | 3.404| | 7.016(F)| SLOW | 4.408(F)| FAST |TTCclkOut<0> | 3.404| TxFB_p<1> | 7.022(R)| SLOW | 4.456(R)| FAST |TTCclkOut<0> | 3.404| | 6.961(F)| SLOW | 4.391(F)| FAST |TTCclkOut<0> | 3.404| TxFB_p<2> | 6.972(R)| SLOW | 4.406(R)| FAST |TTCclkOut<0> | 3.404| | 6.911(F)| SLOW | 4.341(F)| FAST |TTCclkOut<0> | 3.404| TxFB_p<3> | 7.024(R)| SLOW | 4.458(R)| FAST |TTCclkOut<0> | 3.404| | 6.962(F)| SLOW | 4.392(F)| FAST |TTCclkOut<0> | 3.404| ------------+-----------------+------------+-----------------+------------+------------------+--------+ Clock TTC_CLK_p<1> to Pad ------------+-----------------+------------+-----------------+------------+------------------+--------+ |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | ------------+-----------------+------------+-----------------+------------+------------------+--------+ TxFB_n<4> | 7.011(R)| SLOW | 4.407(R)| FAST |TTCclkOut<1> | 3.404| | 6.949(F)| SLOW | 4.341(F)| FAST |TTCclkOut<1> | 3.404| TxFB_n<5> | 7.011(R)| SLOW | 4.407(R)| FAST |TTCclkOut<1> | 3.404| | 6.949(F)| SLOW | 4.341(F)| FAST |TTCclkOut<1> | 3.404| TxFB_n<6> | 6.982(R)| SLOW | 4.378(R)| FAST |TTCclkOut<1> | 3.404| | 6.921(F)| SLOW | 4.313(F)| FAST |TTCclkOut<1> | 3.404| TxFB_p<4> | 6.957(R)| SLOW | 4.391(R)| FAST |TTCclkOut<1> | 3.404| | 6.895(F)| SLOW | 4.325(F)| FAST |TTCclkOut<1> | 3.404| TxFB_p<5> | 6.957(R)| SLOW | 4.391(R)| FAST |TTCclkOut<1> | 3.404| | 6.895(F)| SLOW | 4.325(F)| FAST |TTCclkOut<1> | 3.404| TxFB_p<6> | 6.928(R)| SLOW | 4.362(R)| FAST |TTCclkOut<1> | 3.404| | 6.867(F)| SLOW | 4.297(F)| FAST |TTCclkOut<1> | 3.404| ------------+-----------------+------------+-----------------+------------+------------------+--------+ Clock TTC_CLK_p<2> to Pad ------------+-----------------+------------+-----------------+------------+------------------+--------+ |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | ------------+-----------------+------------+-----------------+------------+------------------+--------+ TxFB_n<7> | 6.963(R)| SLOW | 4.359(R)| FAST |TTCclkOut<2> | 3.404| | 6.901(F)| SLOW | 4.293(F)| FAST |TTCclkOut<2> | 3.404| TxFB_n<8> | 6.963(R)| SLOW | 4.359(R)| FAST |TTCclkOut<2> | 3.404| | 6.901(F)| SLOW | 4.293(F)| FAST |TTCclkOut<2> | 3.404| TxFB_n<9> | 6.962(R)| SLOW | 4.358(R)| FAST |TTCclkOut<2> | 3.404| | 6.901(F)| SLOW | 4.293(F)| FAST |TTCclkOut<2> | 3.404| TxFB_p<7> | 6.909(R)| SLOW | 4.343(R)| FAST |TTCclkOut<2> | 3.404| | 6.847(F)| SLOW | 4.277(F)| FAST |TTCclkOut<2> | 3.404| TxFB_p<8> | 6.909(R)| SLOW | 4.343(R)| FAST |TTCclkOut<2> | 3.404| | 6.847(F)| SLOW | 4.277(F)| FAST |TTCclkOut<2> | 3.404| TxFB_p<9> | 6.908(R)| SLOW | 4.342(R)| FAST |TTCclkOut<2> | 3.404| | 6.847(F)| SLOW | 4.277(F)| FAST |TTCclkOut<2> | 3.404| ------------+-----------------+------------+-----------------+------------+------------------+--------+ Clock TTC_CLK_p<3> to Pad ------------+-----------------+------------+-----------------+------------+------------------+--------+ |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | ------------+-----------------+------------+-----------------+------------+------------------+--------+ TxFB_n<10> | 6.851(R)| SLOW | 4.247(R)| FAST |TTCclkOut<3> | 3.404| | 6.851(F)| SLOW | 4.253(F)| FAST |TTCclkOut<3> | 3.404| TxFB_n<11> | 6.851(R)| SLOW | 4.247(R)| FAST |TTCclkOut<3> | 3.404| | 6.851(F)| SLOW | 4.253(F)| FAST |TTCclkOut<3> | 3.404| TxFB_n<12> | 6.902(R)| SLOW | 4.298(R)| FAST |TTCclkOut<3> | 3.404| | 6.902(F)| SLOW | 4.304(F)| FAST |TTCclkOut<3> | 3.404| TxFB_p<10> | 6.797(R)| SLOW | 4.231(R)| FAST |TTCclkOut<3> | 3.404| | 6.797(F)| SLOW | 4.237(F)| FAST |TTCclkOut<3> | 3.404| TxFB_p<11> | 6.797(R)| SLOW | 4.231(R)| FAST |TTCclkOut<3> | 3.404| | 6.797(F)| SLOW | 4.237(F)| FAST |TTCclkOut<3> | 3.404| TxFB_p<12> | 6.848(R)| SLOW | 4.282(R)| FAST |TTCclkOut<3> | 3.404| | 6.848(F)| SLOW | 4.288(F)| FAST |TTCclkOut<3> | 3.404| ------------+-----------------+------------+-----------------+------------+------------------+--------+ Clock to Setup on destination clock FSIO_SCK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ FSIO_SCK | 6.940| | 8.159| 3.085| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock TTC_REFCLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ TTC_REFCLK | 15.201| 9.215| 8.660| | ---------------+---------+---------+---------+---------+ COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "RISING"; Worst Case Data Window 2.418; Ideal Clock Offset To Actual Clock -0.376; ------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | ------------------+------------+------------+------------+------------+---------+---------+-------------+ TTCdata_p | 7.333(R)| SLOW | -4.915(R)| FAST | 2.667| 1.915| 0.376| ------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary| 7.333| - | -4.915| - | 2.667| 1.915| | ------------------+------------+------------+------------+------------+---------+---------+-------------+ COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "FALLING"; Worst Case Data Window 2.403; Ideal Clock Offset To Actual Clock -0.309; ------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | ------------------+------------+------------+------------+------------+---------+---------+-------------+ TTCdata_p | -5.057(F)| SLOW | 7.460(F)| FAST | 2.607| 1.990| 0.309| ------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary| -5.057| - | 7.460| - | 2.607| 1.990| | ------------------+------------+------------+------------+------------+---------+---------+-------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<0>" "RISING"; Bus Skew: 0.106 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<1> | 7.076| SLOW | 4.472| FAST | 0.104| TxFB_n<2> | 7.026| SLOW | 4.422| FAST | 0.054| TxFB_n<3> | 7.078| SLOW | 4.474| FAST | 0.106| TxFB_p<1> | 7.022| SLOW | 4.456| FAST | 0.050| TxFB_p<2> | 6.972| SLOW | 4.406| FAST | 0.000| TxFB_p<3> | 7.024| SLOW | 4.458| FAST | 0.052| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<0>" "FALLING"; Bus Skew: 0.105 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<1> | 7.015| SLOW | 4.407| FAST | 0.104| TxFB_n<2> | 6.965| SLOW | 4.357| FAST | 0.054| TxFB_n<3> | 7.016| SLOW | 4.408| FAST | 0.105| TxFB_p<1> | 6.961| SLOW | 4.391| FAST | 0.050| TxFB_p<2> | 6.911| SLOW | 4.341| FAST | 0.000| TxFB_p<3> | 6.962| SLOW | 4.392| FAST | 0.051| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<1>" "RISING"; Bus Skew: 0.083 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<4> | 7.011| SLOW | 4.407| FAST | 0.083| TxFB_n<5> | 7.011| SLOW | 4.407| FAST | 0.083| TxFB_n<6> | 6.982| SLOW | 4.378| FAST | 0.054| TxFB_p<4> | 6.957| SLOW | 4.391| FAST | 0.029| TxFB_p<5> | 6.957| SLOW | 4.391| FAST | 0.029| TxFB_p<6> | 6.928| SLOW | 4.362| FAST | 0.000| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<1>" "FALLING"; Bus Skew: 0.082 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<4> | 6.949| SLOW | 4.341| FAST | 0.082| TxFB_n<5> | 6.949| SLOW | 4.341| FAST | 0.082| TxFB_n<6> | 6.921| SLOW | 4.313| FAST | 0.054| TxFB_p<4> | 6.895| SLOW | 4.325| FAST | 0.028| TxFB_p<5> | 6.895| SLOW | 4.325| FAST | 0.028| TxFB_p<6> | 6.867| SLOW | 4.297| FAST | 0.000| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<2>" "RISING"; Bus Skew: 0.055 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<7> | 6.963| SLOW | 4.359| FAST | 0.055| TxFB_n<8> | 6.963| SLOW | 4.359| FAST | 0.055| TxFB_n<9> | 6.962| SLOW | 4.358| FAST | 0.054| TxFB_p<7> | 6.909| SLOW | 4.343| FAST | 0.001| TxFB_p<8> | 6.909| SLOW | 4.343| FAST | 0.001| TxFB_p<9> | 6.908| SLOW | 4.342| FAST | 0.000| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<2>" "FALLING"; Bus Skew: 0.054 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<7> | 6.901| SLOW | 4.293| FAST | 0.054| TxFB_n<8> | 6.901| SLOW | 4.293| FAST | 0.054| TxFB_n<9> | 6.901| SLOW | 4.293| FAST | 0.054| TxFB_p<7> | 6.847| SLOW | 4.277| FAST | 0.000| TxFB_p<8> | 6.847| SLOW | 4.277| FAST | 0.000| TxFB_p<9> | 6.847| SLOW | 4.277| FAST | 0.000| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<3>" "RISING"; Bus Skew: 0.105 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<10> | 6.851| SLOW | 4.247| FAST | 0.054| TxFB_n<11> | 6.851| SLOW | 4.247| FAST | 0.054| TxFB_n<12> | 6.902| SLOW | 4.298| FAST | 0.105| TxFB_p<10> | 6.797| SLOW | 4.231| FAST | 0.000| TxFB_p<11> | 6.797| SLOW | 4.231| FAST | 0.000| TxFB_p<12> | 6.848| SLOW | 4.282| FAST | 0.051| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ OFFSET = OUT 7.2 ns AFTER COMP "TTC_CLK_p<3>" "FALLING"; Bus Skew: 0.105 ns; -----------------------------------------------+-------------+------------+-------------+------------+--------------+ |Max (slowest)| Process |Min (fastest)| Process | | PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ TxFB_n<10> | 6.851| SLOW | 4.253| FAST | 0.054| TxFB_n<11> | 6.851| SLOW | 4.253| FAST | 0.054| TxFB_n<12> | 6.902| SLOW | 4.304| FAST | 0.105| TxFB_p<10> | 6.797| SLOW | 4.237| FAST | 0.000| TxFB_p<11> | 6.797| SLOW | 4.237| FAST | 0.000| TxFB_p<12> | 6.848| SLOW | 4.288| FAST | 0.051| -----------------------------------------------+-------------+------------+-------------+------------+--------------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 99001 paths, 14 nets, and 27154 connections Design statistics: Minimum period: 24.772ns{1} (Maximum frequency: 40.368MHz) Maximum path delay from/to any node: 18.004ns Maximum net delay: 2.823ns Minimum input required time before clock: 7.393ns Minimum output required time after clock: 7.078ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Sat Dec 5 04:03:51 2020 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 576 MB