-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS 

  -- Component Declaration
COMPONENT dpbr_32_1
  PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    clkb : IN STD_LOGIC;
    enb : IN STD_LOGIC;
    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;

          SIGNAL clk :  std_logic := '0';
          SIGNAL wbuf_ra :  std_logic_vector(12 downto 0) := (others =>'0');
          SIGNAL wbuf_wa :  std_logic_vector(7 downto 0) := (others =>'0');
          SIGNAL doa :  std_logic_vector(0 downto 0) := (others =>'0');
          SIGNAL web :  std_logic_vector(0 downto 0) := (others =>'0');
          SIGNAL w_data :  std_logic_vector(31 downto 0) := (others =>'0');
          SIGNAL flash_wdata :  std_logic_vector(31 downto 0);
          SIGNAL cntr :  std_logic_vector(7 downto 0) := (others =>'0');
          

  BEGIN

  -- Component Instantiation
i_wbuf : dpbr_32_1
  PORT MAP (
    clka => clk,
    ena => '1',
    wea => "0",
    addra => wbuf_ra,
    dina => (others => '0'),
    douta => doa,
    clkb => clk,
    enb => '1',
    web => web,
    addrb => wbuf_wa,
    dinb => w_data,
    doutb => flash_wdata
  );

clk <= not clk after 5 ns;
wbuf_wa <= x"0" & cntr(3 downto 0);
w_data(7 downto 0) <= cntr;
web(0) <= cntr(4);
process(clk)
begin
	if(clk'event and clk = '1')then
		cntr <= cntr + 1;
	end if;
end process;
  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        wait for 100 ns; -- wait until global set/reset completes

        -- Add user defined stimulus here

        wait; -- will wait forever
     END PROCESS tb;
  --  End Test Bench 

  END;