Instructions about amc13xg teststand firmware
First, put a TTC loop back SFP module into the bottom SFP cage.
Then, put three 10G(8G) SFP loopback module into the top three SFP cages.
connect the digilent JTAG cable to the AMC13 JTAG header. VDD side should be up.
turn on the fan and then the 12V power supply.

1. log in as daq to computer driving the JTAG cable
2. double click iMpact icon
3. open the project and program spartan chip first and then the Kintex chip.
4. in T2
check that the reg0x7(ErrCnt) should be 0, at least not changing.
	       reg0x4(TxFB) and reg0x5(RxFB) should be changing.
	       bit0 of reg0x6(T1_ready) should be 1.
5. in T1
check that	reg0x1f(TTCcntr) is changing(if not, TxFB and RxFB in step 7 will not change)
set bit 13 of reg 0xf to 1 to enable memory test.
		reg0xa(mem_sta) is changing(otherwise, there's a memory error detected)
6. T1 register 0xf controls setting of GTX link tests
	change values of bit[2:0]AMC_RxSel, bit[5:3]AMC_TxSel. Legal values are
	1, 2, 3 and 4. When AMC_TxSel = AMC_RxSel, all error counters should not change.
	When otherwise, all error counters should be changing.
	error counter for AMC1 is reg 0x10 and reg 0x11 for AMC2... reg 0x1b for AMC12
7. Do the same for bit[8:6]SFP_RxSel and bit[11:9]SFP_TxSel and check SFP0 error counter 0x1c
    and reg 0x1d for SFP1 and reg 0x1e for SFP2
8. use a scope to look at signals at the terminals of resistors on the test stand. you should
    see 40MHz LVDS level signals on them.

Turn off the 12V power supply before you remove it from the test stand.

This procedure tests the memory, front panel SFP ports and AMC backplane links and GTP link
between T1 and T2. TTC clock outputs are also tested. 

related mempry map

T2:
0x4	read only	bit 11-0	T2 to AMC data
0x5	read only	bit 11-0	AMC to T2 data
0x6	read only	bit 0		T1 ready
0x7	read only	bit 5-0		T2 AMC link error counter

T1:
0xa	read only	bit 31		if 1, fatal memory error
			bit 30-0	memory data being read(should change all the time)
0xf	read/write	bit 31-14	not used
			bit 13		if 1, memory test enabled		
			bit 12		if 1, reset counters		
			bit 11-9	SFPtxprbssel(legal values are 1, 2, 3 and 4)		
			bit 8-6		SFPrxprbssel(legal values are 1, 2, 3 and 4)		
			bit 5-3		AMCtxprbssel(legal values are 1, 2, 3 and 4)		
			bit 2-0		AMCrxprbssel(legal values are 1, 2, 3 and 4)		
0x10	read only	bit 15-0	AMC1 error counter
0x11	read only	bit 15-0	AMC2 error counter
0x12	read only	bit 15-0	AMC3 error counter
0x13	read only	bit 15-0	AMC4 error counter
0x14	read only	bit 15-0	AMC5 error counter
0x15	read only	bit 15-0	AMC6 error counter
0x16	read only	bit 15-0	AMC7 error counter
0x17	read only	bit 15-0	AMC8 error counter
0x18	read only	bit 15-0	AMC9 error counter
0x19	read only	bit 15-0	AMC10 error counter
0x1a	read only	bit 15-0	AMC11 error counter
0x1b	read only	bit 15-0	AMC12 error counter
0x1c	read only	bit 15-0	SFP0 error counter
0x1d	read only	bit 15-0	SFP1 error counter
0x1e	read only	bit 15-0	SFP2 error counter
0x1f	read only	bit 15-0	TTC counter(if TTC clock is there, it counts)