| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
5,172 |
54,576 |
9% |
|
| Number used as Flip Flops |
5,169 |
|
|
|
| Number used as Latches |
3 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
4,398 |
27,288 |
16% |
|
| Number used as logic |
4,141 |
27,288 |
15% |
|
| Number using O6 output only |
2,694 |
|
|
|
| Number using O5 output only |
216 |
|
|
|
| Number using O5 and O6 |
1,231 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
28 |
6,408 |
1% |
|
| Number used as Dual Port RAM |
0 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
28 |
|
|
|
| Number using O6 output only |
16 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
12 |
|
|
|
| Number used exclusively as route-thrus |
229 |
|
|
|
| Number with same-slice register load |
210 |
|
|
|
| Number with same-slice carry load |
19 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
1,731 |
6,822 |
25% |
|
| Number of MUXCYs used |
636 |
13,644 |
4% |
|
| Number of LUT Flip Flop pairs used |
5,453 |
|
|
|
| Number with an unused Flip Flop |
1,240 |
5,453 |
22% |
|
| Number with an unused LUT |
1,055 |
5,453 |
19% |
|
| Number of fully used LUT-FF pairs |
3,158 |
5,453 |
57% |
|
| Number of unique control sets |
158 |
|
|
|
Number of slice register sites lost
to control set restrictions |
452 |
54,576 |
1% |
|
| Number of bonded IOBs |
104 |
296 |
35% |
|
| Number of LOCed IOBs |
77 |
104 |
74% |
|
| IOB Flip Flops |
19 |
|
|
|
| IOB Master Pads |
13 |
|
|
|
| IOB Slave Pads |
13 |
|
|
|
| Number of bonded IPADs |
6 |
16 |
37% |
|
| Number of LOCed IPADs |
6 |
6 |
100% |
|
| Number of bonded OPADs |
4 |
8 |
50% |
|
| Number of LOCed OPADs |
4 |
4 |
100% |
|
| Number of RAMB16BWERs |
37 |
116 |
31% |
|
| Number of RAMB8BWERs |
0 |
232 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
2 |
32 |
6% |
|
| Number used as BUFIO2s |
2 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2FBs |
1 |
|
|
|
| Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
| Number of BUFG/BUFGMUXs |
7 |
16 |
43% |
|
| Number used as BUFGs |
7 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
2 |
8 |
25% |
|
| Number used as DCMs |
2 |
|
|
|
| Number used as DCM_CLKGENs |
0 |
|
|
|
| Number of ILOGIC2/ISERDES2s |
16 |
376 |
4% |
|
| Number used as ILOGIC2s |
16 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
376 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
3 |
376 |
1% |
|
| Number used as OLOGIC2s |
3 |
|
|
|
| Number used as OSERDES2s |
0 |
|
|
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHs |
0 |
256 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
0 |
58 |
0% |
|
| Number of GTPA1_DUALs |
1 |
2 |
50% |
|
| Number of ICAPs |
1 |
1 |
100% |
|
| Number of MCBs |
0 |
2 |
0% |
|
| Number of PCIE_A1s |
0 |
1 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
0 |
4 |
0% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Number of RPM macros |
1 |
|
|
|
| Average Fanout of Non-Clock Nets |
3.11 |
|
|
|