Release 14.7 Map P.20131013 (lin64) Xilinx Map Application Log File for Design 'AMC13_T2' Design Information ------------------ Command Line : map -intstyle ise -p xc6slx45t-fgg484-2 -w -logic_opt on -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr b -lc off -power off -o AMC13_T2_map.ncd AMC13_T2.ngd AMC13_T2.pcf Target Device : xc6slx45t Target Package : fgg484 Target Speed : -2 Mapper Version : spartan6 -- $Revision: 1.55 $ Mapped Date : Tue Sep 22 23:37:48 2020 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc6slx45t' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Mapping design into LUTs... WARNING:MapLib:701 - Signal TTC_CLK_p<0> connected to top level port TTC_CLK_p<0> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_n<0> connected to top level port TTC_CLK_n<0> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_p<1> connected to top level port TTC_CLK_p<1> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_n<1> connected to top level port TTC_CLK_n<1> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_p<2> connected to top level port TTC_CLK_p<2> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_n<2> connected to top level port TTC_CLK_n<2> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_p<3> connected to top level port TTC_CLK_p<3> has been removed. WARNING:MapLib:701 - Signal TTC_CLK_n<3> connected to top level port TTC_CLK_n<3> has been removed. WARNING:MapLib:41 - All members of TNM group "TTCclk_p" have been optimized out of the design. WARNING:MapLib:50 - The period specification "TS_TTCclk_p" has been discarded because the group "TTCclk_p" has been optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 10000 pS AFTER ipb_clk" has been discarded because the referenced clock pad net (ipb_clk) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<0> RISING" has been discarded because the referenced clock pad net (TTC_CLK_p<0>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<0> FALLING" has been discarded because the referenced clock pad net (TTC_CLK_p<0>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<1> RISING" has been discarded because the referenced clock pad net (TTC_CLK_p<1>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<1> FALLING" has been discarded because the referenced clock pad net (TTC_CLK_p<1>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<2> RISING" has been discarded because the referenced clock pad net (TTC_CLK_p<2>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<2> FALLING" has been discarded because the referenced clock pad net (TTC_CLK_p<2>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<3> RISING" has been discarded because the referenced clock pad net (TTC_CLK_p<3>) was optimized away. WARNING:MapLib:53 - The offset specification "OFFSET=OUT 7200 pS AFTER TTC_CLK_p<3> FALLING" has been discarded because the referenced clock pad net (TTC_CLK_p<3>) was optimized away. Running directed packing... Running delay-based LUT packing... Updating timing models... WARNING:Timing:3223 - Timing constraint TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP "TO_TTC_data_1_LD" TS_TTCclk_dcm DATAPATHONLY ignored during timing analysis. INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 52 secs Total CPU time at the beginning of Placer: 49 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:7f9f2efb) REAL time: 58 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:7f9f2efb) REAL time: 1 mins Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:88da4e7b) REAL time: 1 mins Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:cf2379d5) REAL time: 2 mins 35 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:cf2379d5) REAL time: 2 mins 35 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:cf2379d5) REAL time: 2 mins 35 secs Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization (Checksum:6261b1dd) REAL time: 2 mins 36 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:6261b1dd) REAL time: 2 mins 36 secs Phase 9.8 Global Placement ........................ ............................................................ ....................................................................................................... ................................................................. .......................... Phase 9.8 Global Placement (Checksum:c534017c) REAL time: 6 mins 41 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:c534017c) REAL time: 6 mins 42 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:e3dc6bc0) REAL time: 7 mins 14 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:e3dc6bc0) REAL time: 7 mins 15 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:99396842) REAL time: 7 mins 16 secs Total REAL time to Placer completion: 8 mins 1 secs Total CPU time to Placer completion: 7 mins 44 secs Running physical synthesis... Physical synthesis completed. Running post-placement packing... Writing output files... WARNING:PhysDesignRules:372 - Gated clock. Clock net GbEGTPreset is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net TTC_lock_inv is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net sysclk_dcm_locked_reprogV6_OR_86_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp FLASH_S_PULLUP is set but the tri state is not configured. WARNING:PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp FLASH_C_PULLDOWN is set but the tri state is not configured. WARNING:PhysDesignRules:1269 - Issue with pin connections and/or configuration on block::. The Q1 output pin of IFF is not used. Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 26 Slice Logic Utilization: Number of Slice Registers: 5,172 out of 54,576 9% Number used as Flip Flops: 5,169 Number used as Latches: 3 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 4,398 out of 27,288 16% Number used as logic: 4,141 out of 27,288 15% Number using O6 output only: 2,694 Number using O5 output only: 216 Number using O5 and O6: 1,231 Number used as ROM: 0 Number used as Memory: 28 out of 6,408 1% Number used as Dual Port RAM: 0 Number used as Single Port RAM: 0 Number used as Shift Register: 28 Number using O6 output only: 16 Number using O5 output only: 0 Number using O5 and O6: 12 Number used exclusively as route-thrus: 229 Number with same-slice register load: 210 Number with same-slice carry load: 19 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 1,731 out of 6,822 25% Number of MUXCYs used: 636 out of 13,644 4% Number of LUT Flip Flop pairs used: 5,453 Number with an unused Flip Flop: 1,240 out of 5,453 22% Number with an unused LUT: 1,055 out of 5,453 19% Number of fully used LUT-FF pairs: 3,158 out of 5,453 57% Number of unique control sets: 158 Number of slice register sites lost to control set restrictions: 452 out of 54,576 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 104 out of 296 35% Number of LOCed IOBs: 77 out of 104 74% IOB Flip Flops: 19 IOB Master Pads: 13 IOB Slave Pads: 13 Number of bonded IPADs: 6 out of 16 37% Number of LOCed IPADs: 6 out of 6 100% Number of bonded OPADs: 4 out of 8 50% Number of LOCed OPADs: 4 out of 4 100% Specific Feature Utilization: Number of RAMB16BWERs: 37 out of 116 31% Number of RAMB8BWERs: 0 out of 232 0% Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% Number used as BUFIO2s: 2 Number used as BUFIO2_2CLKs: 0 Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3% Number used as BUFIO2FBs: 1 Number used as BUFIO2FB_2CLKs: 0 Number of BUFG/BUFGMUXs: 7 out of 16 43% Number used as BUFGs: 7 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 2 out of 8 25% Number used as DCMs: 2 Number used as DCM_CLKGENs: 0 Number of ILOGIC2/ISERDES2s: 16 out of 376 4% Number used as ILOGIC2s: 16 Number used as ISERDES2s: 0 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0% Number of OLOGIC2/OSERDES2s: 3 out of 376 1% Number used as OLOGIC2s: 3 Number used as OSERDES2s: 0 Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 256 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 58 0% Number of GTPA1_DUALs: 1 out of 2 50% Number of ICAPs: 1 out of 1 100% Number of MCBs: 0 out of 2 0% Number of PCIE_A1s: 0 out of 1 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 4 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Number of RPM macros: 1 Average Fanout of Non-Clock Nets: 3.11 Peak Memory Usage: 1067 MB Total REAL time to MAP completion: 8 mins 24 secs Total CPU time to MAP completion (all processors): 8 mins 6 secs Mapping completed. See MAP report file "AMC13_T2_map.mrp" for details.