-------------------------------------------------------------------------------- Release 14.7 Trace (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml AMC13_T2.twx AMC13_T2.ncd -o AMC13_T2.twr AMC13_T2.pcf -ucf AMC13_T2.ucf Design file: AMC13_T2.ncd Physical constraint file: AMC13_T2.pcf Device,package,speed: xc6slx45t,fgg484,C,-2 (PRODUCTION 1.23 2013-10-13) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- WARNING:Timing:3223 - Timing constraint TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP "TO_TTC_data_1_LD" TS_TTCclk_dcm DATAPATHONLY; ignored during timing analysis. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: NET "RxFB_in<1>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.251ns. -------------------------------------------------------------------------------- Slack: 0.749ns RxFB_in<1> Report: 2.251ns delay meets 3.000ns timing constraint by 0.749ns From To Delay(ns) ILOGIC_X26Y3.FABRICOUT SLICE_X31Y4.D3 2.251 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<2>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.798ns. -------------------------------------------------------------------------------- Slack: 1.202ns RxFB_in<2> Report: 1.798ns delay meets 3.000ns timing constraint by 1.202ns From To Delay(ns) ILOGIC_X24Y1.FABRICOUT SLICE_X31Y4.B6 1.798 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<3>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.434ns. -------------------------------------------------------------------------------- Slack: 1.566ns RxFB_in<3> Report: 1.434ns delay meets 3.000ns timing constraint by 1.566ns From To Delay(ns) ILOGIC_X18Y1.FABRICOUT SLICE_X31Y4.B1 1.434 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<4>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.296ns. -------------------------------------------------------------------------------- Slack: 1.704ns RxFB_in<4> Report: 1.296ns delay meets 3.000ns timing constraint by 1.704ns From To Delay(ns) ILOGIC_X16Y1.FABRICOUT SLICE_X31Y4.C3 1.296 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<5>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.731ns. -------------------------------------------------------------------------------- Slack: 1.269ns RxFB_in<5> Report: 1.731ns delay meets 3.000ns timing constraint by 1.269ns From To Delay(ns) ILOGIC_X24Y3.FABRICOUT SLICE_X30Y4.A4 1.731 ILOGIC_X24Y3.FABRICOUT SLICE_X31Y4.C6 1.565 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<6>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.225ns. -------------------------------------------------------------------------------- Slack: 1.775ns RxFB_in<6> Report: 1.225ns delay meets 3.000ns timing constraint by 1.775ns From To Delay(ns) ILOGIC_X17Y1.FABRICOUT SLICE_X30Y4.A3 1.225 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<7>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.290ns. -------------------------------------------------------------------------------- Slack: 1.710ns RxFB_in<7> Report: 1.290ns delay meets 3.000ns timing constraint by 1.710ns From To Delay(ns) ILOGIC_X11Y1.FABRICOUT SLICE_X28Y4.D1 1.290 ILOGIC_X11Y1.FABRICOUT SLICE_X30Y4.A6 1.187 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<8>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.165ns. -------------------------------------------------------------------------------- Slack: 1.835ns RxFB_in<8> Report: 1.165ns delay meets 3.000ns timing constraint by 1.835ns From To Delay(ns) ILOGIC_X8Y3.FABRICOUT SLICE_X28Y4.D6 1.165 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<9>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.468ns. -------------------------------------------------------------------------------- Slack: 1.532ns RxFB_in<9> Report: 1.468ns delay meets 3.000ns timing constraint by 1.532ns From To Delay(ns) ILOGIC_X11Y3.FABRICOUT SLICE_X22Y4.D2 0.972 ILOGIC_X11Y3.FABRICOUT SLICE_X28Y4.D2 1.468 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<10>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 1.498ns. -------------------------------------------------------------------------------- Slack: 1.502ns RxFB_in<10> Report: 1.498ns delay meets 3.000ns timing constraint by 1.502ns From To Delay(ns) ILOGIC_X4Y3.FABRICOUT SLICE_X22Y4.D3 1.498 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<11>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.327ns. -------------------------------------------------------------------------------- Slack: 0.673ns RxFB_in<11> Report: 2.327ns delay meets 3.000ns timing constraint by 0.673ns From To Delay(ns) ILOGIC_X3Y3.FABRICOUT SLICE_X22Y4.D6 1.493 ILOGIC_X3Y3.FABRICOUT SLICE_X31Y4.D5 2.327 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "RxFB_in<12>" MAXDELAY = 3 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 2.322ns. -------------------------------------------------------------------------------- Slack: 0.678ns RxFB_in<12> Report: 2.322ns delay meets 3.000ns timing constraint by 0.678ns From To Delay(ns) ILOGIC_X2Y1.FABRICOUT SLICE_X31Y4.D6 2.322 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_REFCLK_P = PERIOD TIMEGRP "REFCLK_P" 8 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 3.703ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_REFCLK_P = PERIOD TIMEGRP "REFCLK_P" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 4.297ns (period - min period limit) Period: 8.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_CLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK00 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK00 Location pin: GTPA1_DUAL_X0Y0.CLK00 Clock network: i_GTP_if/REFCLK -------------------------------------------------------------------------------- Slack: 4.297ns (period - min period limit) Period: 8.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_CLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK01 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/CLK01 Location pin: GTPA1_DUAL_X0Y0.CLK01 Clock network: i_GTP_if/REFCLK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 250 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 3734 paths analyzed, 658 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 15.926ns. -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_out_3 (SLICE_X2Y69.A3), 29 paths -------------------------------------------------------------------------------- Slack (setup path): 117.037ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_3 (FF) Requirement: 125.000ns Data Path Delay: 7.916ns (Levels of Logic = 3) Clock Path Skew: -0.012ns (0.290 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X24Y80.C3 net (fanout=13) 2.988 i_SPI_if/STATUS_5_2 SLICE_X24Y80.C Tilo 0.235 i_ipbus/my_ip_addr_udp<27> i_SPI_if/Mmux_IPADDR_i201 SLICE_X2Y77.B1 net (fanout=2) 2.058 ipaddr<27> SLICE_X2Y77.BMUX Topbb 0.444 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<3>1 i_SPI_if/mux3_5 i_SPI_if/mux3_3_f7 i_SPI_if/mux3_2_f8 SLICE_X2Y69.A3 net (fanout=1) 1.327 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<3>1 SLICE_X2Y69.CLK Tas 0.339 i_SPI_if/sr_out<4> i_SPI_if/sr_out_3_glue_set i_SPI_if/sr_out_3 ------------------------------------------------- --------------------------- Total 7.916ns (1.543ns logic, 6.373ns route) (19.5% logic, 80.5% route) -------------------------------------------------------------------------------- Slack (setup path): 118.036ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/SPI_IPADDR_27 (FF) Destination: i_SPI_if/sr_out_3 (FF) Requirement: 125.000ns Data Path Delay: 6.907ns (Levels of Logic = 3) Clock Path Skew: -0.022ns (0.290 - 0.312) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/SPI_IPADDR_27 to i_SPI_if/sr_out_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y77.DMUX Tshcko 0.535 i_SPI_if/SPI_IPADDR<3> i_SPI_if/SPI_IPADDR_27 SLICE_X24Y80.C1 net (fanout=4) 1.969 i_SPI_if/SPI_IPADDR<27> SLICE_X24Y80.C Tilo 0.235 i_ipbus/my_ip_addr_udp<27> i_SPI_if/Mmux_IPADDR_i201 SLICE_X2Y77.B1 net (fanout=2) 2.058 ipaddr<27> SLICE_X2Y77.BMUX Topbb 0.444 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<3>1 i_SPI_if/mux3_5 i_SPI_if/mux3_3_f7 i_SPI_if/mux3_2_f8 SLICE_X2Y69.A3 net (fanout=1) 1.327 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<3>1 SLICE_X2Y69.CLK Tas 0.339 i_SPI_if/sr_out<4> i_SPI_if/sr_out_3_glue_set i_SPI_if/sr_out_3 ------------------------------------------------- --------------------------- Total 6.907ns (1.553ns logic, 5.354ns route) (22.5% logic, 77.5% route) -------------------------------------------------------------------------------- Slack (setup path): 119.425ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_3 (FF) Requirement: 125.000ns Data Path Delay: 5.528ns (Levels of Logic = 3) Clock Path Skew: -0.012ns (0.290 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X8Y77.A3 net (fanout=13) 1.435 i_SPI_if/STATUS_5_2 SLICE_X8Y77.A Tilo 0.235 i_ipbus/my_ip_addr_udp<4> i_SPI_if/Mmux_IPADDR_i261 SLICE_X2Y77.A5 net (fanout=2) 1.211 ipaddr<3> SLICE_X2Y77.BMUX Topab 0.456 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<3>1 i_SPI_if/mux3_4 i_SPI_if/mux3_3_f7 i_SPI_if/mux3_2_f8 SLICE_X2Y69.A3 net (fanout=1) 1.327 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<3>1 SLICE_X2Y69.CLK Tas 0.339 i_SPI_if/sr_out<4> i_SPI_if/sr_out_3_glue_set i_SPI_if/sr_out_3 ------------------------------------------------- --------------------------- Total 5.528ns (1.555ns logic, 3.973ns route) (28.1% logic, 71.9% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_out_2 (SLICE_X0Y68.D2), 30 paths -------------------------------------------------------------------------------- Slack (setup path): 117.291ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_2 (FF) Requirement: 125.000ns Data Path Delay: 7.666ns (Levels of Logic = 3) Clock Path Skew: -0.008ns (0.294 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X24Y80.A6 net (fanout=13) 2.743 i_SPI_if/STATUS_5_2 SLICE_X24Y80.A Tilo 0.235 i_ipbus/my_ip_addr_udp<27> i_SPI_if/Mmux_IPADDR_i191 SLICE_X2Y78.B5 net (fanout=2) 1.906 ipaddr<26> SLICE_X2Y78.BMUX Topbb 0.444 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<2>1 i_SPI_if/mux2_5 i_SPI_if/mux2_3_f7 i_SPI_if/mux2_2_f8 SLICE_X0Y68.D2 net (fanout=1) 1.464 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<2>1 SLICE_X0Y68.CLK Tas 0.349 i_SPI_if/sr_out<2> i_SPI_if/sr_out_2_glue_set i_SPI_if/sr_out_2 ------------------------------------------------- --------------------------- Total 7.666ns (1.553ns logic, 6.113ns route) (20.3% logic, 79.7% route) -------------------------------------------------------------------------------- Slack (setup path): 118.078ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/SPI_IPADDR_26 (FF) Destination: i_SPI_if/sr_out_2 (FF) Requirement: 125.000ns Data Path Delay: 6.869ns (Levels of Logic = 3) Clock Path Skew: -0.018ns (0.294 - 0.312) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/SPI_IPADDR_26 to i_SPI_if/sr_out_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y77.CMUX Tshcko 0.535 i_SPI_if/SPI_IPADDR<3> i_SPI_if/SPI_IPADDR_26 SLICE_X24Y80.A2 net (fanout=4) 1.936 i_SPI_if/SPI_IPADDR<26> SLICE_X24Y80.A Tilo 0.235 i_ipbus/my_ip_addr_udp<27> i_SPI_if/Mmux_IPADDR_i191 SLICE_X2Y78.B5 net (fanout=2) 1.906 ipaddr<26> SLICE_X2Y78.BMUX Topbb 0.444 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<2>1 i_SPI_if/mux2_5 i_SPI_if/mux2_3_f7 i_SPI_if/mux2_2_f8 SLICE_X0Y68.D2 net (fanout=1) 1.464 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<2>1 SLICE_X0Y68.CLK Tas 0.349 i_SPI_if/sr_out<2> i_SPI_if/sr_out_2_glue_set i_SPI_if/sr_out_2 ------------------------------------------------- --------------------------- Total 6.869ns (1.563ns logic, 5.306ns route) (22.8% logic, 77.2% route) -------------------------------------------------------------------------------- Slack (setup path): 118.663ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_2 (FF) Requirement: 125.000ns Data Path Delay: 6.294ns (Levels of Logic = 3) Clock Path Skew: -0.008ns (0.294 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X10Y79.C4 net (fanout=13) 1.829 i_SPI_if/STATUS_5_2 SLICE_X10Y79.C Tilo 0.255 i_ipbus/my_ip_addr_udp<10> i_SPI_if/Mmux_IPADDR_i21 SLICE_X2Y78.A2 net (fanout=2) 1.416 ipaddr<10> SLICE_X2Y78.BMUX Topab 0.456 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<2>1 i_SPI_if/mux2_4 i_SPI_if/mux2_3_f7 i_SPI_if/mux2_2_f8 SLICE_X0Y68.D2 net (fanout=1) 1.464 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<2>1 SLICE_X0Y68.CLK Tas 0.349 i_SPI_if/sr_out<2> i_SPI_if/sr_out_2_glue_set i_SPI_if/sr_out_2 ------------------------------------------------- --------------------------- Total 6.294ns (1.585ns logic, 4.709ns route) (25.2% logic, 74.8% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/sr_out_1 (SLICE_X0Y68.C3), 30 paths -------------------------------------------------------------------------------- Slack (setup path): 118.727ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_1 (FF) Requirement: 125.000ns Data Path Delay: 6.230ns (Levels of Logic = 3) Clock Path Skew: -0.008ns (0.294 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X15Y77.C3 net (fanout=13) 2.129 i_SPI_if/STATUS_5_2 SLICE_X15Y77.C Tilo 0.259 i_ipbus/my_ip_addr_udp<25> i_SPI_if/Mmux_IPADDR_i181 SLICE_X0Y77.B1 net (fanout=2) 1.454 ipaddr<25> SLICE_X0Y77.BMUX Topbb 0.423 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<1>1 i_SPI_if/mux1_5 i_SPI_if/mux1_3_f7 i_SPI_if/mux1_2_f8 SLICE_X0Y68.C3 net (fanout=1) 1.091 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<1>1 SLICE_X0Y68.CLK Tas 0.349 i_SPI_if/sr_out<2> i_SPI_if/sr_out_1_glue_set i_SPI_if/sr_out_1 ------------------------------------------------- --------------------------- Total 6.230ns (1.556ns logic, 4.674ns route) (25.0% logic, 75.0% route) -------------------------------------------------------------------------------- Slack (setup path): 118.926ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_1 (FF) Requirement: 125.000ns Data Path Delay: 6.031ns (Levels of Logic = 3) Clock Path Skew: -0.008ns (0.294 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X12Y78.C3 net (fanout=13) 1.909 i_SPI_if/STATUS_5_2 SLICE_X12Y78.CMUX Tilo 0.298 i_ipbus/my_ip_addr_udp<2> i_SPI_if/Mmux_IPADDR_i121 SLICE_X0Y77.A5 net (fanout=2) 1.421 ipaddr<1> SLICE_X0Y77.BMUX Topab 0.438 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<1>1 i_SPI_if/mux1_4 i_SPI_if/mux1_3_f7 i_SPI_if/mux1_2_f8 SLICE_X0Y68.C3 net (fanout=1) 1.091 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<1>1 SLICE_X0Y68.CLK Tas 0.349 i_SPI_if/sr_out<2> i_SPI_if/sr_out_1_glue_set i_SPI_if/sr_out_1 ------------------------------------------------- --------------------------- Total 6.031ns (1.610ns logic, 4.421ns route) (26.7% logic, 73.3% route) -------------------------------------------------------------------------------- Slack (setup path): 118.972ns (requirement - (data path - clock path skew + uncertainty)) Source: i_SPI_if/STATUS_5_2 (FF) Destination: i_SPI_if/sr_out_1 (FF) Requirement: 125.000ns Data Path Delay: 5.985ns (Levels of Logic = 3) Clock Path Skew: -0.008ns (0.294 - 0.302) Source Clock: S6_SCK rising at 0.000ns Destination Clock: S6_SCK falling at 125.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_SPI_if/STATUS_5_2 to i_SPI_if/sr_out_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y72.BQ Tcko 0.525 i_SPI_if/STATUS_5_2 i_SPI_if/STATUS_5_2 SLICE_X10Y79.A2 net (fanout=13) 2.011 i_SPI_if/STATUS_5_2 SLICE_X10Y79.A Tilo 0.254 i_ipbus/my_ip_addr_udp<10> i_SPI_if/Mmux_IPADDR_i321 SLICE_X0Y77.A3 net (fanout=2) 1.317 ipaddr<9> SLICE_X0Y77.BMUX Topab 0.438 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<1>1 i_SPI_if/mux1_4 i_SPI_if/mux1_3_f7 i_SPI_if/mux1_2_f8 SLICE_X0Y68.C3 net (fanout=1) 1.091 i_SPI_if/addr[3]_GND_14_o_wide_mux_55_OUT<1>1 SLICE_X0Y68.CLK Tas 0.349 i_SPI_if/sr_out<2> i_SPI_if/sr_out_1_glue_set i_SPI_if/sr_out_1 ------------------------------------------------- --------------------------- Total 5.985ns (1.566ns logic, 4.419ns route) (26.2% logic, 73.8% route) -------------------------------------------------------------------------------- Hold Paths: TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 250 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_SPI_if/NET_MASK_15 (SLICE_X0Y75.D6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.413ns (requirement - (clock path skew + uncertainty - data path)) Source: i_SPI_if/NET_MASK_15 (FF) Destination: i_SPI_if/NET_MASK_15 (FF) Requirement: 0.000ns Data Path Delay: 0.413ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: S6_SCK rising at 250.000ns Destination Clock: S6_SCK rising at 250.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_SPI_if/NET_MASK_15 to i_SPI_if/NET_MASK_15 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y75.DQ Tcko 0.200 i_SPI_if/NET_MASK<15> i_SPI_if/NET_MASK_15 SLICE_X0Y75.D6 net (fanout=2) 0.023 i_SPI_if/NET_MASK<15> SLICE_X0Y75.CLK Tah (-Th) -0.190 i_SPI_if/NET_MASK<15> i_SPI_if/Mmux__n034471 i_SPI_if/NET_MASK_15 ------------------------------------------------- --------------------------- Total 0.413ns (0.390ns logic, 0.023ns route) (94.4% logic, 5.6% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/NET_MASK_12 (SLICE_X0Y75.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.415ns (requirement - (clock path skew + uncertainty - data path)) Source: i_SPI_if/NET_MASK_12 (FF) Destination: i_SPI_if/NET_MASK_12 (FF) Requirement: 0.000ns Data Path Delay: 0.415ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: S6_SCK rising at 250.000ns Destination Clock: S6_SCK rising at 250.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_SPI_if/NET_MASK_12 to i_SPI_if/NET_MASK_12 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y75.AQ Tcko 0.200 i_SPI_if/NET_MASK<15> i_SPI_if/NET_MASK_12 SLICE_X0Y75.A6 net (fanout=2) 0.025 i_SPI_if/NET_MASK<12> SLICE_X0Y75.CLK Tah (-Th) -0.190 i_SPI_if/NET_MASK<15> i_SPI_if/Mmux__n034441 i_SPI_if/NET_MASK_12 ------------------------------------------------- --------------------------- Total 0.415ns (0.390ns logic, 0.025ns route) (94.0% logic, 6.0% route) -------------------------------------------------------------------------------- Paths for end point i_SPI_if/NET_MASK_23 (SLICE_X4Y74.D6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.415ns (requirement - (clock path skew + uncertainty - data path)) Source: i_SPI_if/NET_MASK_23 (FF) Destination: i_SPI_if/NET_MASK_23 (FF) Requirement: 0.000ns Data Path Delay: 0.415ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: S6_SCK rising at 250.000ns Destination Clock: S6_SCK rising at 250.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_SPI_if/NET_MASK_23 to i_SPI_if/NET_MASK_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y74.DQ Tcko 0.200 i_SPI_if/NET_MASK<23> i_SPI_if/NET_MASK_23 SLICE_X4Y74.D6 net (fanout=2) 0.025 i_SPI_if/NET_MASK<23> SLICE_X4Y74.CLK Tah (-Th) -0.190 i_SPI_if/NET_MASK<23> i_SPI_if/Mmux__n0344161 i_SPI_if/NET_MASK_23 ------------------------------------------------- --------------------------- Total 0.415ns (0.390ns logic, 0.025ns route) (94.0% logic, 6.0% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 250 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 247.334ns (period - min period limit) Period: 250.000ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: i_S6_SCK/I0 Logical resource: i_S6_SCK/I0 Location pin: BUFGMUX_X3Y15.I0 Clock network: T1_SCK_OBUF -------------------------------------------------------------------------------- Slack: 248.134ns (period - min period limit) Period: 250.000ns Min period limit: 1.866ns (535.906MHz) (Tickper) Physical resource: T1_MOSI_OBUF/CLK0 Logical resource: i_SPI_if/sr_in_0/CLK0 Location pin: ILOGIC_X0Y68.CLK0 Clock network: S6_SCK -------------------------------------------------------------------------------- Slack: 249.520ns (period - min period limit) Period: 250.000ns Min period limit: 0.480ns (2083.333MHz) (Tcp) Physical resource: S6_MISO/CLK Logical resource: i_SPI_if/sr_out_7/CK Location pin: SLICE_X2Y67.CLK Clock network: S6_SCK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTC_REFCLK = PERIOD TIMEGRP "TTC_REFCLK" 24.9 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 16.000ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTC_REFCLK = PERIOD TIMEGRP "TTC_REFCLK" 24.9 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 8.900ns (period - (min low pulse limit / (low pulse / period))) Period: 24.900ns Low pulse: 12.450ns Low pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50) Physical resource: i_DCM_TTCclk/CLKIN Logical resource: i_DCM_TTCclk/CLKIN Location pin: DCM_X0Y6.CLKIN Clock network: i_DCM_TTCclk_ML_NEW_DIVCLK -------------------------------------------------------------------------------- Slack: 8.900ns (period - (min high pulse limit / (high pulse / period))) Period: 24.900ns High pulse: 12.450ns High pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50) Physical resource: i_DCM_TTCclk/CLKIN Logical resource: i_DCM_TTCclk/CLKIN Location pin: DCM_X0Y6.CLKIN Clock network: i_DCM_TTCclk_ML_NEW_DIVCLK -------------------------------------------------------------------------------- Slack: 20.900ns (period - min period limit) Period: 24.900ns Min period limit: 4.000ns (250.000MHz) (Tdcmper_CLKIN) Physical resource: i_DCM_TTCclk/CLKIN Logical resource: i_DCM_TTCclk/CLKIN Location pin: DCM_X0Y6.CLKIN Clock network: i_DCM_TTCclk_ML_NEW_DIVCLK -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 62664 paths analyzed, 16065 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 8.000ns. -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/status_buffer/history_103 (SLICE_X22Y64.SR), 13 paths -------------------------------------------------------------------------------- Slack (setup path): 0.466ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdvld (FF) Destination: i_ipbus/udp_if/status_buffer/history_103 (FF) Requirement: 8.000ns Data Path Delay: 7.395ns (Levels of Logic = 3) Clock Path Skew: -0.004ns (0.644 - 0.648) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdvld to i_ipbus/udp_if/status_buffer/history_103 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y93.AQ Tcko 0.430 GbErxdvld i_GTP_if/i_mac/emacclientrxdvld SLICE_X17Y95.A6 net (fanout=216) 1.090 GbErxdvld SLICE_X17Y95.A Tilo 0.259 i_ipbus/udp_if/rx_packet_parser/littleendian.reliable_data<27> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X24Y69.A6 net (fanout=675) 2.420 i_ipbus/udp_if/rx_reset SLICE_X24Y69.A Tilo 0.235 i_ipbus/udp_if/status_buffer/history<76> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1257_o141 SLICE_X22Y64.A5 net (fanout=15) 1.074 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1261_o SLICE_X22Y64.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X22Y64.SR net (fanout=5) 1.089 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X22Y64.CLK Tsrck 0.544 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/history_103 ------------------------------------------------- --------------------------- Total 7.395ns (1.722ns logic, 5.673ns route) (23.3% logic, 76.7% route) -------------------------------------------------------------------------------- Slack (setup path): 0.766ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdlast (FF) Destination: i_ipbus/udp_if/status_buffer/history_103 (FF) Requirement: 8.000ns Data Path Delay: 7.095ns (Levels of Logic = 4) Clock Path Skew: -0.004ns (0.644 - 0.648) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdlast to i_ipbus/udp_if/status_buffer/history_103 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y93.AMUX Tshcko 0.518 GbErxdvld i_GTP_if/i_mac/emacclientrxdlast SLICE_X23Y86.C5 net (fanout=3) 0.914 GbErxdlast SLICE_X23Y86.C Tilo 0.259 i_ipbus/udp_if/last_rx_last i_ipbus/udp_if/my_rx_last1 SLICE_X23Y73.A4 net (fanout=61) 1.298 i_ipbus/udp_if/my_rx_last SLICE_X23Y73.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X24Y69.A5 net (fanout=1) 0.651 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_113_o_MUX_1250_o SLICE_X24Y69.A Tilo 0.235 i_ipbus/udp_if/status_buffer/history<76> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1257_o141 SLICE_X22Y64.A5 net (fanout=15) 1.074 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1261_o SLICE_X22Y64.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X22Y64.SR net (fanout=5) 1.089 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X22Y64.CLK Tsrck 0.544 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/history_103 ------------------------------------------------- --------------------------- Total 7.095ns (2.069ns logic, 5.026ns route) (29.2% logic, 70.8% route) -------------------------------------------------------------------------------- Slack (setup path): 0.871ns (requirement - (data path - clock path skew + uncertainty)) Source: rst_ipbus (FF) Destination: i_ipbus/udp_if/status_buffer/history_103 (FF) Requirement: 8.000ns Data Path Delay: 6.983ns (Levels of Logic = 4) Clock Path Skew: -0.011ns (0.302 - 0.313) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: rst_ipbus to i_ipbus/udp_if/status_buffer/history_103 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X21Y67.AQ Tcko 0.430 rst_ipbus rst_ipbus SLICE_X20Y64.B5 net (fanout=2) 0.897 rst_ipbus SLICE_X20Y64.B Tilo 0.235 i_ipbus/udp_if/status_buffer/history_block.async_pending GbEGTPreset1 SLICE_X23Y73.A5 net (fanout=700) 1.315 GbEGTPreset SLICE_X23Y73.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X24Y69.A5 net (fanout=1) 0.651 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_113_o_MUX_1250_o SLICE_X24Y69.A Tilo 0.235 i_ipbus/udp_if/status_buffer/history<76> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1257_o141 SLICE_X22Y64.A5 net (fanout=15) 1.074 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1261_o SLICE_X22Y64.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X22Y64.SR net (fanout=5) 1.089 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X22Y64.CLK Tsrck 0.544 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/history_103 ------------------------------------------------- --------------------------- Total 6.983ns (1.957ns logic, 5.026ns route) (28.0% logic, 72.0% route) -------------------------------------------------------------------------------- Paths for end point i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 (SLICE_X34Y103.AI), 3 paths -------------------------------------------------------------------------------- Slack (setup path): 0.467ns (requirement - (data path - clock path skew + uncertainty)) Source: i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i (FF) Destination: i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 (FF) Requirement: 8.000ns Data Path Delay: 7.312ns (Levels of Logic = 1) Clock Path Skew: -0.086ns (0.584 - 0.670) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i to i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X11Y77.AQ Tcko 0.430 LinkFIFO_empty i_LinkFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i SLICE_X11Y64.A5 net (fanout=3) 1.396 LinkFIFO_empty SLICE_X11Y64.A Tilo 0.259 GbEtxdvld Mmux_GbEtxdvld11 SLICE_X34Y103.AI net (fanout=6) 5.165 GbEtxdvld SLICE_X34Y103.CLK Tds 0.062 i_GTP_if/i_GbE_pcs_pma/BU2/U0/RECEIVER/SOP_REG2 i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 ------------------------------------------------- --------------------------- Total 7.312ns (0.751ns logic, 6.561ns route) (10.3% logic, 89.7% route) -------------------------------------------------------------------------------- Slack (setup path): 0.514ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/udp_if/tx_main/mac_tx_valid_sig (FF) Destination: i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 (FF) Requirement: 8.000ns Data Path Delay: 7.271ns (Levels of Logic = 1) Clock Path Skew: -0.080ns (0.676 - 0.756) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/udp_if/tx_main/mac_tx_valid_sig to i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y56.AQ Tcko 0.430 ipbus_txdvld i_ipbus/udp_if/tx_main/mac_tx_valid_sig SLICE_X11Y64.A3 net (fanout=31) 1.355 ipbus_txdvld SLICE_X11Y64.A Tilo 0.259 GbEtxdvld Mmux_GbEtxdvld11 SLICE_X34Y103.AI net (fanout=6) 5.165 GbEtxdvld SLICE_X34Y103.CLK Tds 0.062 i_GTP_if/i_GbE_pcs_pma/BU2/U0/RECEIVER/SOP_REG2 i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 ------------------------------------------------- --------------------------- Total 7.271ns (0.751ns logic, 6.520ns route) (10.3% logic, 89.7% route) -------------------------------------------------------------------------------- Slack (setup path): 1.205ns (requirement - (data path - clock path skew + uncertainty)) Source: sel_Link (FF) Destination: i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 (FF) Requirement: 8.000ns Data Path Delay: 6.571ns (Levels of Logic = 1) Clock Path Skew: -0.089ns (0.584 - 0.673) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: sel_Link to i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X11Y64.AMUX Tshcko 0.518 GbEtxdvld sel_Link SLICE_X11Y64.A2 net (fanout=9) 0.567 sel_Link SLICE_X11Y64.A Tilo 0.259 GbEtxdvld Mmux_GbEtxdvld11 SLICE_X34Y103.AI net (fanout=6) 5.165 GbEtxdvld SLICE_X34Y103.CLK Tds 0.062 i_GTP_if/i_GbE_pcs_pma/BU2/U0/RECEIVER/SOP_REG2 i_GTP_if/i_mac/Mshreg_clientemactxdvld_dl2 ------------------------------------------------- --------------------------- Total 6.571ns (0.839ns logic, 5.732ns route) (12.8% logic, 87.2% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/status_buffer/history_102 (SLICE_X22Y64.SR), 13 paths -------------------------------------------------------------------------------- Slack (setup path): 0.506ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdvld (FF) Destination: i_ipbus/udp_if/status_buffer/history_102 (FF) Requirement: 8.000ns Data Path Delay: 7.355ns (Levels of Logic = 3) Clock Path Skew: -0.004ns (0.644 - 0.648) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdvld to i_ipbus/udp_if/status_buffer/history_102 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y93.AQ Tcko 0.430 GbErxdvld i_GTP_if/i_mac/emacclientrxdvld SLICE_X17Y95.A6 net (fanout=216) 1.090 GbErxdvld SLICE_X17Y95.A Tilo 0.259 i_ipbus/udp_if/rx_packet_parser/littleendian.reliable_data<27> i_ipbus/udp_if/rx_reset_block/rx_reset1 SLICE_X24Y69.A6 net (fanout=675) 2.420 i_ipbus/udp_if/rx_reset SLICE_X24Y69.A Tilo 0.235 i_ipbus/udp_if/status_buffer/history<76> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1257_o141 SLICE_X22Y64.A5 net (fanout=15) 1.074 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1261_o SLICE_X22Y64.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X22Y64.SR net (fanout=5) 1.089 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X22Y64.CLK Tsrck 0.504 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/history_102 ------------------------------------------------- --------------------------- Total 7.355ns (1.682ns logic, 5.673ns route) (22.9% logic, 77.1% route) -------------------------------------------------------------------------------- Slack (setup path): 0.806ns (requirement - (data path - clock path skew + uncertainty)) Source: i_GTP_if/i_mac/emacclientrxdlast (FF) Destination: i_ipbus/udp_if/status_buffer/history_102 (FF) Requirement: 8.000ns Data Path Delay: 7.055ns (Levels of Logic = 4) Clock Path Skew: -0.004ns (0.644 - 0.648) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_GTP_if/i_mac/emacclientrxdlast to i_ipbus/udp_if/status_buffer/history_102 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y93.AMUX Tshcko 0.518 GbErxdvld i_GTP_if/i_mac/emacclientrxdlast SLICE_X23Y86.C5 net (fanout=3) 0.914 GbErxdlast SLICE_X23Y86.C Tilo 0.259 i_ipbus/udp_if/last_rx_last i_ipbus/udp_if/my_rx_last1 SLICE_X23Y73.A4 net (fanout=61) 1.298 i_ipbus/udp_if/my_rx_last SLICE_X23Y73.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X24Y69.A5 net (fanout=1) 0.651 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_113_o_MUX_1250_o SLICE_X24Y69.A Tilo 0.235 i_ipbus/udp_if/status_buffer/history<76> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1257_o141 SLICE_X22Y64.A5 net (fanout=15) 1.074 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1261_o SLICE_X22Y64.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X22Y64.SR net (fanout=5) 1.089 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X22Y64.CLK Tsrck 0.504 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/history_102 ------------------------------------------------- --------------------------- Total 7.055ns (2.029ns logic, 5.026ns route) (28.8% logic, 71.2% route) -------------------------------------------------------------------------------- Slack (setup path): 0.911ns (requirement - (data path - clock path skew + uncertainty)) Source: rst_ipbus (FF) Destination: i_ipbus/udp_if/status_buffer/history_102 (FF) Requirement: 8.000ns Data Path Delay: 6.943ns (Levels of Logic = 4) Clock Path Skew: -0.011ns (0.302 - 0.313) Source Clock: sysclk rising at 0.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: rst_ipbus to i_ipbus/udp_if/status_buffer/history_102 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X21Y67.AQ Tcko 0.430 rst_ipbus rst_ipbus SLICE_X20Y64.B5 net (fanout=2) 0.897 rst_ipbus SLICE_X20Y64.B Tilo 0.235 i_ipbus/udp_if/status_buffer/history_block.async_pending GbEGTPreset1 SLICE_X23Y73.A5 net (fanout=700) 1.315 GbEGTPreset SLICE_X23Y73.A Tilo 0.259 i_ipbus/udp_if/status_buffer/history_block.event_pending i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_pkt_drop_rarp_mux_19_OUT1111 SLICE_X24Y69.A5 net (fanout=1) 0.651 i_ipbus/udp_if/status_buffer/history_block.event_pending_PWR_113_o_MUX_1250_o SLICE_X24Y69.A Tilo 0.235 i_ipbus/udp_if/status_buffer/history<76> i_ipbus/udp_if/status_buffer/Mmux_history_block.event_data[7]_history_block.event_data[7]_MUX_1257_o141 SLICE_X22Y64.A5 net (fanout=15) 1.074 i_ipbus/udp_if/status_buffer/rst_ipb_125_rst_ipb_125_MUX_1261_o SLICE_X22Y64.A Tilo 0.254 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/_n02111_3 SLICE_X22Y64.SR net (fanout=5) 1.089 i_ipbus/udp_if/status_buffer/_n021112 SLICE_X22Y64.CLK Tsrck 0.504 i_ipbus/udp_if/status_buffer/history<99> i_ipbus/udp_if/status_buffer/history_102 ------------------------------------------------- --------------------------- Total 6.943ns (1.917ns logic, 5.026ns route) (27.6% logic, 72.4% route) -------------------------------------------------------------------------------- Hold Paths: TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X3Y32.WEB1), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.300ns (requirement - (clock path skew + uncertainty - data path)) Source: i_flash/web_1 (FF) Destination: i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 0.000ns Data Path Delay: 0.304ns (Levels of Logic = 0) Clock Path Skew: 0.004ns (0.076 - 0.072) Source Clock: sysclk rising at 8.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_flash/web_1 to i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X53Y64.BQ Tcko 0.198 i_flash/web<3> i_flash/web_1 RAMB16_X3Y32.WEB1 net (fanout=1) 0.159 i_flash/web<1> RAMB16_X3Y32.CLKB Trckc_WEB (-Th) 0.053 i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st i_flash/i_wbuf/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 0.304ns (0.145ns logic, 0.159ns route) (47.7% logic, 52.3% route) -------------------------------------------------------------------------------- Paths for end point i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i (GTPA1_DUAL_X0Y0.TXDATA013), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.332ns (requirement - (clock path skew + uncertainty - data path)) Source: LINKtxdata_13 (FF) Destination: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i (HSIO) Requirement: 0.000ns Data Path Delay: 0.384ns (Levels of Logic = 0) Clock Path Skew: 0.052ns (0.119 - 0.067) Source Clock: sysclk rising at 8.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: LINKtxdata_13 to i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------------- ------------------- SLICE_X6Y116.DQ Tcko 0.234 LINKtxdata<13> LINKtxdata_13 GTPA1_DUAL_X0Y0.TXDATA013 net (fanout=1) 0.650 LINKtxdata<13> GTPA1_DUAL_X0Y0.TXUSRCLK20 Tgtpckc_TXDATA(-Th) 0.500 i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i ------------------------------------------------------- --------------------------- Total 0.384ns (-0.266ns logic, 0.650ns route) (-69.3% logic, 169.3% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/ipbus_tx_ram/Mram_ram9 (RAMB16_X1Y26.ADDRB3), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.354ns (requirement - (clock path skew + uncertainty - data path)) Source: i_ipbus/udp_if/tx_main/addr_sig_4 (FF) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram9 (RAM) Requirement: 0.000ns Data Path Delay: 0.362ns (Levels of Logic = 0) Clock Path Skew: 0.008ns (0.070 - 0.062) Source Clock: sysclk rising at 8.000ns Destination Clock: sysclk rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_ipbus/udp_if/tx_main/addr_sig_4 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X16Y55.AQ Tcko 0.200 i_ipbus/udp_if/addrb<7> i_ipbus/udp_if/tx_main/addr_sig_4 RAMB16_X1Y26.ADDRB3 net (fanout=28) 0.228 i_ipbus/udp_if/addrb<4> RAMB16_X1Y26.CLKB Trckc_ADDRB (-Th) 0.066 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram9 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram9 ------------------------------------------------- --------------------------- Total 0.362ns (0.134ns logic, 0.228ns route) (37.0% logic, 63.0% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 0.000ns (period - min period limit) Period: 8.000ns Min period limit: 8.000ns (125.000MHz) (Tgtpcper_RXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK20 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK20 Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK20 Clock network: sysclk -------------------------------------------------------------------------------- Slack: 0.000ns (period - min period limit) Period: 8.000ns Min period limit: 8.000ns (125.000MHz) (Tgtpcper_RXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK21 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK21 Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK21 Clock network: sysclk -------------------------------------------------------------------------------- Slack: 0.000ns (period - min period limit) Period: 8.000ns Min period limit: 8.000ns (125.000MHz) (Tgtpcper_TXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK20 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK20 Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK20 Clock network: sysclk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_sysclk2x = PERIOD TIMEGRP "sysclk2x" 4 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 3.703ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_sysclk2x = PERIOD TIMEGRP "sysclk2x" 4 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 0.297ns (period - min period limit) Period: 4.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_RXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK0 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/RXUSRCLK0 Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK0 Clock network: sysclk2x -------------------------------------------------------------------------------- Slack: 0.297ns (period - min period limit) Period: 4.000ns Min period limit: 3.703ns (270.051MHz) (Tgtpcper_TXUSRCLK) Physical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK0 Logical resource: i_GTP_if/i_S6Link_GbE/tile0_S6Link_GbE_i/gtpa1_dual_i/TXUSRCLK0 Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK0 Clock network: sysclk2x -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 18488 paths analyzed, 2922 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 18.248ns. -------------------------------------------------------------------------------- Paths for end point i_FLASH_C_ddr (OLOGIC_X26Y1.D2), 2 paths -------------------------------------------------------------------------------- Slack (setup path): 6.876ns (requirement - (data path - clock path skew + uncertainty)) Source: en_conf (FF) Destination: i_FLASH_C_ddr (FF) Requirement: 16.000ns Data Path Delay: 9.403ns (Levels of Logic = 1) Clock Path Skew: 0.464ns (1.111 - 0.647) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk falling at 16.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: en_conf to i_FLASH_C_ddr Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y59.CQ Tcko 0.430 rst_CRC en_conf SLICE_X49Y45.D4 net (fanout=35) 3.868 en_conf SLICE_X49Y45.D Tilo 0.259 en_flash_c en_flash_c1 OLOGIC_X26Y1.D2 net (fanout=1) 3.877 en_flash_c OLOGIC_X26Y1.CLK1 Todck 0.969 FLASH_C_OBUF i_FLASH_C_ddr ------------------------------------------------- --------------------------- Total 9.403ns (1.658ns logic, 7.745ns route) (17.6% logic, 82.4% route) -------------------------------------------------------------------------------- Slack (setup path): 9.975ns (requirement - (data path - clock path skew + uncertainty)) Source: i_flash/MCS_1 (FF) Destination: i_FLASH_C_ddr (FF) Requirement: 16.000ns Data Path Delay: 6.329ns (Levels of Logic = 1) Clock Path Skew: 0.489ns (1.111 - 0.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk falling at 16.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_flash/MCS_1 to i_FLASH_C_ddr Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X42Y45.BQ Tcko 0.476 flash_mcs<1> i_flash/MCS_1 SLICE_X49Y45.D5 net (fanout=2) 0.748 flash_mcs<1> SLICE_X49Y45.D Tilo 0.259 en_flash_c en_flash_c1 OLOGIC_X26Y1.D2 net (fanout=1) 3.877 en_flash_c OLOGIC_X26Y1.CLK1 Todck 0.969 FLASH_C_OBUF i_FLASH_C_ddr ------------------------------------------------- --------------------------- Total 6.329ns (1.704ns logic, 4.625ns route) (26.9% logic, 73.1% route) -------------------------------------------------------------------------------- Paths for end point i_V6CCLK_ddr (OLOGIC_X26Y119.D2), 1 path -------------------------------------------------------------------------------- Slack (setup path): 8.484ns (requirement - (data path - clock path skew + uncertainty)) Source: en_CCLK (FF) Destination: i_V6CCLK_ddr (FF) Requirement: 16.000ns Data Path Delay: 7.782ns (Levels of Logic = 0) Clock Path Skew: 0.451ns (1.188 - 0.737) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk falling at 16.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: en_CCLK to i_V6CCLK_ddr Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X31Y55.BMUX Tshcko 0.518 calc_CRC en_CCLK OLOGIC_X26Y119.D2 net (fanout=2) 6.295 en_CCLK OLOGIC_X26Y119.CLK1 Todck 0.969 V6_CCLK_OBUF i_V6CCLK_ddr ------------------------------------------------- --------------------------- Total 7.782ns (1.487ns logic, 6.295ns route) (19.1% logic, 80.9% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 (RAMB16_X0Y26.DIA1), 43 paths -------------------------------------------------------------------------------- Slack (setup path): 15.688ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/trans/sm/addr_1 (FF) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 (RAM) Requirement: 32.000ns Data Path Delay: 16.107ns (Levels of Logic = 5) Clock Path Skew: -0.020ns (0.631 - 0.651) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/trans/sm/addr_1 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X46Y61.BQ Tcko 0.476 ipb_master_out_ipb_addr<3> i_ipbus/trans/sm/addr_1 SLICE_X30Y30.A1 net (fanout=104) 7.062 ipb_master_out_ipb_addr<1> SLICE_X30Y30.A Tilo 0.254 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_114_OUT_72 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_114_OUT_72 SLICE_X46Y57.A2 net (fanout=1) 3.237 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_114_OUT_72 SLICE_X46Y57.A Tilo 0.235 i_ipbus/trans/sm/rmw_input<12> Mmux_ipb_master_in_ipb_rdata3_SW0 SLICE_X46Y57.B6 net (fanout=1) 0.143 N41 SLICE_X46Y57.B Tilo 0.235 i_ipbus/trans/sm/rmw_input<12> Mmux_ipb_master_in_ipb_rdata3 SLICE_X32Y56.B4 net (fanout=1) 1.153 ipb_master_in_ipb_rdata<11> SLICE_X32Y56.B Tilo 0.235 i_ipbus/trans/cfg_dout<0> i_ipbus/trans/sm/mux1011 SLICE_X32Y56.A5 net (fanout=1) 0.196 i_ipbus/trans/tx_data<11> SLICE_X32Y56.A Tilo 0.235 i_ipbus/trans/cfg_dout<0> i_ipbus/trans/iface/Mmux_trans_out_wdata31 RAMB16_X0Y26.DIA1 net (fanout=1) 2.346 i_ipbus/trans_out_wdata<11> RAMB16_X0Y26.CLKA Trdck_DIA 0.300 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 ------------------------------------------------- --------------------------- Total 16.107ns (1.970ns logic, 14.137ns route) (12.2% logic, 87.8% route) -------------------------------------------------------------------------------- Slack (setup path): 16.250ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/trans/sm/addr_0 (FF) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 (RAM) Requirement: 32.000ns Data Path Delay: 15.545ns (Levels of Logic = 5) Clock Path Skew: -0.020ns (0.631 - 0.651) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/trans/sm/addr_0 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X46Y61.AQ Tcko 0.476 ipb_master_out_ipb_addr<3> i_ipbus/trans/sm/addr_0 SLICE_X30Y30.A3 net (fanout=95) 6.500 ipb_master_out_ipb_addr<0> SLICE_X30Y30.A Tilo 0.254 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_114_OUT_72 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_114_OUT_72 SLICE_X46Y57.A2 net (fanout=1) 3.237 Mmux_ipb_master_out_ipb_addr[3]_GND_11_o_wide_mux_114_OUT_72 SLICE_X46Y57.A Tilo 0.235 i_ipbus/trans/sm/rmw_input<12> Mmux_ipb_master_in_ipb_rdata3_SW0 SLICE_X46Y57.B6 net (fanout=1) 0.143 N41 SLICE_X46Y57.B Tilo 0.235 i_ipbus/trans/sm/rmw_input<12> Mmux_ipb_master_in_ipb_rdata3 SLICE_X32Y56.B4 net (fanout=1) 1.153 ipb_master_in_ipb_rdata<11> SLICE_X32Y56.B Tilo 0.235 i_ipbus/trans/cfg_dout<0> i_ipbus/trans/sm/mux1011 SLICE_X32Y56.A5 net (fanout=1) 0.196 i_ipbus/trans/tx_data<11> SLICE_X32Y56.A Tilo 0.235 i_ipbus/trans/cfg_dout<0> i_ipbus/trans/iface/Mmux_trans_out_wdata31 RAMB16_X0Y26.DIA1 net (fanout=1) 2.346 i_ipbus/trans_out_wdata<11> RAMB16_X0Y26.CLKA Trdck_DIA 0.300 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 ------------------------------------------------- --------------------------- Total 15.545ns (1.970ns logic, 13.575ns route) (12.7% logic, 87.3% route) -------------------------------------------------------------------------------- Slack (setup path): 21.975ns (requirement - (data path - clock path skew + uncertainty)) Source: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram22 (RAM) Destination: i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 (RAM) Requirement: 32.000ns Data Path Delay: 9.849ns (Levels of Logic = 2) Clock Path Skew: 0.009ns (0.723 - 0.714) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.185ns Clock Uncertainty: 0.185ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.300ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram22 to i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X2Y42.DOB1 Trcko_DOB 2.100 i_ipbus/udp_if/ipbus_rx_ram/Mram_ram22 i_ipbus/udp_if/ipbus_rx_ram/Mram_ram22 SLICE_X42Y64.D1 net (fanout=2) 2.872 i_ipbus/trans_in_udp_rdata<11> SLICE_X42Y64.D Tilo 0.235 i_ipbus/trans/sm/rmw_result<11> i_ipbus/trans/iface/Mmux_rxd31 SLICE_X32Y56.A4 net (fanout=9) 1.761 i_ipbus/trans/cfg_din<11> SLICE_X32Y56.A Tilo 0.235 i_ipbus/trans/cfg_dout<0> i_ipbus/trans/iface/Mmux_trans_out_wdata31 RAMB16_X0Y26.DIA1 net (fanout=1) 2.346 i_ipbus/trans_out_wdata<11> RAMB16_X0Y26.CLKA Trdck_DIA 0.300 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 i_ipbus/udp_if/ipbus_tx_ram/Mram_ram6 ------------------------------------------------- --------------------------- Total 9.849ns (2.870ns logic, 6.979ns route) (29.1% logic, 70.9% route) -------------------------------------------------------------------------------- Hold Paths: TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X3Y30.ADDRA8), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.287ns (requirement - (clock path skew + uncertainty - data path)) Source: i_flash/addrap_9 (FF) Destination: i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 0.000ns Data Path Delay: 0.290ns (Levels of Logic = 0) Clock Path Skew: 0.003ns (0.074 - 0.071) Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_flash/addrap_9 to i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X55Y61.AQ Tcko 0.198 i_flash/addrap<11> i_flash/addrap_9 RAMB16_X3Y30.ADDRA8 net (fanout=3) 0.158 i_flash/addrap<9> RAMB16_X3Y30.CLKA Trckc_ADDRA (-Th) 0.066 i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 0.290ns (0.132ns logic, 0.158ns route) (45.5% logic, 54.5% route) -------------------------------------------------------------------------------- Paths for end point i_ipbus/trans/sm/rmw_result_14 (SLICE_X44Y67.CE), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.291ns (requirement - (clock path skew + uncertainty - data path)) Source: i_ipbus/trans/sm/state_FSM_FFd1 (FF) Destination: i_ipbus/trans/sm/rmw_result_14 (FF) Requirement: 0.000ns Data Path Delay: 0.294ns (Levels of Logic = 0) Clock Path Skew: 0.003ns (0.075 - 0.072) Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_ipbus/trans/sm/state_FSM_FFd1 to i_ipbus/trans/sm/rmw_result_14 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X43Y67.AQ Tcko 0.198 i_ipbus/trans/sm/state_FSM_FFd2 i_ipbus/trans/sm/state_FSM_FFd1 SLICE_X44Y67.CE net (fanout=66) 0.198 i_ipbus/trans/sm/state_FSM_FFd1 SLICE_X44Y67.CLK Tckce (-Th) 0.102 i_ipbus/trans/sm/rmw_result<14> i_ipbus/trans/sm/rmw_result_14 ------------------------------------------------- --------------------------- Total 0.294ns (0.096ns logic, 0.198ns route) (32.7% logic, 67.3% route) -------------------------------------------------------------------------------- Paths for end point i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st (RAMB16_X3Y30.ADDRA7), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.292ns (requirement - (clock path skew + uncertainty - data path)) Source: i_flash/addrap_8 (FF) Destination: i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st (RAM) Requirement: 0.000ns Data Path Delay: 0.297ns (Levels of Logic = 0) Clock Path Skew: 0.005ns (0.074 - 0.069) Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: i_flash/addrap_8 to i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X55Y60.DQ Tcko 0.198 i_flash/addrap<8> i_flash/addrap_8 RAMB16_X3Y30.ADDRA7 net (fanout=3) 0.165 i_flash/addrap<8> RAMB16_X3Y30.CLKA Trckc_ADDRA (-Th) 0.066 i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st i_flash/i_rbuf/ramb_st.ramb18_dp_st.ram18_st ------------------------------------------------- --------------------------- Total 0.297ns (0.132ns logic, 0.165ns route) (44.4% logic, 55.6% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 28.430ns (period - min period limit) Period: 32.000ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) Physical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKB Logical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKB Location pin: RAMB16_X2Y34.CLKB Clock network: ipb_clk -------------------------------------------------------------------------------- Slack: 28.430ns (period - min period limit) Period: 32.000ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) Physical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram12/CLKB Logical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram12/CLKB Location pin: RAMB16_X2Y44.CLKB Clock network: ipb_clk -------------------------------------------------------------------------------- Slack: 28.430ns (period - min period limit) Period: 32.000ns Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) Physical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram21/CLKB Logical resource: i_ipbus/udp_if/ipbus_rx_ram/Mram_ram21/CLKB Location pin: RAMB16_X2Y30.CLKB Clock network: ipb_clk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dcm" TS_TTC_REFCLK PHASE -3.890625 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 1123 paths analyzed, 423 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 14.092ns. -------------------------------------------------------------------------------- Paths for end point TTC_data_1_P_1 (SLICE_X33Y99.AX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 5.404ns (requirement - (data path - clock path skew + uncertainty)) Source: i_TTC_data (FF) Destination: TTC_data_1_P_1 (FF) Requirement: 12.450ns Data Path Delay: 6.265ns (Levels of Logic = 0) Clock Path Skew: -0.646ns (0.592 - 1.238) Source Clock: TTCclk falling at 8.560ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_TTC_data to TTC_data_1_P_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y117.Q3 Tickq 1.326 TTCdata<1> i_TTC_data SLICE_X33Y99.AX net (fanout=2) 4.825 TTCdata<1> SLICE_X33Y99.CLK Tdick 0.114 TTC_data_1_P_1 TTC_data_1_P_1 ------------------------------------------------- --------------------------- Total 6.265ns (1.440ns logic, 4.825ns route) (23.0% logic, 77.0% route) -------------------------------------------------------------------------------- Paths for end point TTC_data_1_C_1 (SLICE_X33Y98.AX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 5.414ns (requirement - (data path - clock path skew + uncertainty)) Source: i_TTC_data (FF) Destination: TTC_data_1_C_1 (FF) Requirement: 12.450ns Data Path Delay: 6.257ns (Levels of Logic = 0) Clock Path Skew: -0.644ns (0.594 - 1.238) Source Clock: TTCclk falling at 8.560ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: i_TTC_data to TTC_data_1_C_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y117.Q3 Tickq 1.326 TTCdata<1> i_TTC_data SLICE_X33Y98.AX net (fanout=2) 4.817 TTCdata<1> SLICE_X33Y98.CLK Tdick 0.114 TTC_data_1_C_1 TTC_data_1_C_1 ------------------------------------------------- --------------------------- Total 6.257ns (1.440ns logic, 4.817ns route) (23.0% logic, 77.0% route) -------------------------------------------------------------------------------- Paths for end point ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 (SLICE_X40Y28.CE), 16 paths -------------------------------------------------------------------------------- Slack (setup path): 17.052ns (requirement - (data path - clock path skew + uncertainty)) Source: TxFB_9 (FF) Destination: ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 (FF) Requirement: 24.900ns Data Path Delay: 7.649ns (Levels of Logic = 2) Clock Path Skew: -0.064ns (0.592 - 0.656) Source Clock: TTCclk rising at -3.890ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: TxFB_9 to ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y14.AQ Tcko 0.525 TxFB<12> TxFB_9 SLICE_X22Y4.D1 net (fanout=5) 2.283 TxFB<9> SLICE_X22Y4.D Tilo 0.254 n0029_inv4 n0029_inv4 SLICE_X31Y4.A2 net (fanout=1) 1.547 n0029_inv4 SLICE_X31Y4.A Tilo 0.259 n0029_inv3 n0029_inv7 SLICE_X40Y28.CE net (fanout=1) 2.467 n0029_inv SLICE_X40Y28.CLK Tceck 0.314 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63><5> ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 ------------------------------------------------- --------------------------- Total 7.649ns (1.352ns logic, 6.297ns route) (17.7% logic, 82.3% route) -------------------------------------------------------------------------------- Slack (setup path): 17.385ns (requirement - (data path - clock path skew + uncertainty)) Source: TxFB_11 (FF) Destination: ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 (FF) Requirement: 24.900ns Data Path Delay: 7.316ns (Levels of Logic = 2) Clock Path Skew: -0.064ns (0.592 - 0.656) Source Clock: TTCclk rising at -3.890ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: TxFB_11 to ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y14.CQ Tcko 0.525 TxFB<12> TxFB_11 SLICE_X22Y4.D4 net (fanout=5) 1.950 TxFB<11> SLICE_X22Y4.D Tilo 0.254 n0029_inv4 n0029_inv4 SLICE_X31Y4.A2 net (fanout=1) 1.547 n0029_inv4 SLICE_X31Y4.A Tilo 0.259 n0029_inv3 n0029_inv7 SLICE_X40Y28.CE net (fanout=1) 2.467 n0029_inv SLICE_X40Y28.CLK Tceck 0.314 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63><5> ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 ------------------------------------------------- --------------------------- Total 7.316ns (1.352ns logic, 5.964ns route) (18.5% logic, 81.5% route) -------------------------------------------------------------------------------- Slack (setup path): 17.785ns (requirement - (data path - clock path skew + uncertainty)) Source: TxFB_10 (FF) Destination: ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 (FF) Requirement: 24.900ns Data Path Delay: 6.916ns (Levels of Logic = 2) Clock Path Skew: -0.064ns (0.592 - 0.656) Source Clock: TTCclk rising at -3.890ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.135ns Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: TxFB_10 to ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y14.BQ Tcko 0.525 TxFB<12> TxFB_10 SLICE_X22Y4.D5 net (fanout=4) 1.550 TxFB<10> SLICE_X22Y4.D Tilo 0.254 n0029_inv4 n0029_inv4 SLICE_X31Y4.A2 net (fanout=1) 1.547 n0029_inv4 SLICE_X31Y4.A Tilo 0.259 n0029_inv3 n0029_inv7 SLICE_X40Y28.CE net (fanout=1) 2.467 n0029_inv SLICE_X40Y28.CLK Tceck 0.314 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63><5> ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_0 ------------------------------------------------- --------------------------- Total 6.916ns (1.352ns logic, 5.564ns route) (19.5% logic, 80.5% route) -------------------------------------------------------------------------------- Hold Paths: TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dcm" TS_TTC_REFCLK PHASE -3.890625 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point sr_3 (SLICE_X46Y78.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.399ns (requirement - (clock path skew + uncertainty - data path)) Source: sr_2 (FF) Destination: sr_3 (FF) Requirement: 0.000ns Data Path Delay: 0.399ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: TTCclk rising at 21.010ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: sr_2 to sr_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X46Y78.CQ Tcko 0.200 sr<3> sr_2 SLICE_X46Y78.DX net (fanout=3) 0.151 sr<2> SLICE_X46Y78.CLK Tckdi (-Th) -0.048 sr<3> sr_3 ------------------------------------------------- --------------------------- Total 0.399ns (0.248ns logic, 0.151ns route) (62.2% logic, 37.8% route) -------------------------------------------------------------------------------- Paths for end point ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_3 (SLICE_X40Y28.C5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.401ns (requirement - (clock path skew + uncertainty - data path)) Source: ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_4 (FF) Destination: ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_3 (FF) Requirement: 0.000ns Data Path Delay: 0.401ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: TTCclk rising at 21.010ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_4 to ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X40Y28.CQ Tcko 0.200 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63><5> ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_4 SLICE_X40Y28.C5 net (fanout=4) 0.080 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63><4> SLICE_X40Y28.CLK Tah (-Th) -0.121 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63><5> Mcount_ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_xor<2>11 ASYNC_IN<58>_ASYNC_IN<59>_ASYNC_IN<60>_ASYNC_IN<61>_ASYNC_IN<62>_ASYNC_IN<63>_3 ------------------------------------------------- --------------------------- Total 0.401ns (0.321ns logic, 0.080ns route) (80.0% logic, 20.0% route) -------------------------------------------------------------------------------- Paths for end point sr_1 (SLICE_X46Y78.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.401ns (requirement - (clock path skew + uncertainty - data path)) Source: sr_0 (FF) Destination: sr_1 (FF) Requirement: 0.000ns Data Path Delay: 0.401ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: TTCclk rising at 21.010ns Destination Clock: TTCclk rising at 21.010ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: sr_0 to sr_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X46Y78.AQ Tcko 0.200 sr<3> sr_0 SLICE_X46Y78.BX net (fanout=3) 0.153 sr<0> SLICE_X46Y78.CLK Tckdi (-Th) -0.048 sr<3> sr_1 ------------------------------------------------- --------------------------- Total 0.401ns (0.248ns logic, 0.153ns route) (61.8% logic, 38.2% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dcm" TS_TTC_REFCLK PHASE -3.890625 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 22.234ns (period - min period limit) Period: 24.900ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: i_TTCclk/I0 Logical resource: i_TTCclk/I0 Location pin: BUFGMUX_X2Y3.I0 Clock network: TTCclk_dcm -------------------------------------------------------------------------------- Slack: 23.034ns (period - min period limit) Period: 24.900ns Min period limit: 1.866ns (535.906MHz) (Tickper) Physical resource: RxFB_in<10>/CLK0 Logical resource: RxFB_10/CLK0 Location pin: ILOGIC_X4Y3.CLK0 Clock network: TTCclk -------------------------------------------------------------------------------- Slack: 23.034ns (period - min period limit) Period: 24.900ns Min period limit: 1.866ns (535.906MHz) (Tickper) Physical resource: RxFB_in<11>/CLK0 Logical resource: RxFB_11/CLK0 Location pin: ILOGIC_X3Y3.CLK0 Clock network: TTCclk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP "TO_TTC_data_1_LD" TS_TTCclk_dcm DATAPATHONLY; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_TO_CRC_0_LD = MAXDELAY TO TIMEGRP "TO_CRC_0_LD" TS_ipb_clk DATAPATHONLY; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 4.950ns. -------------------------------------------------------------------------------- Paths for end point CRC_0_LD (SLICE_X45Y50.CLK), 1 path -------------------------------------------------------------------------------- Slack (slowest paths): 27.050ns (requirement - data path) Source: reprogV6 (FF) Destination: CRC_0_LD (LATCH) Requirement: 32.000ns Data Path Delay: 4.950ns (Levels of Logic = 1) Source Clock: ipb_clk rising at 0.000ns Maximum Data Path at Slow Process Corner: reprogV6 to CRC_0_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X31Y66.DMUX Tshcko 0.518 sysclk_dcm_locked_reprogV6_OR_86_o reprogV6 SLICE_X31Y66.D2 net (fanout=4) 0.550 reprogV6 SLICE_X31Y66.D Tilo 0.259 sysclk_dcm_locked_reprogV6_OR_86_o sysclk_dcm_locked_reprogV6_OR_86_o1 SLICE_X45Y50.CLK net (fanout=34) 3.623 sysclk_dcm_locked_reprogV6_OR_86_o ------------------------------------------------- --------------------------- Total 4.950ns (0.777ns logic, 4.173ns route) (15.7% logic, 84.3% route) -------------------------------------------------------------------------------- Hold Paths: TS_TO_CRC_0_LD = MAXDELAY TO TIMEGRP "TO_CRC_0_LD" TS_ipb_clk DATAPATHONLY; -------------------------------------------------------------------------------- Paths for end point CRC_0_LD (SLICE_X45Y50.CLK), 1 path -------------------------------------------------------------------------------- Delay (fastest path): 2.703ns (data path) Source: reprogV6 (FF) Destination: CRC_0_LD (LATCH) Data Path Delay: 2.703ns (Levels of Logic = 1) Source Clock: ipb_clk rising at 0.000ns Minimum Data Path at Fast Process Corner: reprogV6 to CRC_0_LD Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X31Y66.DMUX Tshcko 0.244 sysclk_dcm_locked_reprogV6_OR_86_o reprogV6 SLICE_X31Y66.D2 net (fanout=4) 0.272 reprogV6 SLICE_X31Y66.D Tilo 0.156 sysclk_dcm_locked_reprogV6_OR_86_o sysclk_dcm_locked_reprogV6_OR_86_o1 SLICE_X45Y50.CLK net (fanout=34) 2.031 sysclk_dcm_locked_reprogV6_OR_86_o ------------------------------------------------- --------------------------- Total 2.703ns (0.400ns logic, 2.303ns route) (14.8% logic, 85.2% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "RISING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 7.697ns. -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.303ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk rising at -3.890ns Requirement: 10.000ns Data Path Delay: 3.134ns (Levels of Logic = 2) Clock Path Delay: -0.398ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Data Path at Slow Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 1.387 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp768.IMUX.4 ILOGIC_X0Y117.D net (fanout=1) 0.399 TTCdata_in ILOGIC_X0Y117.CLK0 Tidock 1.348 TTCdata<1> ProtoComp788.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 3.134ns (2.735ns logic, 0.399ns route) (87.3% logic, 12.7% route) Minimum Clock Path at Slow Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 1.344 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp773.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.373 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y6.CLKIN net (fanout=1) 1.086 i_DCM_TTCclk_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -6.470 i_DCM_TTCclk i_DCM_TTCclk BUFGMUX_X2Y3.I0 net (fanout=1) 0.924 TTCclk_dcm BUFGMUX_X2Y3.O Tgi0o 0.197 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK0 net (fanout=56) 1.969 TTCclk ------------------------------------------------- --------------------------- Total -0.398ns (-4.750ns logic, 4.352ns route) -------------------------------------------------------------------------------- Hold Paths: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "RISING"; -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.776ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk rising at -3.890ns Requirement: -3.000ns Data Path Delay: 1.300ns (Levels of Logic = 2) Clock Path Delay: 0.139ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Data Path at Fast Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 0.618 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp768.IMUX.4 ILOGIC_X0Y117.D net (fanout=1) 0.181 TTCdata_in ILOGIC_X0Y117.CLK0 Tiockd (-Th) -0.501 TTCdata<1> ProtoComp788.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 1.300ns (1.119ns logic, 0.181ns route) (86.1% logic, 13.9% route) Maximum Clock Path at Fast Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 0.887 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp773.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.235 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y6.CLKIN net (fanout=1) 0.437 i_DCM_TTCclk_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.970 i_DCM_TTCclk i_DCM_TTCclk BUFGMUX_X2Y3.I0 net (fanout=1) 0.363 TTCclk_dcm BUFGMUX_X2Y3.O Tgi0o 0.063 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK0 net (fanout=56) 0.994 TTCclk ------------------------------------------------- --------------------------- Total 0.139ns (-1.890ns logic, 2.029ns route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "FALLING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 7.757ns. -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.243ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk falling at -3.890ns Requirement: 10.000ns Data Path Delay: 3.134ns (Levels of Logic = 2) Clock Path Delay: -0.458ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Maximum Data Path at Slow Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 1.387 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp768.IMUX.4 ILOGIC_X0Y117.D net (fanout=1) 0.399 TTCdata_in ILOGIC_X0Y117.CLK1 Tidock 1.348 TTCdata<1> ProtoComp788.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 3.134ns (2.735ns logic, 0.399ns route) (87.3% logic, 12.7% route) Minimum Clock Path at Slow Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 1.344 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp773.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.373 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y6.CLKIN net (fanout=1) 1.086 i_DCM_TTCclk_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -6.470 i_DCM_TTCclk i_DCM_TTCclk BUFGMUX_X2Y3.I0 net (fanout=1) 0.924 TTCclk_dcm BUFGMUX_X2Y3.O Tgi0o 0.197 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK1 net (fanout=56) 1.909 TTCclk ------------------------------------------------- --------------------------- Total -0.458ns (-4.750ns logic, 4.292ns route) -------------------------------------------------------------------------------- Hold Paths: COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "FALLING"; -------------------------------------------------------------------------------- Paths for end point i_TTC_data (ILOGIC_X0Y117.D), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.851ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: TTCdata_p (PAD) Destination: i_TTC_data (FF) Destination Clock: TTCclk falling at -3.890ns Requirement: -3.000ns Data Path Delay: 1.300ns (Levels of Logic = 2) Clock Path Delay: 0.064ns (Levels of Logic = 4) Clock Uncertainty: 0.275ns Clock Uncertainty: 0.275ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.200ns Phase Error (PE): 0.150ns Minimum Data Path at Fast Process Corner: TTCdata_p to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- C1.I Tiopi 0.618 TTCdata_p TTCdata_p i_TTCdata/IBUFDS ProtoComp768.IMUX.4 ILOGIC_X0Y117.D net (fanout=1) 0.181 TTCdata_in ILOGIC_X0Y117.CLK1 Tiockd (-Th) -0.501 TTCdata<1> ProtoComp788.D2OFFBYP_SRC i_TTC_data ------------------------------------------------- --------------------------- Total 1.300ns (1.119ns logic, 0.181ns route) (86.1% logic, 13.9% route) Maximum Clock Path at Fast Process Corner: TTC_REFCLK to i_TTC_data Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- L4.I Tiopi 0.887 TTC_REFCLK TTC_REFCLK i_TTC_REFCLK_in ProtoComp773.IMUX BUFIO2_X0Y23.I net (fanout=2) 0.235 TTC_REFCLK_in BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_0 SP6_BUFIO_INSERT_ML_BUFIO2_0 DCM_X0Y6.CLKIN net (fanout=1) 0.437 i_DCM_TTCclk_ML_NEW_DIVCLK DCM_X0Y6.CLK0 Tdmcko_CLK -2.970 i_DCM_TTCclk i_DCM_TTCclk BUFGMUX_X2Y3.I0 net (fanout=1) 0.363 TTCclk_dcm BUFGMUX_X2Y3.O Tgi0o 0.063 i_TTCclk i_TTCclk ILOGIC_X0Y117.CLK1 net (fanout=56) 0.919 TTCclk ------------------------------------------------- --------------------------- Total 0.064ns (-1.890ns logic, 1.954ns route) -------------------------------------------------------------------------------- Derived Constraint Report Derived Constraints for TS_TTC_REFCLK +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_TTC_REFCLK | 24.900ns| 16.000ns| 14.092ns| 0| 0| 0| 1123| | TS_TTCclk_dcm | 24.900ns| 14.092ns| N/A| 0| 0| 1123| 0| | TS_TO_TTC_data_1_LD | 24.900ns| N/A| N/A| 0| 0| 0| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_ipb_clk +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_ipb_clk | 32.000ns| 18.248ns| 4.950ns| 0| 0| 18488| 1| | TS_TO_CRC_0_LD | 32.000ns| 4.950ns| N/A| 0| 0| 1| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock TTC_REFCLK ------------+------------+------------+------------+------------+------------------+--------+ |Max Setup to| Process |Max Hold to | Process | | Clock | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | ------------+------------+------------+------------+------------+------------------+--------+ TTCdata_p | 7.697(R)| SLOW | -4.776(R)| FAST |TTCclk | -3.890| | 7.757(F)| SLOW | -4.851(F)| FAST |TTCclk | -3.890| ------------+------------+------------+------------+------------+------------------+--------+ Clock to Setup on destination clock FSIO_SCK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ FSIO_SCK | 6.329| | 7.963| 3.066| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock TTC_REFCLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ TTC_REFCLK | 7.848| 7.046| | | ---------------+---------+---------+---------+---------+ COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "RISING"; Worst Case Data Window 2.921; Ideal Clock Offset To Actual Clock -0.263; ------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | ------------------+------------+------------+------------+------------+---------+---------+-------------+ TTCdata_p | 7.697(R)| SLOW | -4.776(R)| FAST | 2.303| 1.776| 0.263| ------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary| 7.697| - | -4.776| - | 2.303| 1.776| | ------------------+------------+------------+------------+------------+---------+---------+-------------+ COMP "TTCdata_p" OFFSET = IN 10 ns VALID 7 ns BEFORE COMP "TTC_REFCLK" "FALLING"; Worst Case Data Window 2.906; Ideal Clock Offset To Actual Clock -0.196; ------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | ------------------+------------+------------+------------+------------+---------+---------+-------------+ TTCdata_p | -4.693(F)| SLOW | 7.599(F)| FAST | 2.243| 1.851| 0.196| ------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary| -4.693| - | 7.599| - | 2.243| 1.851| | ------------------+------------+------------+------------+------------+---------+---------+-------------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 86012 paths, 12 nets, and 24006 connections Design statistics: Minimum period: 18.248ns{1} (Maximum frequency: 54.801MHz) Maximum path delay from/to any node: 4.950ns Maximum net delay: 2.327ns Minimum input required time before clock: 7.757ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Tue Sep 22 23:49:43 2020 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 555 MB