Release 14.7 par P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. localhost.localdomain:: Tue Sep 22 23:46:18 2020 par -w -intstyle ise -ol high -mt off AMC13_T2_map.ncd AMC13_T2.ncd AMC13_T2.pcf Constraints file: AMC13_T2.pcf. Loading device for application Rf_Device from file '6slx45t.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/. "AMC13_T2" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -2 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc6slx45t' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.23 2013-10-13". Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 5,172 out of 54,576 9% Number used as Flip Flops: 5,169 Number used as Latches: 3 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 4,398 out of 27,288 16% Number used as logic: 4,141 out of 27,288 15% Number using O6 output only: 2,694 Number using O5 output only: 216 Number using O5 and O6: 1,231 Number used as ROM: 0 Number used as Memory: 28 out of 6,408 1% Number used as Dual Port RAM: 0 Number used as Single Port RAM: 0 Number used as Shift Register: 28 Number using O6 output only: 16 Number using O5 output only: 0 Number using O5 and O6: 12 Number used exclusively as route-thrus: 229 Number with same-slice register load: 210 Number with same-slice carry load: 19 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 1,731 out of 6,822 25% Number of MUXCYs used: 636 out of 13,644 4% Number of LUT Flip Flop pairs used: 5,453 Number with an unused Flip Flop: 1,240 out of 5,453 22% Number with an unused LUT: 1,055 out of 5,453 19% Number of fully used LUT-FF pairs: 3,158 out of 5,453 57% Number of slice register sites lost to control set restrictions: 0 out of 54,576 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 104 out of 296 35% Number of LOCed IOBs: 77 out of 104 74% IOB Flip Flops: 19 IOB Master Pads: 13 IOB Slave Pads: 13 Number of bonded IPADs: 6 out of 16 37% Number of LOCed IPADs: 6 out of 6 100% Number of bonded OPADs: 4 out of 8 50% Number of LOCed OPADs: 4 out of 4 100% Specific Feature Utilization: Number of RAMB16BWERs: 37 out of 116 31% Number of RAMB8BWERs: 0 out of 232 0% Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% Number used as BUFIO2s: 2 Number used as BUFIO2_2CLKs: 0 Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3% Number used as BUFIO2FBs: 1 Number used as BUFIO2FB_2CLKs: 0 Number of BUFG/BUFGMUXs: 7 out of 16 43% Number used as BUFGs: 7 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 2 out of 8 25% Number used as DCMs: 2 Number used as DCM_CLKGENs: 0 Number of ILOGIC2/ISERDES2s: 16 out of 376 4% Number used as ILOGIC2s: 16 Number used as ISERDES2s: 0 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0% Number of OLOGIC2/OSERDES2s: 3 out of 376 1% Number used as OLOGIC2s: 3 Number used as OSERDES2s: 0 Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 256 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 58 0% Number of GTPA1_DUALs: 1 out of 2 50% Number of ICAPs: 1 out of 1 100% Number of MCBs: 0 out of 2 0% Number of PCIE_A1s: 0 out of 1 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 4 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Overall effort level (-ol): High Router effort level (-rl): High WARNING:Timing:3223 - Timing constraint TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP "TO_TTC_data_1_LD" TS_TTCclk_dcm DATAPATHONLY; ignored during timing analysis. Starting initial Timing Analysis. REAL time: 29 secs Finished initial Timing Analysis. REAL time: 30 secs WARNING:Par:288 - The signal GPLED_B<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPLED_B<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPLED_B<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPLED_B<3>_IBUF has no load. PAR will not attempt to route this signal. Starting Router Phase 1 : 27724 unrouted; REAL time: 34 secs Phase 2 : 23533 unrouted; REAL time: 45 secs Phase 3 : 9764 unrouted; REAL time: 1 mins 35 secs Phase 4 : 9765 unrouted; (Setup:0, Hold:1980, Component Switching Limit:0) REAL time: 1 mins 45 secs Updating file: AMC13_T2.ncd with current fully routed design. Phase 5 : 0 unrouted; (Setup:0, Hold:1819, Component Switching Limit:0) REAL time: 2 mins 23 secs Phase 6 : 0 unrouted; (Setup:0, Hold:1819, Component Switching Limit:0) REAL time: 2 mins 23 secs Phase 7 : 0 unrouted; (Setup:0, Hold:1819, Component Switching Limit:0) REAL time: 2 mins 23 secs Phase 8 : 0 unrouted; (Setup:0, Hold:1819, Component Switching Limit:0) REAL time: 2 mins 23 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 29 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 34 secs Total REAL time to Router completion: 2 mins 34 secs Total CPU time to Router completion: 2 mins 28 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | sysclk | BUFGMUX_X3Y13| No | 1241 | 0.099 | 1.810 | +---------------------+--------------+------+------+------------+-------------+ | DNA_clk | BUFGMUX_X2Y4| No | 19 | 0.106 | 1.814 | +---------------------+--------------+------+------+------------+-------------+ | ipb_clk | BUFGMUX_X2Y2| No | 228 | 0.680 | 2.391 | +---------------------+--------------+------+------+------------+-------------+ | S6_SCK | BUFGMUX_X3Y15| No | 42 | 0.580 | 2.336 | +---------------------+--------------+------+------+------------+-------------+ | TTCclk | BUFGMUX_X2Y3| No | 56 | 0.705 | 2.414 | +---------------------+--------------+------+------+------------+-------------+ | ICAP_clk | BUFGMUX_X2Y12| No | 15 | 0.086 | 1.807 | +---------------------+--------------+------+------+------------+-------------+ | sysclk2x | BUFGMUX_X2Y1| No | 2 | 0.009 | 1.809 | +---------------------+--------------+------+------+------------+-------------+ | GbEGTPreset | Local| | 700 | 0.000 | 6.746 | +---------------------+--------------+------+------+------------+-------------+ | TTC_REFCLK_in | Local| | 2 | 0.000 | 3.983 | +---------------------+--------------+------+------+------------+-------------+ | TTC_lock_inv | Local| | 2 | 0.000 | 1.784 | +---------------------+--------------+------+------+------------+-------------+ |sysclk_dcm_locked_re | | | | | | | progV6_OR_86_o | Local| | 34 | 0.000 | 3.623 | +---------------------+--------------+------+------+------------+-------------+ |i_GTP_if/tile0_refcl | | | | | | | k_ibufds_i_ML_IBUF2 | Local| | 1 | 0.000 | 0.002 | +---------------------+--------------+------+------+------------+-------------+ |i_GTP_if/tile0_refcl | | | | | | | k_ibufds_i_ML_IBUF1 | Local| | 1 | 0.000 | 0.002 | +---------------------+--------------+------+------+------------+-------------+ | i_GTP_if/REFCLK | Local| | 2 | 0.000 | 0.002 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. * The fanout is the number of component pins not the individual BEL loads, for example SLICE loads not FF loads. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Number of Timing Constraints that were not applied: 4 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- TS_sysclk = PERIOD TIMEGRP "sysclk" 8 ns | SETUP | 0.466ns| 7.534ns| 0| 0 HIGH 50% | HOLD | 0.300ns| | 0| 0 | MINPERIOD | 0.000ns| 8.000ns| 0| 0 ---------------------------------------------------------------------------------------------------------- TS_sysclk2x = PERIOD TIMEGRP "sysclk2x" 4 | MINPERIOD | 0.297ns| 3.703ns| 0| 0 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<11>" MAXDELAY = 3 ns | MAXDELAY | 0.673ns| 2.327ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<12>" MAXDELAY = 3 ns | MAXDELAY | 0.678ns| 2.322ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<1>" MAXDELAY = 3 ns | MAXDELAY | 0.749ns| 2.251ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<2>" MAXDELAY = 3 ns | MAXDELAY | 1.202ns| 1.798ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<5>" MAXDELAY = 3 ns | MAXDELAY | 1.269ns| 1.731ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<10>" MAXDELAY = 3 ns | MAXDELAY | 1.502ns| 1.498ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<9>" MAXDELAY = 3 ns | MAXDELAY | 1.532ns| 1.468ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<3>" MAXDELAY = 3 ns | MAXDELAY | 1.566ns| 1.434ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<4>" MAXDELAY = 3 ns | MAXDELAY | 1.704ns| 1.296ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<7>" MAXDELAY = 3 ns | MAXDELAY | 1.710ns| 1.290ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<6>" MAXDELAY = 3 ns | MAXDELAY | 1.775ns| 1.225ns| 0| 0 ---------------------------------------------------------------------------------------------------------- NET "RxFB_in<8>" MAXDELAY = 3 ns | MAXDELAY | 1.835ns| 1.165ns| 0| 0 ---------------------------------------------------------------------------------------------------------- COMP "TTCdata_p" OFFSET = IN 10 ns VALID | SETUP | 2.243ns| 7.757ns| 0| 0 7 ns BEFORE COMP "TTC_REFCLK" "FA | HOLD | 1.851ns| | 0| 0 LLING" | | | | | ---------------------------------------------------------------------------------------------------------- COMP "TTCdata_p" OFFSET = IN 10 ns VALID | SETUP | 2.303ns| 7.697ns| 0| 0 7 ns BEFORE COMP "TTC_REFCLK" "RI | HOLD | 1.776ns| | 0| 0 SING" | | | | | ---------------------------------------------------------------------------------------------------------- TS_REFCLK_P = PERIOD TIMEGRP "REFCLK_P" 8 | MINPERIOD | 4.297ns| 3.703ns| 0| 0 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TTCclk_dcm = PERIOD TIMEGRP "TTCclk_dc | SETUP | 5.404ns| 14.092ns| 0| 0 m" TS_TTC_REFCLK PHASE -3.890625 ns | HOLD | 0.399ns| | 0| 0 HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_ipb_clk = PERIOD TIMEGRP "ipb_clk" 32 | SETUP | 6.876ns| 18.248ns| 0| 0 ns HIGH 50% | HOLD | 0.287ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- TS_TTC_REFCLK = PERIOD TIMEGRP "TTC_REFCL | MINLOWPULSE | 8.900ns| 16.000ns| 0| 0 K" 24.9 ns HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- TS_TO_CRC_0_LD = MAXDELAY TO TIMEGRP "TO_ | MAXDELAY | 27.050ns| 4.950ns| 0| 0 CRC_0_LD" TS_ipb_clk DATAPATHONLY | | | | | ---------------------------------------------------------------------------------------------------------- TS_FSIO_SCK = PERIOD TIMEGRP "FSIO_SCK" 2 | SETUP | 117.037ns| 15.926ns| 0| 0 50 ns HIGH 50% | HOLD | 0.413ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- TS_TO_TTC_data_1_LD = MAXDELAY TO TIMEGRP | N/A | N/A| N/A| N/A| N/A "TO_TTC_data_1_LD" TS_TTCclk_dcm | | | | | DATAPATHONLY | | | | | ---------------------------------------------------------------------------------------------------------- Derived Constraint Report Review Timing Report for more details on the following derived constraints. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" or "Run Timing Analysis" from Timing Analyzer (timingan). Derived Constraints for TS_TTC_REFCLK +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_TTC_REFCLK | 24.900ns| 16.000ns| 14.092ns| 0| 0| 0| 1123| | TS_TTCclk_dcm | 24.900ns| 14.092ns| N/A| 0| 0| 1123| 0| | TS_TO_TTC_data_1_LD | 24.900ns| N/A| N/A| 0| 0| 0| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_ipb_clk +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_ipb_clk | 32.000ns| 18.248ns| 4.950ns| 0| 0| 18488| 1| | TS_TO_CRC_0_LD | 32.000ns| 4.950ns| N/A| 0| 0| 1| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 4 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 2 mins 42 secs Total CPU time to PAR completion: 2 mins 35 secs Peak Memory Usage: 804 MB Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 7 Number of info messages: 0 Writing design to file AMC13_T2.ncd PAR done!