D0 STT workshop at Boston University
November 19, 1999

Agenda


Time Event Location
9:00 am Continental Breakfast PRB 591
9:30 am Morning Session PRB 591
Introduction U. Heintz 10'
Synchronization errors J. Linnemann 10'
PCI bus issues and
synchronization errors
E. Hazen 20'
LVDS link test U. Heintz 10'
Clustering (algorithm) M. Narain 15'
Clustering (VHDL) H. Wahl 10'
FRC status and L3 buffering H. Evans 20'
12:00 Lunch Faculty Club
1:30 pm Afternoon Session I PRB 591
TFC status and fitting algorithms J. Hobbs 25'
State of Altera studies W. Taylor 25'
DSP choices C. Pancake 10'
3:00 pm Coffee PRB 591
3:30 pm Afternoon Session II PRB 591
Track truncation studies G. Steinbrueck 10'
Schedule
Cost estimate
Design review
5:30 pm Adjourn