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Address | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | Name | Description
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0100 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.DTTRIG.SAMPLE_BUFFER_ENABLE | Trigger time alignment sample buffer when 1
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RECONFIGURE.BOTH | Start both V6 and S6 Configuration
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RECONFIGURE.T1ONLY | Start V6 configuration
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.GENERAL | bit 0 - general reset
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.TTC_COMMAND_HISTORY | clear TTC command history
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.TTC_FILTER_LIST | clear TTC command filter list
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0104 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DTTRIG.AMC_DELAY_d | Set delay in 1/8 BX steps for AMC input
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0x0101 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DTTRIG.ENABLE | Enable DT LUT trigger
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0x0200 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DTTRIG.LUT | Look-up table for trigger inputs (512 words)
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0x0102 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DTTRIG.TRIG0_DELAY | Set delay in 1/8 BX steps for TRIG0 input
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0x0103 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DTTRIG.TRIG1_DELAY | Set delay in 1/8 BX steps for TRIG1 input
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.FLASH.CMD | Sends data from Flash WBUF (clocks/8 – 1) to be sent
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0030 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.OCR_CMD | TTC OrN reset command
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0x0030 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.OCR_MASK | TTC OrN reset mask
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0x000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.OVERRIDE_MASK | Bitmask of additional locations to send TTC clock/data
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC_HISTORY.ENABLE | TTC history enable
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0x0020 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC_HISTORY.ENA_d | TTC history filter enable
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0x0020 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC_HISTORY.EXCL_CMD_d | TTC history command to exclude
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0x000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC_HISTORY.FILTER | TTC history filter enable
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0x0020 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC_HISTORY.FILTER_LIST | TTC history list base address
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0x0020 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC_HISTORY.MASK_CMD__d | TTC history command mask (1 to ignore bit)
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x1080 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FLASH_RBUF | Flash read buffer (buffer is R/W)
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0x1000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FLASH_WBUF | Flash write buffer (buffer is R/W)
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ID | Read IPBus version / address 0 alias
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0002 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC.ENABLE_MASK | Reads back what was written to Virtex 0x3
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0400 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.DTTRIG.SAMPLE_BUFFER | Sample buffer for DT trigger input alignment
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FIRMWARE_VERS | T2 Firmware Version Number
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FLASH.BUSY | bit 0 - flash I/O busy
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x000f |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.DNA_HI | Bits 32-56 of FPGA DNA
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0x000e |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.DNA_LO | Bits 0-31 of FPGA DNA
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.RECONFIGURE.CRC | configuration data CRC
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0x0003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.RECONFIGURE.T1_DONE | if '1', virtex chip DONE is low
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0x0003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.RECONFIGURE.T1_INIT_B | if '1', virtex chip INIT_B is low
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SERIAL_NO | T2 Serial Number
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x000a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.BC0_COUNTER | BC0 counter (always running)
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0x000b |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.BCNT | Bunch count (always running)
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0x0007 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.BCNT_ERROR | TTC Bunch count error counter (8 bits only)
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0x000c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.CLK_FREQ | TTC clock freq divided by 50
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0x000a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.L1A_COUNTER | L1A counter
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0x0005 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.LAST_BCN | TTC bunch count of last received L1A
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0x0004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.LAST_EVN | TTC event number of last received L1A
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0x0006 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.LAST_ORN | TTC orbit number of last received L1A
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0x0009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.MBIT_ERROR | TTC multi bit error count (8 bits only)
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0x0008 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.SBIT_ERROR | TTC single bit error count (8 bits only)
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x0800 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.BUFFER.BASE | TTC history buffer base address
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0x0802 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.BUFFER.BCN_d | TTC bunch number from history
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0x0800 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.BUFFER.CMD_d | TTC command from history
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0x0803 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.BUFFER.EVN_d | TTC EvN from history
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0x0801 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.BUFFER.ORN_d | TTC orbit number from history
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0x000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.COUNT | Number of entries or oldest entry in TTC history
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0x0011 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.COUNT_CMD_d | TTC command counter
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0x0010 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.ECR_COUNT | TTC reset event number command counter
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0x000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC_HISTORY.FULL | TTC history has at least 512 entries
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