Project Information e:\max2work\altera projects\centest\exp.rpt MAX+plus II Compiler Report File Version 9.24 4/19/99 Compiled: 01/07/2000 13:42:15 Copyright (C) 1988-1999 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Memory Memory LCs POF Device Pins Pins Pins Bits % Utilized LCs % Utilized exp EPF10K10ATC100-1 0 16 0 0 0 % 0 0 % User Pins: 0 16 0 Project Information e:\max2work\altera projects\centest\exp.rpt ** FILE HIERARCHY ** |lpm_constant:1| Device-Specific Information: e:\max2work\altera projects\centest\exp.rpt exp ***** Logic for device 'exp' compiled without errors. Device: EPF10K10ATC100-1 FLEX 10K Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = OFF JTAG User Code = 7f MultiVolt I/O = OFF R R R R R R R R R R R R R R R R E E E E E E E E E E E E E E E E S S S S S S V S S S S S S S S S S ^ E E E E E E C E E E E V E E E E E E D # R R R R R R C R R R R C R R R R R R A T V V V V G V V G G G G I V V V V C V V V V V V T C E E E E N E E N N N N N E E E E I E E E E E E A K D D D D D D D D D D D T D D D D O D D D D D D 0 ----------------------------------------------------_ / 100 98 96 94 92 90 88 86 84 82 80 78 76 |_ / 99 97 95 93 91 89 87 85 83 81 79 77 | ^CONF_DONE | 1 75 | ^DCLK ^nCEO | 2 74 | ^nCE #TDO | 3 73 | #TDI VCCIO | 4 72 | GND 0 | 5 71 | 9 14 | 6 70 | 8 13 | 7 69 | 7 12 | 8 68 | 6 11 | 9 67 | VCCIO 10 | 10 66 | VCCINT GND | 11 65 | 1 GND | 12 64 | 15 5 | 13 EPF10K10ATC100-1 63 | RESERVED 4 | 14 62 | RESERVED 3 | 15 61 | RESERVED 2 | 16 60 | GND VCCIO | 17 59 | GND VCCINT | 18 58 | RESERVED RESERVED | 19 57 | RESERVED RESERVED | 20 56 | RESERVED RESERVED | 21 55 | RESERVED RESERVED | 22 54 | ^MSEL0 RESERVED | 23 53 | ^MSEL1 #TMS | 24 52 | VCCINT ^nSTATUS | 25 51 | ^nCONFIG | 27 29 31 33 35 37 39 41 43 45 47 49 _| \ 26 28 30 32 34 36 38 40 42 44 46 48 50 | \----------------------------------------------------- R R G R R R V R R R R V G G G G R R R R G R R V R E E N E E E C E E E E C N N N N E E E E N E E C E S S D S S S C S S S S C D D D D S S S S D S S C S E E E E E I E E E E I E E E E E E I E R R R R R O R R R R N R R R R R R O R V V V V V V V V V T V V V V V V V E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D N.C. = No Connect, This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. $ = Pin has PCI I/O option enabled. Pin is not '5.0 V'-tolerant. Device-Specific Information: e:\max2work\altera projects\centest\exp.rpt exp ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets Interconnect Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write Interconnect Total dedicated input pins used: 0/6 ( 0%) Total I/O pins used: 16/60 ( 26%) Total logic cells used: 0/576 ( 0%) Total embedded cells used: 0/24 ( 0%) Total EABs used: 0/3 ( 0%) Average fan-in: 0.00/4 ( 0%) Total fan-in: 0/2304 ( 0%) Total input pins required: 0 Total input I/O cell registers required: 0 Total output pins required: 16 Total output I/O cell registers required: 0 Total buried I/O cell registers required: 0 Total bidirectional pins required: 0 Total reserved pins required 0 Total logic cells required: 0 Total flipflops required: 0 Total packed registers required: 0 Total logic cells in carry chains: 0 Total number of carry chains: 0 Total logic cells in cascade chains: 0 Total number of cascade chains: 0 Total single-pin Clock Enables required: 0 Total single-pin Output Enables required: 0 Synthesized logic cells: 0/ 576 ( 0%) Logic Cell and Embedded Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC) A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 Device-Specific Information: e:\max2work\altera projects\centest\exp.rpt exp ** INPUTS ** Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable None. Device-Specific Information: e:\max2work\altera projects\centest\exp.rpt exp ** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 5 - - A -- OUTPUT 0 0 0 0 0 65 - - B -- OUTPUT 0 0 0 0 1 16 - - B -- OUTPUT 0 0 0 0 2 15 - - B -- OUTPUT 0 0 0 0 3 14 - - B -- OUTPUT 0 0 0 0 4 13 - - B -- OUTPUT 0 0 0 0 5 68 - - A -- OUTPUT 0 0 0 0 6 69 - - A -- OUTPUT 0 0 0 0 7 70 - - A -- OUTPUT 0 0 0 0 8 71 - - A -- OUTPUT 0 0 0 0 9 10 - - A -- OUTPUT 0 0 0 0 10 9 - - A -- OUTPUT 0 0 0 0 11 8 - - A -- OUTPUT 0 0 0 0 12 7 - - A -- OUTPUT 0 0 0 0 13 6 - - A -- OUTPUT 0 0 0 0 14 64 - - B -- OUTPUT 0 0 0 0 15 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information: e:\max2work\altera projects\centest\exp.rpt exp ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 10/16( 62%) 0/16( 0%) B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%) C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) Device-Specific Information: e:\max2work\altera projects\centest\exp.rpt exp ** EQUATIONS ** -- Node name is '0' -- Equation name is '0', type is output 0 = GND; -- Node name is '1' -- Equation name is '1', type is output 1 = VCC; -- Node name is '2' -- Equation name is '2', type is output 2 = GND; -- Node name is '3' -- Equation name is '3', type is output 3 = VCC; -- Node name is '4' -- Equation name is '4', type is output 4 = GND; -- Node name is '5' -- Equation name is '5', type is output 5 = VCC; -- Node name is '6' -- Equation name is '6', type is output 6 = GND; -- Node name is '7' -- Equation name is '7', type is output 7 = VCC; -- Node name is '8' -- Equation name is '8', type is output 8 = GND; -- Node name is '9' -- Equation name is '9', type is output 9 = VCC; -- Node name is '10' -- Equation name is '10', type is output 10 = GND; -- Node name is '11' -- Equation name is '11', type is output 11 = VCC; -- Node name is '12' -- Equation name is '12', type is output 12 = GND; -- Node name is '13' -- Equation name is '13', type is output 13 = VCC; -- Node name is '14' -- Equation name is '14', type is output 14 = GND; -- Node name is '15' -- Equation name is '15', type is output 15 = VCC; Project Information e:\max2work\altera projects\centest\exp.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'FLEX10KA' family CARRY_CHAIN = ignore CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = ignore CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = on IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = off Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:01 Partitioner 00:00:02 Fitter 00:00:01 Timing SNF Extractor 00:00:00 Assembler 00:00:01 -------------------------- -------- Total Time 00:00:05 Memory Allocated ----------------- Peak memory allocated during compilation = 14,487K