Project Information d:\max2work\altera projects\alayer\convert.rpt MAX+plus II Compiler Report File Version 9.03 9/18/98 Compiled: 02/23/99 15:34:29 Copyright (C) 1988-1998 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful Untitled ** DEVICE SUMMARY ** Chip/ Input Output Bidir Memory Memory LCs POF Device Pins Pins Pins Bits % Utilized LCs % Utilized convert EPF10K50VBC356-1 96 96 0 0 0 % 96 3 % User Pins: 96 96 0 Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ***** Logic for device 'convert' compiled without errors. Device: EPF10K50VBC356-1 FLEX 10K Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = OFF JTAG User Code = 7f Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** ERROR SUMMARY ** Info: If you believe you may migrate this design project to the FLEX 10KE family, you should consult Altera Applications to determine the proper I/O configuration to ensure compatibility. ---------------------------------------------------------------------------------- | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 | |AF o o o o o o o o o o o o o o o o o o o o o o o o o o AF| |AE o o o o o o o o o o o o o o o o o o o o o o o o o o AE| |AD o o o o o o o o o o o o o o o o o o o o o o o o o o AD| |AC o o o o o o o o o o AC| |AB o o o o o o o o o o AB| |AA o o o o o o o o o o AA| |Y o o o o o o o o o o Y| |W o o o o o o o o o o W| |V o o o o o o o o o o V| |U o o o o o o o o o o U| |T o o o o o o o o o o T| |R o o o o o o o o o o R| |P o o o o o o o o o o P| |N o o o o o o o o o o N| |M o o o o o o o o o o M| |L o o o o o o o o o o L| |K o o o o o o o o o o K| |J o o o o o o o o o o J| |H o o o o o o o o o o H| |G o o o o o o o o o o G| |F o o o o o o o o o o F| |E o o o o o o o o o o E| |D o o o o o o o o o o D| |C o o o o o o o o o o o o o o o o o o o o o o o o o o C| |B o o o o o o o o o o o o o o o o o o o o o o o o o o B| |A o o o o o o o o o o o o o o o o o o o o o o o o o o A| | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 | ---------------------------------------------------------------------------------- EPF10K50VBC356-1 Bottom View Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert A1 VCCINT C21 OUT93 K23 INP70 U25 INP50 AD11 OUT27 A2 GNDINT C22 RESERVED K24 INP25 U26 GNDINT AD12 OUT4 A3 OUT9 C23 RESERVED K25 INP10 V1 OUT60 AD13 RESERVED A4 RESERVED C24 RESERVED K26 INP85 V2 VCCIO AD14 GNDINT A5 RESERVED C25 GNDINT L1 OUT87 V3 OUT63 AD15 OUT19 A6 RESERVED C26 VCCINT L2 OUT41 V4 OUT3 AD16 OUT16 A7 VCCIO D1 OUT44 L3 OUT7 V5 OUT59 AD17 RESERVED A8 RESERVED D2 ^nCONFIG L4 OUT83 V22 INP2 AD18 VCCIO A9 RESERVED D3 ^MSEL1 L5 OUT53 V23 INP9 AD19 RESERVED A10 GNDINT D4 ^MSEL0 L22 INP81 V24 INP47 AD20 GNDINT A11 RESERVED D5 VCCINT L23 INP48 V25 INP28 AD21 RESERVED A12 RESERVED D22 #TMS L24 INP75 V26 INP88 AD22 RESERVED A13 INP65 D23 #nTRST L25 INP19 W1 GNDINT AD23 OUT22 A14 INP67 D24 ^nSTATUS L26 INP60 W2 OUT47 AD24 RESERVED A15 RESERVED D25 VCCIO M1 GNDINT W3 OUT79 AD25 #TCK A16 RESERVED D26 INP37 M2 OUT66 W4 OUT33 AD26 VCCINT A17 RESERVED E1 OUT76 M3 OUT52 W5 OUT62 AE1 GNDINT A18 RESERVED E2 OUT10 M4 OUT6 W22 VCCIO AE2 GNDINT A19 RESERVED E3 OUT56 M5 OUT96 W23 INP59 AE3 RESERVED A20 GNDINT E4 OUT30 M22 INP21 W24 INP90 AE4 RESERVED A21 RESERVED E5 OUT70 M23 VCCIO W25 INP84 AE5 RESERVED A22 RESERVED E22 INP16 M24 INP15 W26 INP43 AE6 RESERVED A23 VCCIO E23 INP22 M25 INP77 Y1 INP34 AE7 GNDINT A24 OUT17 E24 INP49 M26 VCCINT Y2 OUT61 AE8 RESERVED A25 RESERVED E25 INP78 N1 VCCINT Y3 OUT58 AE9 OUT14 A26 VCCINT E26 INP87 N2 OUT82 Y4 OUT46 AE10 RESERVED B1 GNDINT F1 VCCINT N3 INP6 Y5 OUT78 AE11 RESERVED B2 RESERVED F2 OUT48 N4 OUT40 Y22 INP93 AE12 RESERVED B3 RESERVED F3 OUT89 N5 INP40 Y23 INP86 AE13 INP63 B4 VCCIO F4 VCCIO N22 INP52 Y24 INP80 AE14 OUT94 B5 RESERVED F5 INP31 N23 INP56 Y25 INP5 AE15 OUT15 B6 RESERVED F22 INP72 N24 INP96 Y26 INP24 AE16 RESERVED B7 RESERVED F23 INP53 N25 INP62 AA1 VCCINT AE17 RESERVED B8 OUT26 F24 INP27 N26 GNDINT AA2 OUT32 AE18 OUT20 B9 RESERVED F25 INP12 P1 OUT35 AA3 INP30 AE19 OUT92 B10 RESERVED F26 INP18 P2 VCCIO AA4 INP39 AE20 OUT25 B11 RESERVED G1 OUT69 P3 OUT65 AA5 OUT91 AE21 RESERVED B12 RESERVED G2 OUT43 P4 OUT51 AA22 INP45 AE22 RESERVED B13 GNDINT G3 OUT75 P5 OUT73 AA23 INP26 AE23 RESERVED B14 INP64 G4 OUT29 P22 INP11 AA24 INP61 AE24 OUT18 B15 RESERVED G5 OUT55 P23 INP42 AA25 INP51 AE25 GNDINT B16 OUT23 G22 INP94 P24 INP4 AA26 INP55 AE26 GNDINT B17 RESERVED G23 INP83 P25 INP46 AB1 VCCIO AF1 VCCINT B18 OUT24 G24 INP89 P26 INP71 AB2 OUT57 AF2 OUT5 B19 RESERVED G25 INP74 R1 GNDINT AB3 OUT11 AF3 VCCIO B20 RESERVED G26 INP68 R2 OUT81 AB4 OUT71 AF4 RESERVED B21 RESERVED H1 OUT8 R3 INP36 AB5 OUT45 AF5 RESERVED B22 GNDINT H2 OUT49 R4 OUT36 AB22 INP91 AF6 OUT86 B23 RESERVED H3 OUT54 R5 OUT39 AB23 INP76 AF7 VCCIO B24 RESERVED H4 OUT28 R22 INP58 AB24 INP82 AF8 RESERVED B25 GNDINT H5 INP33 R23 INP73 AB25 INP20 AF9 OUT90 B26 GNDINT H22 VCCINT R24 INP92 AB26 INP41 AF10 RESERVED C1 OUT13 H23 GNDINT R25 INP17 AC1 OUT31 AF11 GNDINT C2 GNDINT H24 VCCIO R26 GNDINT AC2 ^nCE AF12 RESERVED C3 RESERVED H25 INP29 T1 GNDINT AC3 #TDI AF13 INP66 C4 RESERVED H26 INP8 T2 OUT64 AC4 INP35 AF14 INP1 C5 RESERVED J1 VCCINT T3 OUT50 AC5 ^DCLK AF15 RESERVED C6 RESERVED J2 OUT88 T4 OUT72 AC22 ^nCEO AF16 VCCIO C7 RESERVED J3 OUT42 T5 OUT34 AC23 #TDO AF17 RESERVED C8 RESERVED J4 OUT74 T22 INP13 AC24 ^CONF_DONEAF18 RESERVED C9 GNDINT J5 OUT68 T23 INP7 AC25 VCCIO AF19 GNDINT C10 RESERVED J22 INP23 T24 INP38 AC26 INP57 AF20 OUT95 C11 RESERVED J23 INP3 T25 VCCIO AD1 OUT77 AF21 RESERVED C12 RESERVED J24 INP14 T26 VCCINT AD2 GNDINT AF22 RESERVED C13 GNDINT J25 INP79 U1 OUT80 AD3 ^DATA0 AF23 OUT85 C14 VCCINT J26 GNDINT U2 OUT37 AD4 OUT1 AF24 RESERVED C15 VCCIO K1 GNDINT U3 OUT38 AD5 OUT12 AF25 GNDINT C16 RESERVED K2 OUT67 U4 INP32 AD6 RESERVED AF26 VCCINT C17 RESERVED K3 OUT21 U5 VCCINT AD7 RESERVED C18 RESERVED K4 OUT84 U22 INP69 AD8 OUT2 C19 RESERVED K5 VCCIO U23 INP54 AD9 RESERVED C20 RESERVED K22 INP44 U24 INP95 AD10 RESERVED N.C. = Not Connected. VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts). GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. GNDIO = Dedicated ground pin, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs (TMS, TCK, TDI) should be tied to VCC when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets Interconnect A1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) A2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) A3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) A19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) A20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) A21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) A22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) A23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) B25 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) B26 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B27 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) B28 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) C30 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) C31 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C32 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C33 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) D1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) D16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) D17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) D18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) D19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) D20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) D34 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) D35 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) D36 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) E4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) E22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) E25 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) F8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) F9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) F10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) F11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) F12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) F26 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) F27 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) F28 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) F29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) F30 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) G15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G31 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G32 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G33 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) G34 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) H35 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) H36 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) I6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) I22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) I24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) J12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%) J25 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J26 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J27 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) J28 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write Interconnect Total dedicated input pins used: 6/6 (100%) Total I/O pins used: 186/268 ( 69%) Total logic cells used: 96/2880 ( 3%) Total embedded cells used: 0/80 ( 0%) Total EABs used: 0/10 ( 0%) Average fan-in: 1.00/4 ( 25%) Total fan-in: 96/11520 ( 0%) Total input pins required: 96 Total input I/O cell registers required: 0 Total output pins required: 96 Total output I/O cell registers required: 0 Total buried I/O cell registers required: 0 Total bidirectional pins required: 0 Total reserved pins required 0 Total logic cells required: 96 Total flipflops required: 0 Total packed registers required: 0 Total logic cells in carry chains: 0 Total number of carry chains: 0 Total logic cells in cascade chains: 0 Total number of cascade chains: 0 Total single-pin Clock Enables required: 0 Total single-pin Output Enables required: 0 Synthesized logic cells: 96/2880 ( 3%) Logic Cell and Embedded Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC) A: 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 10/0 B: 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 10/0 C: 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 10/0 D: 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 10/0 E: 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 10/0 F: 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 10/0 G: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 9/0 H: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 9/0 I: 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 9/0 J: 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 9/0 Total: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 0 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 96/0 Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** INPUTS ** Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name AF14 - - - -- INPUT 0 0 0 1 INP1 V22 - - C -- INPUT 0 0 0 1 INP2 J23 - - H -- INPUT 0 0 0 1 INP3 P24 - - E -- INPUT 0 0 0 1 INP4 Y25 - - B -- INPUT 0 0 0 1 INP5 N3 - - F -- INPUT 0 0 0 1 INP6 T23 - - D -- INPUT 0 0 0 1 INP7 H26 - - H -- INPUT 0 0 0 1 INP8 V23 - - C -- INPUT 0 0 0 1 INP9 K25 - - G -- INPUT 0 0 0 1 INP10 P22 - - E -- INPUT 0 0 0 1 INP11 F25 - - I -- INPUT 0 0 0 1 INP12 T22 - - D -- INPUT 0 0 0 1 INP13 J24 - - H -- INPUT 0 0 0 1 INP14 M24 - - F -- INPUT 0 0 0 1 INP15 E22 - - J -- INPUT 0 0 0 1 INP16 R25 - - E -- INPUT 0 0 0 1 INP17 F26 - - I -- INPUT 0 0 0 1 INP18 L25 - - G -- INPUT 0 0 0 1 INP19 AB25 - - A -- INPUT 0 0 0 1 INP20 M22 - - F -- INPUT 0 0 0 1 INP21 E23 - - J -- INPUT 0 0 0 1 INP22 J22 - - H -- INPUT 0 0 0 1 INP23 Y26 - - B -- INPUT 0 0 0 1 INP24 K24 - - G -- INPUT 0 0 0 1 INP25 AA23 - - A -- INPUT 0 0 0 1 INP26 F24 - - I -- INPUT 0 0 0 1 INP27 V25 - - C -- INPUT 0 0 0 1 INP28 H25 - - H -- INPUT 0 0 0 1 INP29 AA3 - - B -- INPUT 0 0 0 1 INP30 F5 - - J -- INPUT 0 0 0 1 INP31 U4 - - D -- INPUT 0 0 0 1 INP32 H5 - - I -- INPUT 0 0 0 1 INP33 Y1 - - C -- INPUT 0 0 0 1 INP34 AC4 - - A -- INPUT 0 0 0 1 INP35 R3 - - E -- INPUT 0 0 0 1 INP36 D26 - - J -- INPUT 0 0 0 1 INP37 T24 - - D -- INPUT 0 0 0 1 INP38 AA4 - - B -- INPUT 0 0 0 1 INP39 N5 - - F -- INPUT 0 0 0 1 INP40 AB26 - - A -- INPUT 0 0 0 1 INP41 P23 - - E -- INPUT 0 0 0 1 INP42 W26 - - C -- INPUT 0 0 0 1 INP43 K22 - - G -- INPUT 0 0 0 1 INP44 AA22 - - A -- INPUT 0 0 0 1 INP45 P25 - - E -- INPUT 0 0 0 1 INP46 V24 - - C -- INPUT 0 0 0 1 INP47 L23 - - G -- INPUT 0 0 0 1 INP48 E24 - - J -- INPUT 0 0 0 1 INP49 U25 - - D -- INPUT 0 0 0 1 INP50 AA25 - - B -- INPUT 0 0 0 1 INP51 N22 - - F -- INPUT 0 0 0 1 INP52 F23 - - J -- INPUT 0 0 0 1 INP53 U23 - - D -- INPUT 0 0 0 1 INP54 AA26 - - B -- INPUT 0 0 0 1 INP55 N23 - - F -- INPUT 0 0 0 1 INP56 AC26 - - A -- INPUT 0 0 0 1 INP57 R22 - - E -- INPUT 0 0 0 1 INP58 W23 - - C -- INPUT 0 0 0 1 INP59 L26 - - G -- INPUT 0 0 0 1 INP60 AA24 - - B -- INPUT 0 0 0 1 INP61 N25 - - F -- INPUT 0 0 0 1 INP62 AE13 - - - -- INPUT 0 0 0 1 INP63 B14 - - - -- INPUT 0 0 0 1 INP64 A13 - - - -- INPUT 0 0 0 1 INP65 AF13 - - - -- INPUT 0 0 0 1 INP66 A14 - - - -- INPUT 0 0 0 1 INP67 G26 - - I -- INPUT 0 0 0 1 INP68 U22 - - D -- INPUT 0 0 0 1 INP69 K23 - - H -- INPUT 0 0 0 1 INP70 P26 - - F -- INPUT 0 0 0 1 INP71 F22 - - J -- INPUT 0 0 0 1 INP72 R23 - - E -- INPUT 0 0 0 1 INP73 G25 - - I -- INPUT 0 0 0 1 INP74 L24 - - G -- INPUT 0 0 0 1 INP75 AB23 - - A -- INPUT 0 0 0 1 INP76 M25 - - F -- INPUT 0 0 0 1 INP77 E25 - - J -- INPUT 0 0 0 1 INP78 J25 - - H -- INPUT 0 0 0 1 INP79 Y24 - - B -- INPUT 0 0 0 1 INP80 L22 - - G -- INPUT 0 0 0 1 INP81 AB24 - - A -- INPUT 0 0 0 1 INP82 G23 - - I -- INPUT 0 0 0 1 INP83 W25 - - C -- INPUT 0 0 0 1 INP84 K26 - - H -- INPUT 0 0 0 1 INP85 Y23 - - B -- INPUT 0 0 0 1 INP86 E26 - - J -- INPUT 0 0 0 1 INP87 V26 - - D -- INPUT 0 0 0 1 INP88 G24 - - I -- INPUT 0 0 0 1 INP89 W24 - - C -- INPUT 0 0 0 1 INP90 AB22 - - A -- INPUT 0 0 0 1 INP91 R24 - - E -- INPUT 0 0 0 1 INP92 Y22 - - B -- INPUT 0 0 0 1 INP93 G22 - - I -- INPUT 0 0 0 1 INP94 U24 - - D -- INPUT 0 0 0 1 INP95 N24 - - F -- INPUT 0 0 0 1 INP96 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name AD4 - - - 01 OUTPUT 0 1 0 0 OUT1 AD8 - - - 06 OUTPUT 0 1 0 0 OUT2 V4 - - C -- OUTPUT 0 1 0 0 OUT3 AD12 - - - 16 OUTPUT 0 1 0 0 OUT4 AF2 - - - 03 OUTPUT 0 1 0 0 OUT5 M4 - - F -- OUTPUT 0 1 0 0 OUT6 L3 - - G -- OUTPUT 0 1 0 0 OUT7 H1 - - H -- OUTPUT 0 1 0 0 OUT8 A3 - - - 05 OUTPUT 0 1 0 0 OUT9 E2 - - J -- OUTPUT 0 1 0 0 OUT10 AB3 - - A -- OUTPUT 0 1 0 0 OUT11 AD5 - - - 02 OUTPUT 0 1 0 0 OUT12 C1 - - J -- OUTPUT 0 1 0 0 OUT13 AE9 - - - 11 OUTPUT 0 1 0 0 OUT14 AE15 - - - 20 OUTPUT 0 1 0 0 OUT15 AD16 - - - 24 OUTPUT 0 1 0 0 OUT16 A24 - - - 29 OUTPUT 0 1 0 0 OUT17 AE24 - - - 34 OUTPUT 0 1 0 0 OUT18 AD15 - - - 21 OUTPUT 0 1 0 0 OUT19 AE18 - - - 26 OUTPUT 0 1 0 0 OUT20 K3 - - G -- OUTPUT 0 1 0 0 OUT21 AD23 - - - 35 OUTPUT 0 1 0 0 OUT22 B16 - - - 21 OUTPUT 0 1 0 0 OUT23 B18 - - - 25 OUTPUT 0 1 0 0 OUT24 AE20 - - - 30 OUTPUT 0 1 0 0 OUT25 B8 - - - 09 OUTPUT 0 1 0 0 OUT26 AD11 - - - 13 OUTPUT 0 1 0 0 OUT27 H4 - - H -- OUTPUT 0 1 0 0 OUT28 G4 - - I -- OUTPUT 0 1 0 0 OUT29 E4 - - J -- OUTPUT 0 1 0 0 OUT30 AC1 - - A -- OUTPUT 0 1 0 0 OUT31 AA2 - - B -- OUTPUT 0 1 0 0 OUT32 W4 - - C -- OUTPUT 0 1 0 0 OUT33 T5 - - D -- OUTPUT 0 1 0 0 OUT34 P1 - - E -- OUTPUT 0 1 0 0 OUT35 R4 - - E -- OUTPUT 0 1 0 0 OUT36 U2 - - D -- OUTPUT 0 1 0 0 OUT37 U3 - - D -- OUTPUT 0 1 0 0 OUT38 R5 - - E -- OUTPUT 0 1 0 0 OUT39 N4 - - F -- OUTPUT 0 1 0 0 OUT40 L2 - - G -- OUTPUT 0 1 0 0 OUT41 J3 - - H -- OUTPUT 0 1 0 0 OUT42 G2 - - I -- OUTPUT 0 1 0 0 OUT43 D1 - - J -- OUTPUT 0 1 0 0 OUT44 AB5 - - A -- OUTPUT 0 1 0 0 OUT45 Y4 - - B -- OUTPUT 0 1 0 0 OUT46 W2 - - C -- OUTPUT 0 1 0 0 OUT47 F2 - - I -- OUTPUT 0 1 0 0 OUT48 H2 - - H -- OUTPUT 0 1 0 0 OUT49 T3 - - D -- OUTPUT 0 1 0 0 OUT50 P4 - - E -- OUTPUT 0 1 0 0 OUT51 M3 - - F -- OUTPUT 0 1 0 0 OUT52 L5 - - G -- OUTPUT 0 1 0 0 OUT53 H3 - - H -- OUTPUT 0 1 0 0 OUT54 G5 - - I -- OUTPUT 0 1 0 0 OUT55 E3 - - J -- OUTPUT 0 1 0 0 OUT56 AB2 - - A -- OUTPUT 0 1 0 0 OUT57 Y3 - - B -- OUTPUT 0 1 0 0 OUT58 V5 - - C -- OUTPUT 0 1 0 0 OUT59 V1 - - C -- OUTPUT 0 1 0 0 OUT60 Y2 - - B -- OUTPUT 0 1 0 0 OUT61 W5 - - B -- OUTPUT 0 1 0 0 OUT62 V3 - - C -- OUTPUT 0 1 0 0 OUT63 T2 - - D -- OUTPUT 0 1 0 0 OUT64 P3 - - E -- OUTPUT 0 1 0 0 OUT65 M2 - - F -- OUTPUT 0 1 0 0 OUT66 K2 - - G -- OUTPUT 0 1 0 0 OUT67 J5 - - H -- OUTPUT 0 1 0 0 OUT68 G1 - - I -- OUTPUT 0 1 0 0 OUT69 E5 - - J -- OUTPUT 0 1 0 0 OUT70 AB4 - - A -- OUTPUT 0 1 0 0 OUT71 T4 - - D -- OUTPUT 0 1 0 0 OUT72 P5 - - E -- OUTPUT 0 1 0 0 OUT73 J4 - - H -- OUTPUT 0 1 0 0 OUT74 G3 - - I -- OUTPUT 0 1 0 0 OUT75 E1 - - J -- OUTPUT 0 1 0 0 OUT76 AD1 - - A -- OUTPUT 0 1 0 0 OUT77 Y5 - - B -- OUTPUT 0 1 0 0 OUT78 W3 - - C -- OUTPUT 0 1 0 0 OUT79 U1 - - D -- OUTPUT 0 1 0 0 OUT80 R2 - - E -- OUTPUT 0 1 0 0 OUT81 N2 - - F -- OUTPUT 0 1 0 0 OUT82 L4 - - G -- OUTPUT 0 1 0 0 OUT83 K4 - - G -- OUTPUT 0 1 0 0 OUT84 AF23 - - - 29 OUTPUT 0 1 0 0 OUT85 AF6 - - - 12 OUTPUT 0 1 0 0 OUT86 L1 - - G -- OUTPUT 0 1 0 0 OUT87 J2 - - H -- OUTPUT 0 1 0 0 OUT88 F3 - - I -- OUTPUT 0 1 0 0 OUT89 AF9 - - - 14 OUTPUT 0 1 0 0 OUT90 AA5 - - A -- OUTPUT 0 1 0 0 OUT91 AE19 - - - 28 OUTPUT 0 1 0 0 OUT92 C21 - - - 33 OUTPUT 0 1 0 0 OUT93 AE14 - - - 19 OUTPUT 0 1 0 0 OUT94 AF20 - - - 25 OUTPUT 0 1 0 0 OUT95 M5 - - F -- OUTPUT 0 1 0 0 OUT96 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** BURIED LOGIC ** Fan-In Fan-Out IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - 1 - A 01 LCELL s 1 0 1 0 OUT1~1 - 1 - B 06 LCELL s 1 0 1 0 OUT2~1 - 7 - C 11 LCELL s 1 0 1 0 OUT3~1 - 1 - D 16 LCELL s 1 0 1 0 OUT4~1 - 1 - E 03 LCELL s 1 0 1 0 OUT5~1 - 7 - F 08 LCELL s 1 0 1 0 OUT6~1 - 6 - G 13 LCELL s 1 0 1 0 OUT7~1 - 7 - H 18 LCELL s 1 0 1 0 OUT8~1 - 1 - I 05 LCELL s 1 0 1 0 OUT9~1 - 6 - J 10 LCELL s 1 0 1 0 OUT10~1 - 7 - A 19 LCELL s 1 0 1 0 OUT11~1 - 1 - A 02 LCELL s 1 0 1 0 OUT12~1 - 8 - J 25 LCELL s 1 0 1 0 OUT13~1 - 1 - J 11 LCELL s 1 0 1 0 OUT14~1 - 1 - A 20 LCELL s 1 0 1 0 OUT15~1 - 1 - B 24 LCELL s 1 0 1 0 OUT16~1 - 1 - C 29 LCELL s 1 0 1 0 OUT17~1 - 1 - D 34 LCELL s 1 0 1 0 OUT18~1 - 1 - E 21 LCELL s 1 0 1 0 OUT19~1 - 1 - F 26 LCELL s 1 0 1 0 OUT20~1 - 7 - G 31 LCELL s 1 0 1 0 OUT21~1 - 1 - H 35 LCELL s 1 0 1 0 OUT22~1 - 1 - I 21 LCELL s 1 0 1 0 OUT23~1 - 1 - B 25 LCELL s 1 0 1 0 OUT24~1 - 1 - C 30 LCELL s 1 0 1 0 OUT25~1 - 1 - F 09 LCELL s 1 0 1 0 OUT26~1 - 1 - G 14 LCELL s 1 0 1 0 OUT27~1 - 7 - H 01 LCELL s 1 0 1 0 OUT28~1 - 3 - I 06 LCELL s 1 0 1 0 OUT29~1 - 3 - J 12 LCELL s 1 0 1 0 OUT30~1 - 4 - A 21 LCELL s 1 0 1 0 OUT31~1 - 3 - B 26 LCELL s 1 0 1 0 OUT32~1 - 2 - C 31 LCELL s 1 0 1 0 OUT33~1 - 5 - D 35 LCELL s 1 0 1 0 OUT34~1 - 5 - E 22 LCELL s 1 0 1 0 OUT35~1 - 2 - E 04 LCELL s 1 0 1 0 OUT36~1 - 3 - D 17 LCELL s 1 0 1 0 OUT37~1 - 1 - D 36 LCELL s 1 0 1 0 OUT38~1 - 2 - E 23 LCELL s 1 0 1 0 OUT39~1 - 3 - F 27 LCELL s 1 0 1 0 OUT40~1 - 1 - G 32 LCELL s 1 0 1 0 OUT41~1 - 1 - H 36 LCELL s 1 0 1 0 OUT42~1 - 1 - I 22 LCELL s 1 0 1 0 OUT43~1 - 2 - J 26 LCELL s 1 0 1 0 OUT44~1 - 3 - A 03 LCELL s 1 0 1 0 OUT45~1 - 5 - B 07 LCELL s 1 0 1 0 OUT46~1 - 3 - C 12 LCELL s 1 0 1 0 OUT47~1 - 7 - I 07 LCELL s 1 0 1 0 OUT48~1 - 5 - H 02 LCELL s 1 0 1 0 OUT49~1 - 7 - D 19 LCELL s 1 0 1 0 OUT50~1 - 7 - E 24 LCELL s 1 0 1 0 OUT51~1 - 5 - F 28 LCELL s 1 0 1 0 OUT52~1 - 4 - G 33 LCELL s 1 0 1 0 OUT53~1 - 6 - H 19 LCELL s 1 0 1 0 OUT54~1 - 6 - I 23 LCELL s 1 0 1 0 OUT55~1 - 5 - J 27 LCELL s 1 0 1 0 OUT56~1 - 5 - A 04 LCELL s 1 0 1 0 OUT57~1 - 5 - B 08 LCELL s 1 0 1 0 OUT58~1 - 5 - C 13 LCELL s 1 0 1 0 OUT59~1 - 5 - C 32 LCELL s 1 0 1 0 OUT60~1 - 7 - B 27 LCELL s 1 0 1 0 OUT61~1 - 8 - B 09 LCELL s 1 0 1 0 OUT62~1 - 7 - C 14 LCELL s 1 0 1 0 OUT63~1 - 7 - D 18 LCELL s 1 0 1 0 OUT64~1 - 6 - E 05 LCELL s 1 0 1 0 OUT65~1 - 5 - F 10 LCELL s 1 0 1 0 OUT66~1 - 3 - G 15 LCELL s 1 0 1 0 OUT67~1 - 4 - H 03 LCELL s 1 0 1 0 OUT68~1 - 5 - I 08 LCELL s 1 0 1 0 OUT69~1 - 6 - J 13 LCELL s 1 0 1 0 OUT70~1 - 5 - A 22 LCELL s 1 0 1 0 OUT71~1 - 6 - D 01 LCELL s 1 0 1 0 OUT72~1 - 6 - E 06 LCELL s 1 0 1 0 OUT73~1 - 2 - H 20 LCELL s 1 0 1 0 OUT74~1 - 2 - I 24 LCELL s 1 0 1 0 OUT75~1 - 1 - J 28 LCELL s 1 0 1 0 OUT76~1 - 2 - A 05 LCELL s 1 0 1 0 OUT77~1 - 2 - B 10 LCELL s 1 0 1 0 OUT78~1 - 3 - C 15 LCELL s 1 0 1 0 OUT79~1 - 3 - D 02 LCELL s 1 0 1 0 OUT80~1 - 4 - E 07 LCELL s 1 0 1 0 OUT81~1 - 4 - F 11 LCELL s 1 0 1 0 OUT82~1 - 5 - G 16 LCELL s 1 0 1 0 OUT83~1 - 7 - G 34 LCELL s 1 0 1 0 OUT84~1 - 1 - F 29 LCELL s 1 0 1 0 OUT85~1 - 1 - F 12 LCELL s 1 0 1 0 OUT86~1 - 1 - G 17 LCELL s 1 0 1 0 OUT87~1 - 1 - H 04 LCELL s 1 0 1 0 OUT88~1 - 8 - I 09 LCELL s 1 0 1 0 OUT89~1 - 1 - J 14 LCELL s 1 0 1 0 OUT90~1 - 8 - A 23 LCELL s 1 0 1 0 OUT91~1 - 1 - B 28 LCELL s 1 0 1 0 OUT92~1 - 1 - C 33 LCELL s 1 0 1 0 OUT93~1 - 1 - D 20 LCELL s 1 0 1 0 OUT94~1 - 1 - E 25 LCELL s 1 0 1 0 OUT95~1 - 6 - F 30 LCELL s 1 0 1 0 OUT96~1 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell p = Packed register Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 13/144( 9%) 3/ 72( 4%) 0/ 72( 0%) 9/16( 56%) 7/16( 43%) 0/16( 0%) B: 12/144( 8%) 4/ 72( 5%) 0/ 72( 0%) 10/16( 62%) 6/16( 37%) 0/16( 0%) C: 11/144( 7%) 5/ 72( 6%) 0/ 72( 0%) 9/16( 56%) 7/16( 43%) 0/16( 0%) D: 12/144( 8%) 4/ 72( 5%) 0/ 72( 0%) 9/16( 56%) 7/16( 43%) 0/16( 0%) E: 12/144( 8%) 4/ 72( 5%) 0/ 72( 0%) 9/16( 56%) 7/16( 43%) 0/16( 0%) F: 13/144( 9%) 3/ 72( 4%) 0/ 72( 0%) 10/16( 62%) 6/16( 37%) 0/16( 0%) G: 12/144( 8%) 4/ 72( 5%) 0/ 72( 0%) 8/16( 50%) 8/16( 50%) 0/16( 0%) H: 11/144( 7%) 5/ 72( 6%) 0/ 72( 0%) 8/16( 50%) 8/16( 50%) 0/16( 0%) I: 12/144( 8%) 4/ 72( 5%) 0/ 72( 0%) 9/16( 56%) 7/16( 43%) 0/16( 0%) J: 13/144( 9%) 3/ 72( 4%) 0/ 72( 0%) 9/16( 56%) 7/16( 43%) 0/16( 0%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 21: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%) 22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 25: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%) 26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 29: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%) 30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 34: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) Device-Specific Information: d:\max2work\altera projects\alayer\convert.rpt convert ** EQUATIONS ** INP1 : INPUT; INP2 : INPUT; INP3 : INPUT; INP4 : INPUT; INP5 : INPUT; INP6 : INPUT; INP7 : INPUT; INP8 : INPUT; INP9 : INPUT; INP10 : INPUT; INP11 : INPUT; INP12 : INPUT; INP13 : INPUT; INP14 : INPUT; INP15 : INPUT; INP16 : INPUT; INP17 : INPUT; INP18 : INPUT; INP19 : INPUT; INP20 : INPUT; INP21 : INPUT; INP22 : INPUT; INP23 : INPUT; INP24 : INPUT; INP25 : INPUT; INP26 : INPUT; INP27 : INPUT; INP28 : INPUT; INP29 : INPUT; INP30 : INPUT; INP31 : INPUT; INP32 : INPUT; INP33 : INPUT; INP34 : INPUT; INP35 : INPUT; INP36 : INPUT; INP37 : INPUT; INP38 : INPUT; INP39 : INPUT; INP40 : INPUT; INP41 : INPUT; INP42 : INPUT; INP43 : INPUT; INP44 : INPUT; INP45 : INPUT; INP46 : INPUT; INP47 : INPUT; INP48 : INPUT; INP49 : INPUT; INP50 : INPUT; INP51 : INPUT; INP52 : INPUT; INP53 : INPUT; INP54 : INPUT; INP55 : INPUT; INP56 : INPUT; INP57 : INPUT; INP58 : INPUT; INP59 : INPUT; INP60 : INPUT; INP61 : INPUT; INP62 : INPUT; INP63 : INPUT; INP64 : INPUT; INP65 : INPUT; INP66 : INPUT; INP67 : INPUT; INP68 : INPUT; INP69 : INPUT; INP70 : INPUT; INP71 : INPUT; INP72 : INPUT; INP73 : INPUT; INP74 : INPUT; INP75 : INPUT; INP76 : INPUT; INP77 : INPUT; INP78 : INPUT; INP79 : INPUT; INP80 : INPUT; INP81 : INPUT; INP82 : INPUT; INP83 : INPUT; INP84 : INPUT; INP85 : INPUT; INP86 : INPUT; INP87 : INPUT; INP88 : INPUT; INP89 : INPUT; INP90 : INPUT; INP91 : INPUT; INP92 : INPUT; INP93 : INPUT; INP94 : INPUT; INP95 : INPUT; INP96 : INPUT; -- Node name is 'OUT1~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT1~1', location is LC1_A1, type is buried. -- synthesized logic cell _LC1_A1 = LCELL( INP1); -- Node name is 'OUT1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT1', type is output OUT1 = _LC1_A1; -- Node name is 'OUT2~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT2~1', location is LC1_B6, type is buried. -- synthesized logic cell _LC1_B6 = LCELL( INP5); -- Node name is 'OUT2' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT2', type is output OUT2 = _LC1_B6; -- Node name is 'OUT3~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT3~1', location is LC7_C11, type is buried. -- synthesized logic cell _LC7_C11 = LCELL( INP9); -- Node name is 'OUT3' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT3', type is output OUT3 = _LC7_C11; -- Node name is 'OUT4~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT4~1', location is LC1_D16, type is buried. -- synthesized logic cell _LC1_D16 = LCELL( INP13); -- Node name is 'OUT4' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT4', type is output OUT4 = _LC1_D16; -- Node name is 'OUT5~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT5~1', location is LC1_E3, type is buried. -- synthesized logic cell _LC1_E3 = LCELL( INP17); -- Node name is 'OUT5' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT5', type is output OUT5 = _LC1_E3; -- Node name is 'OUT6~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT6~1', location is LC7_F8, type is buried. -- synthesized logic cell _LC7_F8 = LCELL( INP21); -- Node name is 'OUT6' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT6', type is output OUT6 = _LC7_F8; -- Node name is 'OUT7~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT7~1', location is LC6_G13, type is buried. -- synthesized logic cell _LC6_G13 = LCELL( INP25); -- Node name is 'OUT7' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT7', type is output OUT7 = _LC6_G13; -- Node name is 'OUT8~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT8~1', location is LC7_H18, type is buried. -- synthesized logic cell _LC7_H18 = LCELL( INP29); -- Node name is 'OUT8' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT8', type is output OUT8 = _LC7_H18; -- Node name is 'OUT9~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT9~1', location is LC1_I5, type is buried. -- synthesized logic cell _LC1_I5 = LCELL( INP33); -- Node name is 'OUT9' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT9', type is output OUT9 = _LC1_I5; -- Node name is 'OUT10~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT10~1', location is LC6_J10, type is buried. -- synthesized logic cell _LC6_J10 = LCELL( INP37); -- Node name is 'OUT10' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT10', type is output OUT10 = _LC6_J10; -- Node name is 'OUT11~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT11~1', location is LC7_A19, type is buried. -- synthesized logic cell _LC7_A19 = LCELL( INP41); -- Node name is 'OUT11' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT11', type is output OUT11 = _LC7_A19; -- Node name is 'OUT12~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT12~1', location is LC1_A2, type is buried. -- synthesized logic cell _LC1_A2 = LCELL( INP45); -- Node name is 'OUT12' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT12', type is output OUT12 = _LC1_A2; -- Node name is 'OUT13~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT13~1', location is LC8_J25, type is buried. -- synthesized logic cell _LC8_J25 = LCELL( INP49); -- Node name is 'OUT13' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT13', type is output OUT13 = _LC8_J25; -- Node name is 'OUT14~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT14~1', location is LC1_J11, type is buried. -- synthesized logic cell _LC1_J11 = LCELL( INP53); -- Node name is 'OUT14' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT14', type is output OUT14 = _LC1_J11; -- Node name is 'OUT15~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT15~1', location is LC1_A20, type is buried. -- synthesized logic cell _LC1_A20 = LCELL( INP57); -- Node name is 'OUT15' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT15', type is output OUT15 = _LC1_A20; -- Node name is 'OUT16~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT16~1', location is LC1_B24, type is buried. -- synthesized logic cell _LC1_B24 = LCELL( INP61); -- Node name is 'OUT16' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT16', type is output OUT16 = _LC1_B24; -- Node name is 'OUT17~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT17~1', location is LC1_C29, type is buried. -- synthesized logic cell _LC1_C29 = LCELL( INP65); -- Node name is 'OUT17' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT17', type is output OUT17 = _LC1_C29; -- Node name is 'OUT18~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT18~1', location is LC1_D34, type is buried. -- synthesized logic cell _LC1_D34 = LCELL( INP69); -- Node name is 'OUT18' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT18', type is output OUT18 = _LC1_D34; -- Node name is 'OUT19~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT19~1', location is LC1_E21, type is buried. -- synthesized logic cell _LC1_E21 = LCELL( INP73); -- Node name is 'OUT19' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT19', type is output OUT19 = _LC1_E21; -- Node name is 'OUT20~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT20~1', location is LC1_F26, type is buried. -- synthesized logic cell _LC1_F26 = LCELL( INP77); -- Node name is 'OUT20' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT20', type is output OUT20 = _LC1_F26; -- Node name is 'OUT21~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT21~1', location is LC7_G31, type is buried. -- synthesized logic cell _LC7_G31 = LCELL( INP81); -- Node name is 'OUT21' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT21', type is output OUT21 = _LC7_G31; -- Node name is 'OUT22~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT22~1', location is LC1_H35, type is buried. -- synthesized logic cell _LC1_H35 = LCELL( INP85); -- Node name is 'OUT22' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT22', type is output OUT22 = _LC1_H35; -- Node name is 'OUT23~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT23~1', location is LC1_I21, type is buried. -- synthesized logic cell _LC1_I21 = LCELL( INP89); -- Node name is 'OUT23' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT23', type is output OUT23 = _LC1_I21; -- Node name is 'OUT24~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT24~1', location is LC1_B25, type is buried. -- synthesized logic cell _LC1_B25 = LCELL( INP93); -- Node name is 'OUT24' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT24', type is output OUT24 = _LC1_B25; -- Node name is 'OUT25~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT25~1', location is LC1_C30, type is buried. -- synthesized logic cell _LC1_C30 = LCELL( INP2); -- Node name is 'OUT25' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT25', type is output OUT25 = _LC1_C30; -- Node name is 'OUT26~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT26~1', location is LC1_F9, type is buried. -- synthesized logic cell _LC1_F9 = LCELL( INP6); -- Node name is 'OUT26' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT26', type is output OUT26 = _LC1_F9; -- Node name is 'OUT27~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT27~1', location is LC1_G14, type is buried. -- synthesized logic cell _LC1_G14 = LCELL( INP10); -- Node name is 'OUT27' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT27', type is output OUT27 = _LC1_G14; -- Node name is 'OUT28~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT28~1', location is LC7_H1, type is buried. -- synthesized logic cell _LC7_H1 = LCELL( INP14); -- Node name is 'OUT28' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT28', type is output OUT28 = _LC7_H1; -- Node name is 'OUT29~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT29~1', location is LC3_I6, type is buried. -- synthesized logic cell _LC3_I6 = LCELL( INP18); -- Node name is 'OUT29' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT29', type is output OUT29 = _LC3_I6; -- Node name is 'OUT30~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT30~1', location is LC3_J12, type is buried. -- synthesized logic cell _LC3_J12 = LCELL( INP22); -- Node name is 'OUT30' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT30', type is output OUT30 = _LC3_J12; -- Node name is 'OUT31~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT31~1', location is LC4_A21, type is buried. -- synthesized logic cell _LC4_A21 = LCELL( INP26); -- Node name is 'OUT31' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT31', type is output OUT31 = _LC4_A21; -- Node name is 'OUT32~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT32~1', location is LC3_B26, type is buried. -- synthesized logic cell _LC3_B26 = LCELL( INP30); -- Node name is 'OUT32' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT32', type is output OUT32 = _LC3_B26; -- Node name is 'OUT33~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT33~1', location is LC2_C31, type is buried. -- synthesized logic cell _LC2_C31 = LCELL( INP34); -- Node name is 'OUT33' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT33', type is output OUT33 = _LC2_C31; -- Node name is 'OUT34~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT34~1', location is LC5_D35, type is buried. -- synthesized logic cell _LC5_D35 = LCELL( INP38); -- Node name is 'OUT34' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT34', type is output OUT34 = _LC5_D35; -- Node name is 'OUT35~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT35~1', location is LC5_E22, type is buried. -- synthesized logic cell _LC5_E22 = LCELL( INP42); -- Node name is 'OUT35' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT35', type is output OUT35 = _LC5_E22; -- Node name is 'OUT36~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT36~1', location is LC2_E4, type is buried. -- synthesized logic cell _LC2_E4 = LCELL( INP46); -- Node name is 'OUT36' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT36', type is output OUT36 = _LC2_E4; -- Node name is 'OUT37~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT37~1', location is LC3_D17, type is buried. -- synthesized logic cell _LC3_D17 = LCELL( INP50); -- Node name is 'OUT37' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT37', type is output OUT37 = _LC3_D17; -- Node name is 'OUT38~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT38~1', location is LC1_D36, type is buried. -- synthesized logic cell _LC1_D36 = LCELL( INP54); -- Node name is 'OUT38' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT38', type is output OUT38 = _LC1_D36; -- Node name is 'OUT39~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT39~1', location is LC2_E23, type is buried. -- synthesized logic cell _LC2_E23 = LCELL( INP58); -- Node name is 'OUT39' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT39', type is output OUT39 = _LC2_E23; -- Node name is 'OUT40~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT40~1', location is LC3_F27, type is buried. -- synthesized logic cell _LC3_F27 = LCELL( INP62); -- Node name is 'OUT40' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT40', type is output OUT40 = _LC3_F27; -- Node name is 'OUT41~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT41~1', location is LC1_G32, type is buried. -- synthesized logic cell _LC1_G32 = LCELL( INP66); -- Node name is 'OUT41' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT41', type is output OUT41 = _LC1_G32; -- Node name is 'OUT42~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT42~1', location is LC1_H36, type is buried. -- synthesized logic cell _LC1_H36 = LCELL( INP70); -- Node name is 'OUT42' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT42', type is output OUT42 = _LC1_H36; -- Node name is 'OUT43~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT43~1', location is LC1_I22, type is buried. -- synthesized logic cell _LC1_I22 = LCELL( INP74); -- Node name is 'OUT43' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT43', type is output OUT43 = _LC1_I22; -- Node name is 'OUT44~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT44~1', location is LC2_J26, type is buried. -- synthesized logic cell _LC2_J26 = LCELL( INP78); -- Node name is 'OUT44' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT44', type is output OUT44 = _LC2_J26; -- Node name is 'OUT45~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT45~1', location is LC3_A3, type is buried. -- synthesized logic cell _LC3_A3 = LCELL( INP82); -- Node name is 'OUT45' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT45', type is output OUT45 = _LC3_A3; -- Node name is 'OUT46~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT46~1', location is LC5_B7, type is buried. -- synthesized logic cell _LC5_B7 = LCELL( INP86); -- Node name is 'OUT46' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT46', type is output OUT46 = _LC5_B7; -- Node name is 'OUT47~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT47~1', location is LC3_C12, type is buried. -- synthesized logic cell _LC3_C12 = LCELL( INP90); -- Node name is 'OUT47' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT47', type is output OUT47 = _LC3_C12; -- Node name is 'OUT48~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT48~1', location is LC7_I7, type is buried. -- synthesized logic cell _LC7_I7 = LCELL( INP94); -- Node name is 'OUT48' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT48', type is output OUT48 = _LC7_I7; -- Node name is 'OUT49~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT49~1', location is LC5_H2, type is buried. -- synthesized logic cell _LC5_H2 = LCELL( INP3); -- Node name is 'OUT49' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT49', type is output OUT49 = _LC5_H2; -- Node name is 'OUT50~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT50~1', location is LC7_D19, type is buried. -- synthesized logic cell _LC7_D19 = LCELL( INP7); -- Node name is 'OUT50' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT50', type is output OUT50 = _LC7_D19; -- Node name is 'OUT51~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT51~1', location is LC7_E24, type is buried. -- synthesized logic cell _LC7_E24 = LCELL( INP11); -- Node name is 'OUT51' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT51', type is output OUT51 = _LC7_E24; -- Node name is 'OUT52~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT52~1', location is LC5_F28, type is buried. -- synthesized logic cell _LC5_F28 = LCELL( INP15); -- Node name is 'OUT52' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT52', type is output OUT52 = _LC5_F28; -- Node name is 'OUT53~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT53~1', location is LC4_G33, type is buried. -- synthesized logic cell _LC4_G33 = LCELL( INP19); -- Node name is 'OUT53' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT53', type is output OUT53 = _LC4_G33; -- Node name is 'OUT54~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT54~1', location is LC6_H19, type is buried. -- synthesized logic cell _LC6_H19 = LCELL( INP23); -- Node name is 'OUT54' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT54', type is output OUT54 = _LC6_H19; -- Node name is 'OUT55~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT55~1', location is LC6_I23, type is buried. -- synthesized logic cell _LC6_I23 = LCELL( INP27); -- Node name is 'OUT55' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT55', type is output OUT55 = _LC6_I23; -- Node name is 'OUT56~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT56~1', location is LC5_J27, type is buried. -- synthesized logic cell _LC5_J27 = LCELL( INP31); -- Node name is 'OUT56' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT56', type is output OUT56 = _LC5_J27; -- Node name is 'OUT57~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT57~1', location is LC5_A4, type is buried. -- synthesized logic cell _LC5_A4 = LCELL( INP35); -- Node name is 'OUT57' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT57', type is output OUT57 = _LC5_A4; -- Node name is 'OUT58~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT58~1', location is LC5_B8, type is buried. -- synthesized logic cell _LC5_B8 = LCELL( INP39); -- Node name is 'OUT58' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT58', type is output OUT58 = _LC5_B8; -- Node name is 'OUT59~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT59~1', location is LC5_C13, type is buried. -- synthesized logic cell _LC5_C13 = LCELL( INP43); -- Node name is 'OUT59' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT59', type is output OUT59 = _LC5_C13; -- Node name is 'OUT60~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT60~1', location is LC5_C32, type is buried. -- synthesized logic cell _LC5_C32 = LCELL( INP47); -- Node name is 'OUT60' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT60', type is output OUT60 = _LC5_C32; -- Node name is 'OUT61~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT61~1', location is LC7_B27, type is buried. -- synthesized logic cell _LC7_B27 = LCELL( INP51); -- Node name is 'OUT61' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT61', type is output OUT61 = _LC7_B27; -- Node name is 'OUT62~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT62~1', location is LC8_B9, type is buried. -- synthesized logic cell _LC8_B9 = LCELL( INP55); -- Node name is 'OUT62' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT62', type is output OUT62 = _LC8_B9; -- Node name is 'OUT63~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT63~1', location is LC7_C14, type is buried. -- synthesized logic cell _LC7_C14 = LCELL( INP59); -- Node name is 'OUT63' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT63', type is output OUT63 = _LC7_C14; -- Node name is 'OUT64~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT64~1', location is LC7_D18, type is buried. -- synthesized logic cell _LC7_D18 = LCELL( INP63); -- Node name is 'OUT64' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT64', type is output OUT64 = _LC7_D18; -- Node name is 'OUT65~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT65~1', location is LC6_E5, type is buried. -- synthesized logic cell _LC6_E5 = LCELL( INP67); -- Node name is 'OUT65' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT65', type is output OUT65 = _LC6_E5; -- Node name is 'OUT66~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT66~1', location is LC5_F10, type is buried. -- synthesized logic cell _LC5_F10 = LCELL( INP71); -- Node name is 'OUT66' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT66', type is output OUT66 = _LC5_F10; -- Node name is 'OUT67~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT67~1', location is LC3_G15, type is buried. -- synthesized logic cell _LC3_G15 = LCELL( INP75); -- Node name is 'OUT67' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT67', type is output OUT67 = _LC3_G15; -- Node name is 'OUT68~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT68~1', location is LC4_H3, type is buried. -- synthesized logic cell _LC4_H3 = LCELL( INP79); -- Node name is 'OUT68' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT68', type is output OUT68 = _LC4_H3; -- Node name is 'OUT69~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT69~1', location is LC5_I8, type is buried. -- synthesized logic cell _LC5_I8 = LCELL( INP83); -- Node name is 'OUT69' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT69', type is output OUT69 = _LC5_I8; -- Node name is 'OUT70~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT70~1', location is LC6_J13, type is buried. -- synthesized logic cell _LC6_J13 = LCELL( INP87); -- Node name is 'OUT70' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT70', type is output OUT70 = _LC6_J13; -- Node name is 'OUT71~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT71~1', location is LC5_A22, type is buried. -- synthesized logic cell _LC5_A22 = LCELL( INP91); -- Node name is 'OUT71' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT71', type is output OUT71 = _LC5_A22; -- Node name is 'OUT72~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT72~1', location is LC6_D1, type is buried. -- synthesized logic cell _LC6_D1 = LCELL( INP95); -- Node name is 'OUT72' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT72', type is output OUT72 = _LC6_D1; -- Node name is 'OUT73~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT73~1', location is LC6_E6, type is buried. -- synthesized logic cell _LC6_E6 = LCELL( INP4); -- Node name is 'OUT73' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT73', type is output OUT73 = _LC6_E6; -- Node name is 'OUT74~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT74~1', location is LC2_H20, type is buried. -- synthesized logic cell _LC2_H20 = LCELL( INP8); -- Node name is 'OUT74' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT74', type is output OUT74 = _LC2_H20; -- Node name is 'OUT75~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT75~1', location is LC2_I24, type is buried. -- synthesized logic cell _LC2_I24 = LCELL( INP12); -- Node name is 'OUT75' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT75', type is output OUT75 = _LC2_I24; -- Node name is 'OUT76~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT76~1', location is LC1_J28, type is buried. -- synthesized logic cell _LC1_J28 = LCELL( INP16); -- Node name is 'OUT76' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT76', type is output OUT76 = _LC1_J28; -- Node name is 'OUT77~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT77~1', location is LC2_A5, type is buried. -- synthesized logic cell _LC2_A5 = LCELL( INP20); -- Node name is 'OUT77' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT77', type is output OUT77 = _LC2_A5; -- Node name is 'OUT78~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT78~1', location is LC2_B10, type is buried. -- synthesized logic cell _LC2_B10 = LCELL( INP24); -- Node name is 'OUT78' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT78', type is output OUT78 = _LC2_B10; -- Node name is 'OUT79~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT79~1', location is LC3_C15, type is buried. -- synthesized logic cell _LC3_C15 = LCELL( INP28); -- Node name is 'OUT79' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT79', type is output OUT79 = _LC3_C15; -- Node name is 'OUT80~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT80~1', location is LC3_D2, type is buried. -- synthesized logic cell _LC3_D2 = LCELL( INP32); -- Node name is 'OUT80' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT80', type is output OUT80 = _LC3_D2; -- Node name is 'OUT81~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT81~1', location is LC4_E7, type is buried. -- synthesized logic cell _LC4_E7 = LCELL( INP36); -- Node name is 'OUT81' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT81', type is output OUT81 = _LC4_E7; -- Node name is 'OUT82~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT82~1', location is LC4_F11, type is buried. -- synthesized logic cell _LC4_F11 = LCELL( INP40); -- Node name is 'OUT82' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT82', type is output OUT82 = _LC4_F11; -- Node name is 'OUT83~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT83~1', location is LC5_G16, type is buried. -- synthesized logic cell _LC5_G16 = LCELL( INP44); -- Node name is 'OUT83' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT83', type is output OUT83 = _LC5_G16; -- Node name is 'OUT84~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT84~1', location is LC7_G34, type is buried. -- synthesized logic cell _LC7_G34 = LCELL( INP48); -- Node name is 'OUT84' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT84', type is output OUT84 = _LC7_G34; -- Node name is 'OUT85~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT85~1', location is LC1_F29, type is buried. -- synthesized logic cell _LC1_F29 = LCELL( INP52); -- Node name is 'OUT85' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT85', type is output OUT85 = _LC1_F29; -- Node name is 'OUT86~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT86~1', location is LC1_F12, type is buried. -- synthesized logic cell _LC1_F12 = LCELL( INP56); -- Node name is 'OUT86' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT86', type is output OUT86 = _LC1_F12; -- Node name is 'OUT87~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT87~1', location is LC1_G17, type is buried. -- synthesized logic cell _LC1_G17 = LCELL( INP60); -- Node name is 'OUT87' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT87', type is output OUT87 = _LC1_G17; -- Node name is 'OUT88~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT88~1', location is LC1_H4, type is buried. -- synthesized logic cell _LC1_H4 = LCELL( INP64); -- Node name is 'OUT88' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT88', type is output OUT88 = _LC1_H4; -- Node name is 'OUT89~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT89~1', location is LC8_I9, type is buried. -- synthesized logic cell _LC8_I9 = LCELL( INP68); -- Node name is 'OUT89' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT89', type is output OUT89 = _LC8_I9; -- Node name is 'OUT90~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT90~1', location is LC1_J14, type is buried. -- synthesized logic cell _LC1_J14 = LCELL( INP72); -- Node name is 'OUT90' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT90', type is output OUT90 = _LC1_J14; -- Node name is 'OUT91~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT91~1', location is LC8_A23, type is buried. -- synthesized logic cell _LC8_A23 = LCELL( INP76); -- Node name is 'OUT91' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT91', type is output OUT91 = _LC8_A23; -- Node name is 'OUT92~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT92~1', location is LC1_B28, type is buried. -- synthesized logic cell _LC1_B28 = LCELL( INP80); -- Node name is 'OUT92' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT92', type is output OUT92 = _LC1_B28; -- Node name is 'OUT93~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT93~1', location is LC1_C33, type is buried. -- synthesized logic cell _LC1_C33 = LCELL( INP84); -- Node name is 'OUT93' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT93', type is output OUT93 = _LC1_C33; -- Node name is 'OUT94~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT94~1', location is LC1_D20, type is buried. -- synthesized logic cell _LC1_D20 = LCELL( INP88); -- Node name is 'OUT94' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT94', type is output OUT94 = _LC1_D20; -- Node name is 'OUT95~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT95~1', location is LC1_E25, type is buried. -- synthesized logic cell _LC1_E25 = LCELL( INP92); -- Node name is 'OUT95' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT95', type is output OUT95 = _LC1_E25; -- Node name is 'OUT96~1' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT96~1', location is LC6_F30, type is buried. -- synthesized logic cell _LC6_F30 = LCELL( INP96); -- Node name is 'OUT96' from file "convert.tdf" line 23, column 10 -- Equation name is 'OUT96', type is output OUT96 = _LC6_F30; Project Information d:\max2work\altera projects\alayer\convert.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'FLEX10KA' family CARRY_CHAIN = ignore CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = ignore CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = on IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = off Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:02 Database Builder 00:00:00 Logic Synthesizer 00:00:04 Partitioner 00:00:07 Fitter 00:00:43 Timing SNF Extractor 00:00:04 Assembler 00:00:19 -------------------------- -------- Total Time 00:01:19 Memory Allocated ----------------- Peak memory allocated during compilation = 28,782K