--
--  Copyright (C) 1988-2001 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP centbld
BEGIN
	|TP2 :	OUTPUT_PIN = C23;
	|TP1 :	OUTPUT_PIN = B24;
	|TP0 :	OUTPUT_PIN = C21;
	|INP_L3 :	INPUT_PIN = R2;
	DEVICE = EPF10K100ABC356-2;
	|FPGA_ID7 :	OUTPUT_PIN = C17;
	|FPGA_ID6 :	OUTPUT_PIN = B19;
	|FPGA_ID5 :	OUTPUT_PIN = B21;
	|FPGA_ID4 :	OUTPUT_PIN = B23;
	|FPGA_ID3 :	OUTPUT_PIN = AD17;
	|FPGA_ID2 :	OUTPUT_PIN = A19;
	|FPGA_ID1 :	OUTPUT_PIN = AD13;
	|FPGA_ID0 :	OUTPUT_PIN = A12;
	|OUT0 :	OUTPUT_PIN = B20;
	|OUT1 :	OUTPUT_PIN = C20;
	|OUT2 :	OUTPUT_PIN = N3;
	|OUT3 :	OUTPUT_PIN = AD21;
	|OUT4 :	OUTPUT_PIN = AE12;
	|OUT5 :	OUTPUT_PIN = AD9;
	|OUT6 :	OUTPUT_PIN = AF8;
	|OUT7 :	OUTPUT_PIN = AF21;
	|OUT8 :	OUTPUT_PIN = N5;
	|OUT9 :	OUTPUT_PIN = A21;
	|OUT10 :	OUTPUT_PIN = AF24;
	|OUT11 :	OUTPUT_PIN = E25;
	|OUT12 :	OUTPUT_PIN = P26;
	|OUT13 :	OUTPUT_PIN = AE10;
	|OUT14 :	OUTPUT_PIN = AE22;
	|OUT15 :	OUTPUT_PIN = AF22;
	|OUT16 :	OUTPUT_PIN = J5;
	|OUT17 :	OUTPUT_PIN = A3;
	|OUT18 :	OUTPUT_PIN = A9;
	|OUT19 :	OUTPUT_PIN = C11;
	|OUT20 :	OUTPUT_PIN = C6;
	|OUT21 :	OUTPUT_PIN = AE6;
	|OUT22 :	OUTPUT_PIN = AF5;
	|OUT23 :	OUTPUT_PIN = AE8;
	|OUT24 :	OUTPUT_PIN = A5;
	|OUT25 :	OUTPUT_PIN = C1;
	|OUT26 :	OUTPUT_PIN = E2;
	|OUT27 :	OUTPUT_PIN = AE9;
	|OUT28 :	OUTPUT_PIN = AE3;
	|OUT29 :	OUTPUT_PIN = B10;
	|OUT30 :	OUTPUT_PIN = B7;
	|OUT31 :	OUTPUT_PIN = C10;
	|OUT32 :	OUTPUT_PIN = B18;
	|OUT33 :	OUTPUT_PIN = C22;
	|OUT34 :	OUTPUT_PIN = A8;
	|OUT35 :	OUTPUT_PIN = A11;
	|OUT36 :	OUTPUT_PIN = A25;
	|OUT37 :	OUTPUT_PIN = AF10;
	|OUT38 :	OUTPUT_PIN = AE11;
	|OUT39 :	OUTPUT_PIN = AF9;
	|OUT40 :	OUTPUT_PIN = M4;
	|OUT41 :	OUTPUT_PIN = AB22;
	|OUT42 :	OUTPUT_PIN = AF6;
	|OUT43 :	OUTPUT_PIN = B11;
	|OUT44 :	OUTPUT_PIN = K24;
	|OUT45 :	OUTPUT_PIN = AE21;
	|OUT46 :	OUTPUT_PIN = M22;
	|OUT47 :	OUTPUT_PIN = AF20;
	|OUT48 :	OUTPUT_PIN = AF23;
	|OUT49 :	OUTPUT_PIN = AD22;
	|OUT50 :	OUTPUT_PIN = C18;
	|OUT51 :	OUTPUT_PIN = AE20;
	|OUT52 :	OUTPUT_PIN = C19;
	|OUT53 :	OUTPUT_PIN = AD19;
	|OUT54 :	OUTPUT_PIN = A24;
	|OUT55 :	OUTPUT_PIN = AE17;
	|OUT56 :	OUTPUT_PIN = AE18;
	|OUT57 :	OUTPUT_PIN = AD16;
	|OUT58 :	OUTPUT_PIN = AE19;
	|OUT59 :	OUTPUT_PIN = A22;
	|OUT60 :	OUTPUT_PIN = AD10;
	|OUT61 :	OUTPUT_PIN = B16;
	|OUT62 :	OUTPUT_PIN = AD12;
	|OUT63 :	OUTPUT_PIN = C24;
	|STARTOUT :	OUTPUT_PIN = B8;
	|START :	INPUT_PIN = G3;
	|INP_A15 :	INPUT_PIN = J23;
	|INP_A14 :	INPUT_PIN = H26;
	|INP_A13 :	INPUT_PIN = H25;
	|INP_A12 :	INPUT_PIN = F22;
	|INP_A11 :	INPUT_PIN = F24;
	|INP_A10 :	INPUT_PIN = F25;
	|INP_A9 :	INPUT_PIN = F23;
	|INP_A8 :	INPUT_PIN = E26;
	|INP_A7 :	INPUT_PIN = E24;
	|INP_A6 :	INPUT_PIN = AF12;
	|INP_B15 :	INPUT_PIN = L26;
	|INP_B14 :	INPUT_PIN = L24;
	|INP_B13 :	INPUT_PIN = L22;
	|INP_B12 :	INPUT_PIN = V23;
	|INP_B11 :	INPUT_PIN = W26;
	|INP_B10 :	INPUT_PIN = V24;
	|INP_B9 :	INPUT_PIN = V25;
	|INP_B8 :	INPUT_PIN = U23;
	|INP_B7 :	INPUT_PIN = U24;
	|INP_B6 :	INPUT_PIN = V26;
	|INP_B5 :	INPUT_PIN = AA22;
	|INP_B4 :	INPUT_PIN = AA23;
	|INP_B3 :	INPUT_PIN = AA25;
	|INP_B2 :	INPUT_PIN = AA26;
	|INP_B1 :	INPUT_PIN = Y22;
	|INP_B0 :	INPUT_PIN = J22;
	|INP_C15 :	INPUT_PIN = W5;
	|INP_C14 :	INPUT_PIN = Y3;
	|INP_C13 :	INPUT_PIN = V22;
	|INP_C12 :	INPUT_PIN = W25;
	|INP_C11 :	INPUT_PIN = G22;
	|INP_C10 :	INPUT_PIN = G23;
	|INP_C9 :	INPUT_PIN = F26;
	|INP_C8 :	INPUT_PIN = AC26;
	|INP_C7 :	INPUT_PIN = A6;
	|INP_C6 :	INPUT_PIN = K25;
	|INP_C5 :	INPUT_PIN = AD7;
	|INP_C4 :	INPUT_PIN = K22;
	|INP_C3 :	INPUT_PIN = K23;
	|INP_C2 :	INPUT_PIN = L25;
	|INP_C1 :	INPUT_PIN = L23;
	|INP_C0 :	INPUT_PIN = A4;
	|INP_D10 :	INPUT_PIN = R5;
	|INP_D9 :	INPUT_PIN = P24;
	|INP_D8 :	INPUT_PIN = P22;
	|INP_D7 :	INPUT_PIN = T5;
	|INP_D6 :	INPUT_PIN = T4;
	|INP_D5 :	INPUT_PIN = T3;
	|INP_D4 :	INPUT_PIN = AB25;
	|INP_D3 :	INPUT_PIN = AB26;
	|INP_D2 :	INPUT_PIN = P23;
	|INP_D1 :	INPUT_PIN = P25;
	|INP_D0 :	INPUT_PIN = Y2;
	|INP_E15 :	INPUT_PIN = G24;
	|INP_E14 :	INPUT_PIN = H2;
	|INP_E13 :	INPUT_PIN = Y5;
	|INP_E12 :	INPUT_PIN = G4;
	|INP_E11 :	INPUT_PIN = G1;
	|INP_E10 :	INPUT_PIN = E22;
	|INP_E9 :	INPUT_PIN = E23;
	|INP_E8 :	INPUT_PIN = E1;
	|INP_E7 :	INPUT_PIN = D26;
	|INP_E6 :	INPUT_PIN = AD1;
	|INP_E5 :	INPUT_PIN = AC4;
	|INP_E4 :	INPUT_PIN = B12;
	|INP_E3 :	INPUT_PIN = N24;
	|INP_E2 :	INPUT_PIN = M25;
	|INP_E1 :	INPUT_PIN = M24;
	|INP_E0 :	INPUT_PIN = AD11;
	|INP_F15 :	INPUT_PIN = K2;
	|INP_F14 :	INPUT_PIN = L5;
	|INP_F13 :	INPUT_PIN = V1;
	|INP_F12 :	INPUT_PIN = V4;
	|INP_F11 :	INPUT_PIN = V3;
	|INP_F10 :	INPUT_PIN = U4;
	|INP_F9 :	INPUT_PIN = V5;
	|INP_F8 :	INPUT_PIN = U1;
	|INP_F7 :	INPUT_PIN = T23;
	|INP_F6 :	INPUT_PIN = R22;
	|INP_F5 :	INPUT_PIN = Y23;
	|INP_F4 :	INPUT_PIN = AA5;
	|INP_F3 :	INPUT_PIN = AA4;
	|INP_F2 :	INPUT_PIN = AA3;
	|INP_F1 :	INPUT_PIN = G26;
	|INP_F0 :	INPUT_PIN = G25;
	|INP_G15 :	INPUT_PIN = Y24;
	|INP_G14 :	INPUT_PIN = W23;
	|INP_G13 :	INPUT_PIN = Y26;
	|INP_G12 :	INPUT_PIN = Y25;
	|INP_G11 :	INPUT_PIN = F2;
	|INP_G10 :	INPUT_PIN = G5;
	|INP_G9 :	INPUT_PIN = AC1;
	|INP_G8 :	INPUT_PIN = AB5;
	|INP_G7 :	INPUT_PIN = L3;
	|INP_G6 :	INPUT_PIN = J24;
	|INP_G5 :	INPUT_PIN = K3;
	|INP_G4 :	INPUT_PIN = K26;
	|INP_G3 :	INPUT_PIN = J25;
	|INP_G2 :	INPUT_PIN = B9;
	|INP_G1 :	INPUT_PIN = L1;
	|INP_G0 :	INPUT_PIN = L2;
	|INP_H10 :	INPUT_PIN = P5;
	|INP_H9 :	INPUT_PIN = P4;
	|INP_H8 :	INPUT_PIN = C8;
	|INP_H7 :	INPUT_PIN = B17;
	|INP_H6 :	INPUT_PIN = T22;
	|INP_H5 :	INPUT_PIN = U25;
	|INP_H4 :	INPUT_PIN = AA24;
	|INP_H3 :	INPUT_PIN = R25;
	|INP_H2 :	INPUT_PIN = R24;
	|INP_H1 :	INPUT_PIN = R23;
	|INP_H0 :	INPUT_PIN = W24;
	|INP_I15 :	INPUT_PIN = H5;
	|INP_I14 :	INPUT_PIN = G2;
	|INP_I13 :	INPUT_PIN = B3;
	|INP_I12 :	INPUT_PIN = F5;
	|INP_I11 :	INPUT_PIN = F3;
	|INP_I10 :	INPUT_PIN = E5;
	|INP_I9 :	INPUT_PIN = E3;
	|INP_I8 :	INPUT_PIN = E4;
	|INP_I7 :	INPUT_PIN = D1;
	|INP_I6 :	INPUT_PIN = AB2;
	|INP_I5 :	INPUT_PIN = N2;
	|INP_I4 :	INPUT_PIN = N4;
	|INP_I3 :	INPUT_PIN = M5;
	|INP_I2 :	INPUT_PIN = M2;
	|INP_I1 :	INPUT_PIN = M3;
	|INP_I0 :	INPUT_PIN = AF18;
	|INP_J15 :	INPUT_PIN = L4;
	|INP_J14 :	INPUT_PIN = B5;
	|INP_J13 :	INPUT_PIN = B2;
	|INP_J12 :	INPUT_PIN = C4;
	|INP_J11 :	INPUT_PIN = AF15;
	|INP_J10 :	INPUT_PIN = U2;
	|INP_J9 :	INPUT_PIN = U3;
	|INP_J8 :	INPUT_PIN = R3;
	|INP_J7 :	INPUT_PIN = T2;
	|INP_J6 :	INPUT_PIN = C3;
	|INP_J5 :	INPUT_PIN = A16;
	|INP_J4 :	INPUT_PIN = Y4;
	|INP_J3 :	INPUT_PIN = AA2;
	|INP_J2 :	INPUT_PIN = H4;
	|INP_J1 :	INPUT_PIN = H3;
	|INP_J0 :	INPUT_PIN = H1;
	|INP_K15 :	INPUT_PIN = Y1;
	|INP_K14 :	INPUT_PIN = W2;
	|INP_K13 :	INPUT_PIN = AE15;
	|INP_K12 :	INPUT_PIN = C16;
	|INP_K11 :	INPUT_PIN = A18;
	|INP_K10 :	INPUT_PIN = AE16;
	|INP_K9 :	INPUT_PIN = A15;
	|INP_K8 :	INPUT_PIN = C5;
	|INP_K7 :	INPUT_PIN = J4;
	|INP_K6 :	INPUT_PIN = J3;
	|INP_K5 :	INPUT_PIN = J2;
	|INP_K4 :	INPUT_PIN = K4;
	|INP_K3 :	INPUT_PIN = A17;
	|INP_K2 :	INPUT_PIN = AE4;
	|INP_K1 :	INPUT_PIN = B6;
	|INP_K0 :	INPUT_PIN = AD15;
	|INP_L10 :	INPUT_PIN = P3;
	|INP_L9 :	INPUT_PIN = P1;
	|INP_L8 :	INPUT_PIN = AF17;
	|INP_L7 :	INPUT_PIN = C7;
	|INP_L6 :	INPUT_PIN = B15;
	|INP_L5 :	INPUT_PIN = AB3;
	|INP_L4 :	INPUT_PIN = AB4;
	|INP_L2 :	INPUT_PIN = R4;
	|INP_L1 :	INPUT_PIN = W3;
	|INP_L0 :	INPUT_PIN = W4;
	|CLOCK :	INPUT_PIN = A14;
	|nCLEAR :	INPUT_PIN = A13;
	|INP_A5 :	INPUT_PIN = AB24;
	|INP_A4 :	INPUT_PIN = AB23;
	|INP_A3 :	INPUT_PIN = N23;
	|INP_A2 :	INPUT_PIN = N22;
	|INP_A1 :	INPUT_PIN = N25;
	|INP_A0 :	INPUT_PIN = C12;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K30ATC144-1;
	AUTO_DEVICE = EPF10K30AQC208-1;
	AUTO_DEVICE = EPF10K30AQC240-1;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	DEVICE_FOR_TIMING_SYNTHESIS = FLEX10KA;
	MAINTAIN_STABLE_SYNTHESIS = ON;
	CUT_ALL_BIDIR = ON;
	CUT_ALL_CLEAR_PRESET = ON;
END;

IGNORED_ASSIGNMENTS
BEGIN
	FIT_IGNORE_TIMING = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
END;

LOGIC_OPTIONS
BEGIN
	|CLOCK :	INCREASE_INPUT_DELAY = ON;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	MAX7000B_ENABLE_VREFB = OFF;
	MAX7000B_ENABLE_VREFA = OFF;
	MAX7000B_VCCIO_IOBANK2 = 3.3V;
	MAX7000B_VCCIO_IOBANK1 = 3.3V;
	ENABLE_CHIP_WIDE_OE = ON;
	ENABLE_INIT_DONE_OUTPUT = ON;
	nWS_nRS_nCS_CS = RESERVED_TRI_STATED;
	DATA1_TO_DATA7 = RESERVED_TRI_STATED;
	RDYnBUSY = RESERVED_DRIVES_OUT;
	CONFIG_SCHEME_10K = PASSIVE_PARALLEL_ASYNCHRONOUS;
	CONFIG_EPROM_PULLUP_RESISTOR = ON;
	CONFIG_EPROM_USER_CODE = FFFFFFFF;
	FLEX_CONFIGURATION_EPROM = AUTO;
	MAX7000AE_ENABLE_JTAG = ON;
	MAX7000AE_USER_CODE = FFFFFFFF;
	RESERVED_LCELLS_PERCENT = 0;
	RESERVED_PINS_PERCENT = 0;
	SECURITY_BIT = OFF;
	USER_CLOCK = OFF;
	AUTO_RESTART = OFF;
	RELEASE_CLEARS = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	DISABLE_TIME_OUT = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	FLEX8000_ENABLE_JTAG = OFF;
	DATA0 = RESERVED_TRI_STATED;
	RDCLK = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	ADD0_TO_ADD12 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD17 = UNRESERVED;
	CLKUSR = UNRESERVED;
	nCEO = UNRESERVED;
	ENABLE_CHIP_WIDE_RESET = OFF;
	FLEX10K_JTAG_USER_CODE = 7F;
	MAX7000S_USER_CODE = FFFF;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_ENABLE_JTAG = ON;
	MULTIVOLT_IO = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	FLEX6000_ENABLE_JTAG = OFF;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	DEVICE_FAMILY = FLEX10KA;
	AUTO_FAST_IO = ON;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
	AUTO_GLOBAL_CLOCK = ON;
	AUTO_GLOBAL_CLEAR = ON;
	AUTO_GLOBAL_PRESET = ON;
	AUTO_GLOBAL_OE = ON;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
	OPTIMIZE_FOR_SPEED = 5;
	STYLE = NORMAL;
	AUTO_REGISTER_PACKING = OFF;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	DESIGN_DOCTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	OPTIMIZE_TIMING_SNF = OFF;
	LINKED_SNF_EXTRACTOR = OFF;
	RPT_FILE_EQUATIONS = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	GENERATE_AHDL_TDO_FILE = OFF;
	SMART_RECOMPILE = OFF;
	FITTER_SETTINGS = NORMAL;
	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	EDIF_INPUT_LMF1 = *.lmf;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_OUTPUT_EDC_FILE = *.edc;
	EDIF_INPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_OUTPUT_GND = GND;
	EDIF_INPUT_USE_LMF1 = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_FLATTEN_BUS = OFF;
	EDIF_BUS_DELIMITERS = [];
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	EDIF_NETLIST_WRITER = OFF;
	EDIF_OUTPUT_VERSION = 200;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	VERILOG_NETLIST_WRITER = OFF;
	VHDL_NETLIST_WRITER = OFF;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	VHDL_READER_VERSION = VHDL87;
	VHDL_WRITER_VERSION = VHDL87;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	RIPPLE_CLOCKS = ON;
	GATED_CLOCKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	PRESET_CLEAR_NETWORKS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	DELAY_CHAINS = ON;
	RACE_CONDITIONS = ON;
	EXPANDER_NETWORKS = ON;
	MASTER_RESET = OFF;
END;

SIMULATOR_CONFIGURATION
BEGIN
	END_TIME = 1.0us;
	SETUP_HOLD = ON;
	BIDIR_PIN = STRONG;
	USE_DEVICE = OFF;
	CHECK_OUTPUTS = OFF;
	OSCILLATION = OFF;
	OSCILLATION_TIME = 0.0ns;
	GLITCH = OFF;
	GLITCH_TIME = 0.0ns;
	START_TIME = 0.0ns;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	ANALYSIS_MODE = REGISTERED_PERFORMANCE;
	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
	AUTO_RECALCULATE = OFF;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	LIST_ONLY_LONGEST_PATH = ON;
	CELL_WIDTH = 18;
	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
	INCLUDE_PATHS_GREATER_THAN = OFF;
	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
	INCLUDE_PATHS_LESS_THAN = OFF;
	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
	REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
	LIST_PATH_COUNT = 10;
	LIST_PATH_FREQUENCY = 10MHz;
END;

OTHER_CONFIGURATION
BEGIN
	LAST_MAXPLUS2_VERSION = 10.1;
	ORIGINAL_MAXPLUS2_VERSION = 8.2;
	EXPLICIT_FAMILY = 1;
	DESIGNER_NAME = "Emanuel Machado";
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
	ROW_PINS_PERCENT = 50;
	EXP_PER_LCELL_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	LCELLS_PER_ROW_PERCENT = 100;
	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	FLEX_10K_52_COLUMNS = 40;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	CARRY_CHAIN_LENGTH = 32;
	CASCADE_CHAIN_LENGTH = 2;
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	IGNORE_SOFT_BUFFERS = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CARRY_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CARRY_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CARRY_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	CASCADE_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = AUTO;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	CASCADE_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = MANUAL;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;