SUBDESIGN 9616old (
	INP[95..0]	:	INPUT;
	nCLEAR		:	INPUT;
	START, CLOCK:	INPUT;
	OUT[15..0]	:	OUTPUT;
	STARTOUT	:	OUTPUT;
)

VARIABLE

-- Data registers

	IMP[95..0]		:	DFFE;
	DATA[95..0]		:	DFF;
	OUT[15..0]		:	DFF;
	START_[16..0]	:	DFF;
	LOAD_[11..1]	:	DFF;
	IMPLOAD_[6..1]	:	DFF;
	STARTOUT		:	DFF;

-- switching registers


	
BEGIN

-- all clocks

	IMP[].clk = CLOCK;
	DATA[].clk = CLOCK;
	OUT[].clk = CLOCK;
	START_[].clk = CLOCK;
	LOAD_[].clk	= CLOCK;
	IMPLOAD_[].clk	= CLOCK;
	STARTOUT.clk	= CLOCK;

-- clearing specials

	IMP[].clrn = nCLEAR;
	DATA[].clrn = nCLEAR;
	OUT[].clrn = nCLEAR;
	START_[].clrn = nCLEAR;
	LOAD_[].clrn = nCLEAR;
	IMPLOAD_[].clrn = nCLEAR;
	STARTOUT.clrn = nCLEAR;

-- Enabling specials

	IMP[15..0 ].ena = IMPLOAD_1;
	IMP[31..16].ena = IMPLOAD_2;
	IMP[47..32].ena = IMPLOAD_3;
	IMP[63..48].ena = IMPLOAD_4;
	IMP[79..64].ena = IMPLOAD_5;
	IMP[95..80].ena = IMPLOAD_6;

-- switching chain

	start_0 = start;
	for i in 1 to 16 generate
		start_[i] = start_[i-1];
	end generate;

-- The Load Chain

	for i in 1 to 11 generate
		LOAD_[i] = START_10;
	end generate;

	for i in 1 to 6 generate
		IMPLOAD_[i] = START_8;
	end generate;

	STARTOUT = START_12;

	IMP[] = INP[];

	DATA[95..80] = IMP[95..80] AND LOAD_1;
	DATA[79..64] = (IMP[79..64] AND LOAD_2) OR (DATA[95..80] AND NOT LOAD_7);
	DATA[63..48] = (IMP[63..48] AND LOAD_3) OR (DATA[79..64] AND NOT LOAD_8);
	DATA[47..32] = (IMP[47..32] AND LOAD_4) OR (DATA[63..48] AND NOT LOAD_9);
	DATA[31..16] = (IMP[31..16] AND LOAD_5) OR (DATA[47..32] AND NOT LOAD_10);
	DATA[15..0 ] = (IMP[15..0 ] AND LOAD_6) OR (DATA[31..16] AND NOT LOAD_11);

	OUT[] = DATA[15..0];

END;