SUBDESIGN 1696old (
	IMP[15..0]		:	INPUT;
	OUT[95..0]		:	OUTPUT;
	CLOCK			:	INPUT;
	START			:	INPUT;
	nCLEAR			:	INPUT;
)

VARIABLE

START_[6..1]	:	DFF;
LOAD_[6..1]		:	DFF;
DATA[95..0]		:	DFF;
INP[15..0]		:	DFF;
OUT[95..0]		:	DFFE;

BEGIN

START_[].clk = CLOCK;
LOAD_[].clk = CLOCK;
DATA[95..0].clk = CLOCK;
INP[15..0].clk = CLOCK;
OUT[95..0].clk = CLOCK;

START_[].clrn = nCLEAR;
LOAD_[].clrn = nCLEAR;
DATA[95..0].clrn = nCLEAR;
INP[15..0].clrn = nCLEAR;
OUT[95..0].clrn = nCLEAR;

START_1 = START;

for i in 2 to 6 generate
	start_[i] = start_[i-1];
end generate;

for i in 1 to 6 generate
	load_[i] = start_6;
end generate;
 
INP[] = IMP[];

DATA[95..80]  = INP[15..0];
DATA[79..64] = DATA[95..80];
DATA[63..48] = DATA[79..64];
DATA[47..32] = DATA[63..48];
DATA[31..16] = DATA[47..32];
DATA[15..0] = DATA[31..16];

OUT[] = DATA[];


OUT[15..0 ].ena = load_1;
OUT[31..16].ena = load_2;
OUT[47..32].ena = load_3;
OUT[63..48].ena = load_4;
OUT[79..64].ena = load_5;
OUT[95..80].ena = load_6;

END;