---------------------------------------------------------------------------
-- VHDL Timing Model
-- Converted from JEDEC file
-- Created by Philips Semiconductors
-- Program: xplafit version 3.21
-- Design Name = tmgdec
-- Device Name = pz5064cs7bc
-- Jan 18 18:16:00 2001
---------------------------------------------------------------------------
package pxa_pkg is
    constant tpd0 : time := 0 ps;
    constant tpd1 : time := 6000 ps;
    constant tpd2 : time := 7500 ps;
    constant tclk : time := 1500 ps;
    constant tap2q: time := 3000 ps;
    constant tar2q: time := 3000 ps;
    constant trd  : time := 2000 ps;
    constant tbuf : time := 1500 ps;
    constant toe  : time := 1500 ps;
end pxa_pkg;
---------------------------------------------------------------------------
-- Components Defined Here
---------------------------------------------------------------------------
-- Output Buffer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_bufif1 is
	Port (O: out std_logic; I, OE : in std_logic);
end pxa_bufif1;
architecture behavioral of pxa_bufif1 is
begin
	O <= I after tbuf when OE='1' else 'Z' after toe;
end behavioral;

-- D Flip Flop with Asynchronous Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_dff_ar_p0 is
	port (Q : Out std_logic; D, CLK, AR : In std_logic);
end pxa_dff_ar_p0;
architecture behavioral of pxa_dff_ar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
	 elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- D flip flop with Asynchronous Preset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_dff_ap_p0 is
	port (Q : Out std_logic; D, CLK, AP : In std_logic);
end pxa_dff_ap_p0;
architecture behavioral of pxa_dff_ap_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP)
  begin
	 if AP = '1' then
	   Q_local <= '1' after tap2q;
	 elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_tff_ar_p0 is
	port (Q : out std_logic; T, CLK, AR : in std_logic);
end pxa_tff_ar_p0;
architecture behavioral of pxa_tff_ar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Preset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_tff_ap_p0 is
	port (Q : out std_logic; T, CLK, AP : in std_logic);
end pxa_tff_ap_p0;
architecture behavioral of pxa_tff_ap_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP)
  begin
    if AP = '1' then
      Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

---------------------------------------------------------------------------
-- Main VHDL Model 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity tmgdec is
    port(VXO53MHz: in std_logic;
         Clk106MHz: in std_logic;
         EncTmgp: in std_logic;
         RF_In: in std_logic;
         VXO_Div4: out std_logic;
         FC: out std_logic;
         SGap: out std_logic;
         Gap: out std_logic;
         Clk53MHzOut: out std_logic;
         PhDet: out std_logic;
         test1: out std_logic;
         test0: out std_logic;
         RF_Dtct: out std_logic);
end tmgdec;

architecture structure of tmgdec is

-- Signal Declaration -------------------------------
signal VXO_Div4_T, VXO_Div4_OE, VXO_Div4_Q, VXO_Div4_C, VXO_Div4_AP,
       VXO_Div4_AR, FC_T, FC_OE, FC_Q, FC_C, FC_AP, FC_AR, SGap_T, SGap_OE,
       SGap_Q, SGap_C, SGap_AP, SGap_AR, Gap_T, Gap_OE, Gap_Q, Gap_C, Gap_AP,
       Gap_AR, Clk53MHzOut_D, Clk53MHzOut_OE, Clk53MHzOut_Q, Clk53MHzOut_C,
       Clk53MHzOut_AP, Clk53MHzOut_AR, PhDet_COM, PhDet_OE, test1_T,
       test1_OE, test1_Q, test1_C, test1_AP, test1_AR, test0_T, test0_OE,
       test0_Q, test0_C, test0_AP, test0_AR, RF_Dtct_D, RF_Dtct_OE,
       RF_Dtct_Q, RF_Dtct_C, RF_Dtct_AP, RF_Dtct_AR, Enc_Div2, Enc_Div2_T,
       Enc_Div2_C, Enc_Div2_AP, Enc_Div2_AR, D0, D0_D, D0_C, D0_AP, D0_AR,
       D1, D1_D, D1_C, D1_AP, D1_AR, S2, S2_T, S2_C, S2_AP, S2_AR, IDtct,
       IDtct_D, IDtct_C, IDtct_AP, IDtct_AR, VXOCnt0, VXOCnt0_T, VXOCnt0_C,
       VXOCnt0_AP, VXOCnt0_AR, VXOCnt1, VXOCnt1_T, VXOCnt1_C, VXOCnt1_AP,
       VXOCnt1_AR, VXOCnt2, VXOCnt2_T, VXOCnt2_C, VXOCnt2_AP, VXOCnt2_AR
       : std_logic;
signal VCC : std_logic := '1';
signal GND : std_logic := '0';

component pxa_bufif1
	Port (O: out std_logic; I, OE : in std_logic);
end component;
component pxa_dff_ap_p0
	port (Q : out std_logic; D, CLK, AP : in std_logic);
end component;
component pxa_dff_ar_p0
	port (Q : out std_logic; D, CLK, AR : in std_logic);
end component;
component pxa_tff_ap_p0
	port (Q : out std_logic; T, CLK, AP : in std_logic);
end component;
component pxa_tff_ar_p0
	port (Q : out std_logic; T, CLK, AR : in std_logic);
end component;
begin
-- Equations:

------( VXO_Div4 )-----------------------------------------------------------
VXO_Div4_T <= ((VXOCnt0)) after tpd1;
VXO_Div4_OE <= (VCC) after tpd0;
VXO_Div4_buf: pxa_bufif1 port map (VXO_Div4, VXO_Div4_Q, VXO_Div4_OE);
VXO_Div4_AP <= (GND) after tpd0;
VXO_Div4_AR <= (GND) after tpd0;
VXO_Div4_C <= (VXO53MHz) after tclk;
VXO_Div4_ff: pxa_tff_ar_p0 port map(VXO_Div4_Q, VXO_Div4_T, VXO_Div4_C, VXO_Div4_AR);
------( FC )-----------------------------------------------------------------
FC_T <= ((FC_Q and not D0 and EncTmgp and not test1_Q and D1 and S2 and not test0_Q)
	or (FC_Q and D0 and not EncTmgp and not test1_Q and not D1 and S2 and not test0_Q)
	or (not FC_Q and EncTmgp and not test1_Q and not D1 and S2 and not test0_Q)) after tpd1;
FC_OE <= (VCC) after tpd0;
FC_buf: pxa_bufif1 port map (FC, FC_Q, FC_OE);
FC_AP <= (GND) after tpd0;
FC_AR <= (GND) after tpd0;
FC_C <= (Clk106MHz) after tclk;
FC_ff: pxa_tff_ar_p0 port map(FC_Q, FC_T, FC_C, FC_AR);
------( SGap )---------------------------------------------------------------
SGap_T <= ((not D0 and EncTmgp and SGap_Q and D1 and S2 and not test1_Q and not test0_Q)
	or (D0 and EncTmgp and not SGap_Q and not D1 and S2 and not test1_Q and not test0_Q)
	or (not D0 and not EncTmgp and not SGap_Q and not D1 and S2 and not test1_Q and not test0_Q)) after tpd1;
SGap_OE <= (VCC) after tpd0;
SGap_buf: pxa_bufif1 port map (SGap, SGap_Q, SGap_OE);
SGap_AP <= (GND) after tpd0;
SGap_AR <= (GND) after tpd0;
SGap_C <= (Clk106MHz) after tclk;
SGap_ff: pxa_tff_ar_p0 port map(SGap_Q, SGap_T, SGap_C, SGap_AR);
------( Gap )----------------------------------------------------------------
Gap_T <= ((Gap_Q and not D0 and EncTmgp and not test1_Q and D1 and S2 and not test0_Q)
	or (not Gap_Q and not D0 and not EncTmgp and not test1_Q and D1 and S2 and not test0_Q)) after tpd1;
Gap_OE <= (VCC) after tpd0;
Gap_buf: pxa_bufif1 port map (Gap, Gap_Q, Gap_OE);
Gap_AP <= (GND) after tpd0;
Gap_AR <= (GND) after tpd0;
Gap_C <= (Clk106MHz) after tclk;
Gap_ff: pxa_tff_ar_p0 port map(Gap_Q, Gap_T, Gap_C, Gap_AR);
------( Clk53MHzOut )--------------------------------------------------------
Clk53MHzOut_D <= ((test0_Q)) after tpd1;
Clk53MHzOut_OE <= (VCC) after tpd0;
Clk53MHzOut_buf: pxa_bufif1 port map (Clk53MHzOut, Clk53MHzOut_Q, Clk53MHzOut_OE);
Clk53MHzOut_AP <= (GND) after tpd0;
Clk53MHzOut_AR <= (GND) after tpd0;
Clk53MHzOut_C <= (Clk106MHz) after tclk;
Clk53MHzOut_ff: pxa_dff_ar_p0 port map (Clk53MHzOut_Q, Clk53MHzOut_D, Clk53MHzOut_C, Clk53MHzOut_AR);
------( PhDet )--------------------------------------------------------------
PhDet_COM <= ((not Enc_Div2 and VXOCnt0)
	or (Enc_Div2 and not VXOCnt0)) after tpd1;
PhDet_OE <= (VCC) after tpd0;
PhDet_buf: pxa_bufif1 port map (PhDet, PhDet_COM, PhDet_OE);
------( test1 )--------------------------------------------------------------
test1_T <= not((not test0_Q)
	or (not EncTmgp and not S2 and not test1_Q)) after tpd1;
test1_OE <= (VCC) after tpd0;
test1_buf: pxa_bufif1 port map (test1, test1_Q, test1_OE);
test1_AP <= (GND) after tpd0;
test1_AR <= (GND) after tpd0;
test1_C <= (Clk106MHz) after tclk;
test1_ff: pxa_tff_ar_p0 port map(test1_Q, test1_T, test1_C, test1_AR);
------( test0 )--------------------------------------------------------------
test0_T <= not((not EncTmgp and not S2 and not test1_Q and not test0_Q)) after tpd1;
test0_OE <= (VCC) after tpd0;
test0_buf: pxa_bufif1 port map (test0, test0_Q, test0_OE);
test0_AP <= (GND) after tpd0;
test0_AR <= (GND) after tpd0;
test0_C <= (Clk106MHz) after tclk;
test0_ff: pxa_tff_ar_p0 port map(test0_Q, test0_T, test0_C, test0_AR);
------( RF_Dtct )------------------------------------------------------------
RF_Dtct_D <= (VCC) after tpd0;
RF_Dtct_OE <= (VCC) after tpd0;
RF_Dtct_buf: pxa_bufif1 port map (RF_Dtct, RF_Dtct_Q, RF_Dtct_OE);
RF_Dtct_AP <= (GND) after tpd0;
RF_Dtct_AR <= (VXO_Div4_Q and VXOCnt0 and not IDtct and VXOCnt1 and not VXOCnt2) after tpd1;
RF_Dtct_C <= (RF_In) after tclk;
RF_Dtct_ff: pxa_dff_ar_p0 port map (RF_Dtct_Q, RF_Dtct_D, RF_Dtct_C, RF_Dtct_AR);
------( Enc_Div2 )-----------------------------------------------------------
Enc_Div2_T <= (VCC) after tpd0;
Enc_Div2_AP <= (GND) after tpd0;
Enc_Div2_AR <= (GND) after tpd0;
Enc_Div2_C <= (EncTmgp) after tclk;
Enc_Div2_ff: pxa_tff_ar_p0  port map(Enc_Div2, Enc_Div2_T, Enc_Div2_C, Enc_Div2_AR);
------( D0 )-----------------------------------------------------------------
D0_D <= ((EncTmgp)) after tpd1;
D0_AP <= (GND) after tpd0;
D0_AR <= (GND) after tpd0;
D0_C <= (Clk106MHz) after tclk;
D0_ff: pxa_dff_ar_p0 port map(D0, D0_D, D0_C, D0_AR);
------( D1 )-----------------------------------------------------------------
D1_D <= ((D0)) after tpd1;
D1_AP <= (GND) after tpd0;
D1_AR <= (GND) after tpd0;
D1_C <= (Clk106MHz) after tclk;
D1_ff: pxa_dff_ar_p0 port map(D1, D1_D, D1_C, D1_AR);
------( S2 )-----------------------------------------------------------------
S2_T <= ((test1_Q and test0_Q)) after tpd1;
S2_AP <= (GND) after tpd0;
S2_AR <= (GND) after tpd0;
S2_C <= (Clk106MHz) after tclk;
S2_ff: pxa_tff_ar_p0  port map(S2, S2_T, S2_C, S2_AR);
------( IDtct )--------------------------------------------------------------
IDtct_D <= (VCC) after tpd0;
IDtct_AP <= (GND) after tpd0;
IDtct_AR <= (VXO_Div4_Q and VXOCnt0 and VXOCnt1 and VXOCnt2) after tpd1;
IDtct_C <= (RF_In) after tclk;
IDtct_ff: pxa_dff_ar_p0 port map(IDtct, IDtct_D, IDtct_C, IDtct_AR);
------( VXOCnt0 )------------------------------------------------------------
VXOCnt0_T <= (VCC) after tpd0;
VXOCnt0_AP <= (GND) after tpd0;
VXOCnt0_AR <= (GND) after tpd0;
VXOCnt0_C <= (VXO53MHz) after tclk;
VXOCnt0_ff: pxa_tff_ar_p0  port map(VXOCnt0, VXOCnt0_T, VXOCnt0_C, VXOCnt0_AR);
------( VXOCnt1 )------------------------------------------------------------
VXOCnt1_T <= ((VXO_Div4_Q and VXOCnt0)) after tpd1;
VXOCnt1_AP <= (GND) after tpd0;
VXOCnt1_AR <= (GND) after tpd0;
VXOCnt1_C <= (VXO53MHz) after tclk;
VXOCnt1_ff: pxa_tff_ar_p0  port map(VXOCnt1, VXOCnt1_T, VXOCnt1_C, VXOCnt1_AR);
------( VXOCnt2 )------------------------------------------------------------
VXOCnt2_T <= ((VXO_Div4_Q and VXOCnt0 and VXOCnt1)) after tpd1;
VXOCnt2_AP <= (GND) after tpd0;
VXOCnt2_AR <= (GND) after tpd0;
VXOCnt2_C <= (VXO53MHz) after tclk;
VXOCnt2_ff: pxa_tff_ar_p0  port map(VXOCnt2, VXOCnt2_T, VXOCnt2_C, VXOCnt2_AR);
end structure;