------------------------------------------------------------------
-- Translated VHDL Source File
-- Auto-Generated By Xilinx's Blf2lang.
-- Copyright (c) 1999. Xilinx, Inc.
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library aim;
use aim.components.all;
library pls;
use pls.attributes.all;

entity tmgdec is
port (
    RF_Inn : in std_logic;
    EncTmgn : in std_logic;
    PhDet : in std_logic;
    Clk106MHz : in std_logic;
    VXO53MHz : in std_logic;
    RF_Inp : in std_logic;
    EncTmgp : in std_logic;
    Gap : inout std_logic;
    SGap : inout std_logic;
    FC : inout std_logic;
    VXO_Div4 : inout std_logic;
    Clk53MHzOut : out std_logic;
    Up : out std_logic;
    Down : out std_logic;
    RF_Dtct : out std_logic
     );
attribute PIN_ASSIGN of Clk106MHz : signal is "P15";
attribute PIN_ASSIGN of VXO53MHz : signal is "P18";
attribute PIN_ASSIGN of RF_Inp : signal is "P37";
attribute PIN_ASSIGN of RF_Inn : signal is "P39";
attribute PIN_ASSIGN of EncTmgp : signal is "P42";
attribute PIN_ASSIGN of EncTmgn : signal is "P43";
attribute PIN_ASSIGN of Gap : signal is "P28";
attribute PIN_ASSIGN of SGap : signal is "P21";
attribute PIN_ASSIGN of FC : signal is "P33";
attribute PIN_ASSIGN of VXO_Div4 : signal is "P44";
attribute PIN_ASSIGN of Clk53MHzOut : signal is "P34";
attribute PIN_ASSIGN of PhDet : signal is "P13";
attribute PIN_ASSIGN of Up : signal is "P23";
attribute PIN_ASSIGN of Down : signal is "P19";
attribute PIN_ASSIGN of RF_Dtct : signal is "P22";
end tmgdec;

architecture equation of tmgdec is
    signal Enc_Div2 : std_logic;
    signal S2 : std_logic;
    signal S1 : std_logic;
    signal S0 : std_logic;
    signal D1 : std_logic;
    signal D0 : std_logic;
    signal VXOCnt2 : std_logic;
    signal VXOCnt1 : std_logic;
    signal VXOCnt0 : std_logic;
    signal IDtct : std_logic;
    signal PhVXO : std_logic;
    signal PhEncTmg : std_logic;
    signal Up_xcBUF : std_logic;
    signal Up_xcOE : std_logic;
    signal Down_xcBUF : std_logic;
    signal Down_xcOE : std_logic;
    signal Gap_xcD : std_logic;
    signal Gap_xcQ : std_logic;
    signal Gap_xcCLOCK : std_logic;
    signal SGap_xcD : std_logic;
    signal SGap_xcQ : std_logic;
    signal SGap_xcCLOCK : std_logic;
    signal FC_xcD : std_logic;
    signal FC_xcQ : std_logic;
    signal FC_xcCLOCK : std_logic;
    signal VXO_Div4_xcD : std_logic;
    signal VXO_Div4_xcQ : std_logic;
    signal VXO_Div4_xcCLOCK : std_logic;
    signal Clk53MHzOut_xcD : std_logic;
    signal Clk53MHzOut_xcQ : std_logic;
    signal Clk53MHzOut_xcCLOCK : std_logic;
    signal RF_Dtct_xcD : std_logic;
    signal RF_Dtct_xcQ : std_logic;
    signal RF_Dtct_xcCLOCK : std_logic;
    signal RF_Dtct_xcR : std_logic;
    signal S2_xcD : std_logic;
    signal S2_xcQ : std_logic;
    signal S2_xcCLOCK : std_logic;
    signal S1_xcD : std_logic;
    signal S1_xcQ : std_logic;
    signal S1_xcCLOCK : std_logic;
    signal S0_xcD : std_logic;
    signal S0_xcQ : std_logic;
    signal S0_xcCLOCK : std_logic;
    signal D1_xcD : std_logic;
    signal D1_xcQ : std_logic;
    signal D1_xcCLOCK : std_logic;
    signal D0_xcD : std_logic;
    signal D0_xcQ : std_logic;
    signal D0_xcCLOCK : std_logic;
    signal VXOCnt2_xcD : std_logic;
    signal VXOCnt2_xcQ : std_logic;
    signal VXOCnt2_xcCLOCK : std_logic;
    signal VXOCnt1_xcD : std_logic;
    signal VXOCnt1_xcQ : std_logic;
    signal VXOCnt1_xcCLOCK : std_logic;
    signal VXOCnt0_xcD : std_logic;
    signal VXOCnt0_xcQ : std_logic;
    signal VXOCnt0_xcCLOCK : std_logic;
    signal IDtct_xcD : std_logic;
    signal IDtct_xcQ : std_logic;
    signal IDtct_xcCLOCK : std_logic;
    signal IDtct_xcR : std_logic;
    signal PhVXO_xcD : std_logic;
    signal PhVXO_xcQ : std_logic;
    signal PhVXO_xcCLOCK : std_logic;
    signal PhVXO_xcR : std_logic;
    signal PhEncTmg_xcD : std_logic;
    signal PhEncTmg_xcQ : std_logic;
    signal PhEncTmg_xcCLOCK : std_logic;
    signal PhEncTmg_xcR : std_logic;
    signal vcc : std_logic;
    signal gnd : std_logic;

begin
vcc <= '1';
gnd <= '0';
Gap_xcCLOCK <=  ((Clk106MHz));
Gap_xcD <= (( not(D0) and D1 and EncTmgp and Gap and  not(S0) and  not(S1) and S2)
       or  ( not(D0) and D1 and  not(EncTmgp) and  not(Gap) and  not(S0) and  not(S1) and S2));
B2LINST_1 : G_TPC port map ( Q=>Gap_xcQ, T=>Gap_xcD, CLK=>Gap_xcCLOCK, P=>gnd, C=>gnd);
Gap <=  (Gap_xcQ);

SGap_xcCLOCK <=  ((Clk106MHz));
SGap_xcD <= (( not(D0) and D1 and EncTmgp and  not(S0) and  not(S1) and S2 and SGap)
       or  (D0 and  not(D1) and EncTmgp and  not(S0) and  not(S1) and S2 and  not(SGap))
       or  ( not(D0) and  not(D1) and  not(EncTmgp) and  not(S0) and  not(S1) and S2 and  not(SGap)));
B2LINST_2 : G_TPC port map ( Q=>SGap_xcQ, T=>SGap_xcD, CLK=>SGap_xcCLOCK, P=>gnd, C=>gnd);
SGap <=  (SGap_xcQ);

FC_xcCLOCK <=  ((Clk106MHz));
FC_xcD <= (( not(D1) and EncTmgp and  not(FC) and  not(S0) and  not(S1) and S2)
       or  ( not(D0) and D1 and EncTmgp and FC and  not(S0) and  not(S1) and S2)
       or  (D0 and  not(D1) and  not(EncTmgp) and FC and  not(S0) and  not(S1) and S2));
B2LINST_3 : G_TPC port map ( Q=>FC_xcQ, T=>FC_xcD, CLK=>FC_xcCLOCK, P=>gnd, C=>gnd);
FC <=  (FC_xcQ);

VXO_Div4_xcCLOCK <=  ((VXO53MHz));
VXO_Div4_xcD <= (( not(VXOCnt0) and VXO_Div4)
       or  (VXOCnt0 and  not(VXO_Div4)));
B2LINST_4 : G_DEPC port map ( Q=>VXO_Div4_xcQ, D=>VXO_Div4_xcD, CLK=>VXO_Div4_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);
VXO_Div4 <=  (VXO_Div4_xcQ);

Clk53MHzOut_xcCLOCK <=  ((Clk106MHz));
Clk53MHzOut_xcD <= ((S0));
B2LINST_5 : G_DEPC port map ( Q=>Clk53MHzOut_xcQ, D=>Clk53MHzOut_xcD, CLK=>Clk53MHzOut_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);
Clk53MHzOut <=  (Clk53MHzOut_xcQ);

Up_xcOE <=  ((PhEncTmg and  not(PhVXO)));
Up_xcBUF <= (vcc);
Up <= (Up_xcBUF) when (Up_xcOE = '1') else 'Z';

Down_xcOE <=  (( not(PhEncTmg) and PhVXO));
Down_xcBUF <= (gnd);
Down <= (Down_xcBUF) when (Down_xcOE = '1') else 'Z';

RF_Dtct_xcCLOCK <=  ((RF_Inp));
RF_Dtct_xcR <=  (( not(IDtct) and VXOCnt0 and VXOCnt1 and  not(VXOCnt2) and VXO_Div4));
RF_Dtct_xcD <= (vcc);
B2LINST_6 : G_DEPC port map ( Q=>RF_Dtct_xcQ, D=>RF_Dtct_xcD, CLK=>RF_Dtct_xcCLOCK, E=>vcc, P=>gnd, C=>RF_Dtct_xcR);
RF_Dtct <=  (RF_Dtct_xcQ);


S2_xcCLOCK <=  ((Clk106MHz));
S2_xcD <= (( not(S0) and S2)
       or  ( not(S1) and S2)
       or  (S0 and S1 and  not(S2)));
B2LINST_7 : G_DEPC port map ( Q=>S2, D=>S2_xcD, CLK=>S2_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

S1_xcCLOCK <=  ((Clk106MHz));
S1_xcD <= (( not(S0) and S1)
       or  (EncTmgp and S0 and  not(S1))
       or  (S0 and  not(S1) and S2));
B2LINST_8 : G_DEPC port map ( Q=>S1, D=>S1_xcD, CLK=>S1_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

S0_xcCLOCK <=  ((Clk106MHz));
S0_xcD <= not ((S0)
       or  ( not(EncTmgp) and  not(S1) and  not(S2)));
B2LINST_9 : G_DEPC port map ( Q=>S0, D=>S0_xcD, CLK=>S0_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

D1_xcCLOCK <=  ((Clk106MHz));
D1_xcD <= ((D0));
B2LINST_10 : G_DEPC port map ( Q=>D1, D=>D1_xcD, CLK=>D1_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

D0_xcCLOCK <=  ((Clk106MHz));
D0_xcD <= ((EncTmgp));
B2LINST_11 : G_DEPC port map ( Q=>D0, D=>D0_xcD, CLK=>D0_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

VXOCnt2_xcCLOCK <=  ((VXO53MHz));
VXOCnt2_xcD <= (( not(VXOCnt0) and VXOCnt2)
       or  ( not(VXOCnt1) and VXOCnt2)
       or  (VXOCnt2 and  not(VXO_Div4))
       or  (VXOCnt0 and VXOCnt1 and  not(VXOCnt2) and VXO_Div4));
B2LINST_12 : G_DEPC port map ( Q=>VXOCnt2, D=>VXOCnt2_xcD, CLK=>VXOCnt2_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

VXOCnt1_xcCLOCK <=  ((VXO53MHz));
VXOCnt1_xcD <= (( not(VXOCnt0) and VXOCnt1)
       or  (VXOCnt1 and  not(VXO_Div4))
       or  (VXOCnt0 and  not(VXOCnt1) and VXO_Div4));
B2LINST_13 : G_DEPC port map ( Q=>VXOCnt1, D=>VXOCnt1_xcD, CLK=>VXOCnt1_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

VXOCnt0_xcCLOCK <=  ((VXO53MHz));
VXOCnt0_xcD <= (not (VXOCnt0));
B2LINST_14 : G_DEPC port map ( Q=>VXOCnt0, D=>VXOCnt0_xcD, CLK=>VXOCnt0_xcCLOCK, E=>vcc, P=>gnd, C=>gnd);

IDtct_xcCLOCK <=  ((RF_Inp));
IDtct_xcR <=  ((VXOCnt0 and VXOCnt1 and VXOCnt2 and VXO_Div4));
IDtct_xcD <= (vcc);
B2LINST_15 : G_DEPC port map ( Q=>IDtct, D=>IDtct_xcD, CLK=>IDtct_xcCLOCK, E=>vcc, P=>gnd, C=>IDtct_xcR);

PhVXO_xcCLOCK <=  ((VXO53MHz));
PhVXO_xcR <=  (( not(PhEncTmg))
       or  ( not(PhVXO)));
PhVXO_xcD <= (vcc);
B2LINST_16 : G_DEPC port map ( Q=>PhVXO, D=>PhVXO_xcD, CLK=>PhVXO_xcCLOCK, E=>vcc, P=>gnd, C=>PhVXO_xcR);

PhEncTmg_xcCLOCK <=  ((EncTmgp));
PhEncTmg_xcR <=  (( not(PhEncTmg))
       or  ( not(PhVXO)));
PhEncTmg_xcD <= (vcc);
B2LINST_17 : G_DEPC port map ( Q=>PhEncTmg, D=>PhEncTmg_xcD, CLK=>PhEncTmg_xcCLOCK, E=>vcc, P=>gnd, C=>PhEncTmg_xcR);

end equation;