XST D.19
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

--> Parameter TMPDIR set to .
 
--> Parameter DUMPDIR set to .
 
--> Parameter overwrite set to YES
 
--> Parameter EdifUpper set to yes
 
--> =========================================================================
---- Source Parameters
Input File Name                    : tmgdec.prj
Input Format                       : VHDL

---- Target Parameters
Output File Name                   : tmgdec.edn
Output Format                      : EDIF

---- Source Options
Entity Name                        : tmgdec
Mux Extraction                     : YES
XOR Collapsing                     : YES

---- Target Options
Family                             : 9500
Add IO Buffers                     : YES
Macro Generator                    : Macro+
MACRO Preserve                     : YES
XOR Preserve                       : YES
FF Optimization                    : YES
Flatten Hierarchy                  : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1

=========================================================================

Compiling vhdl file d:\Xilinx_CPLD\data\webpack\genff.vhd in Library genff.
Entity <g_depc> (Architecture <behavioral>) compiled.
Entity <g_tpc> (Architecture <behavioral>) compiled.
Entity <g_latpc> (Architecture <behavioral>) compiled.
Compiling vhdl file C:\WINNT\Profiles\emachado\DESKTOP\TimingChip\timdec\tmgdec.vhf in Library work.
Entity <tmgdec> (Architecture <equation>) compiled.

Analyzing Entity <tmgdec> (Architecture <equation>).
    Set property "user_defined = LOC P39" for signal <rf_inn> in unit <tmgdec>.
    Set property "user_defined = LOC P43" for signal <enctmgn> in unit <tmgdec>.
    Set property "user_defined = LOC P13" for signal <phdet> in unit <tmgdec>.
    Set property "user_defined = LOC P15" for signal <clk106mhz> in unit <tmgdec>.
    Set property "user_defined = LOC P18" for signal <vxo53mhz> in unit <tmgdec>.
    Set property "user_defined = LOC P37" for signal <rf_inp> in unit <tmgdec>.
    Set property "user_defined = LOC P42" for signal <enctmgp> in unit <tmgdec>.
    Set property "user_defined = LOC P28" for signal <gap> in unit <tmgdec>.
    Set property "user_defined = LOC P21" for signal <sgap> in unit <tmgdec>.
    Set property "user_defined = LOC P33" for signal <fc> in unit <tmgdec>.
    Set property "user_defined = LOC P44" for signal <vxo_div4> in unit <tmgdec>.
    Set property "user_defined = LOC P34" for signal <clk53mhzout> in unit <tmgdec>.
    Set property "user_defined = LOC P23" for signal <up> in unit <tmgdec>.
    Set property "user_defined = LOC P19" for signal <down> in unit <tmgdec>.
    Set property "user_defined = LOC P22" for signal <rf_dtct> in unit <tmgdec>.
Entity <tmgdec> analyzed. Unit <tmgdec> generated.

Analyzing Entity <g_tpc> (Architecture <behavioral>).
Entity <g_tpc> analyzed. Unit <g_tpc> generated.

Analyzing Entity <g_depc> (Architecture <behavioral>).
Entity <g_depc> analyzed. Unit <g_depc> generated.


Synthesizing Unit <tmgdec>.
    Extracting tristate(s) for signal <up>.
    Extracting tristate(s) for signal <down>.
WARNING : (HDL__0002). Input <rf_inn> is never used.
WARNING : (HDL__0002). Input <enctmgn> is never used.
WARNING : (HDL__0002). Input <phdet> is never used.
    Summary:
	inferred   2 Tristate(s).
Unit <tmgdec> synthesized.


Synthesizing Unit <g_tpc>.
    Extracting 1-bit register for signal <q_local>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <g_tpc> synthesized.


Synthesizing Unit <g_depc>.
    Extracting 1-bit register for signal <q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <g_depc> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 17
  1-bit register                   : 17

=========================================================================


Starting low level synthesis...

Optimizing unit <tmgdec> ...
  ncf constraint: LOC=P39		 : RF_INN
  ncf constraint: LOC=P43		 : ENCTMGN
  ncf constraint: LOC=P13		 : PHDET
  ncf constraint: LOC=P15		 : CLK106MHZ
  ncf constraint: LOC=P18		 : VXO53MHZ
  ncf constraint: LOC=P37		 : RF_INP
  ncf constraint: LOC=P42		 : ENCTMGP
  ncf constraint: LOC=P28		 : GAP
  ncf constraint: LOC=P21		 : SGAP
  ncf constraint: LOC=P33		 : FC
  ncf constraint: LOC=P44		 : VXO_DIV4
  ncf constraint: LOC=P34		 : CLK53MHZOUT
  ncf constraint: LOC=P23		 : UP
  ncf constraint: LOC=P19		 : DOWN
  ncf constraint: LOC=P22		 : RF_DTCT
=========================================================================
Final Results
Output File Name                   : tmgdec.edn
Output Format                      : edif
Optimization Criterion             : Speed
Target Technology                  : 9500
Flatten Hierarchy                  : YES
Macro Preserve                     : YES
Macro Generation                   : Macro+
XOR Preserve                       : YES

Design Statistics
# Edif Instances                   : 97
# I/Os                             : 15

Other Data
.NCF file name                     : tmgdec.ncf

=========================================================================
 
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