module tmgdec;

"Sten Hansen 		Fermilab		9-26-98

"Decodes Gap, Sync Gap and FC from 53MHz encoded data when in remote mode.
"Generates these signals internally when in local mode.
"Phase detector compares phase of incoming encoded timing with local VXO.
"Divides 53MHz by 4 for use by ST49C101 x8 frequency multiplier.
"Generates a status output when 53MHz RF is present

"Inputs..
        Clk106MHz,VXO53MHz,Reset	pin  15,18,2;
        RF_In,Rem_Loc,EncTmgp,EncTmgm	pin  37,39,42,43;

"Outputs..
	Gap,SGap,FC,VXO_Div4		pin 28,21,33,44		istype 'reg';
	Clk53MHzOut			pin 34			istype 'reg';
	PhDet				pin 13			istype 'com';
	test0, test1			pin 23, 19		istype 'com';
	RF_Dtct				pin 22			istype 'reg';

"Buried nodes..
	Enc_Div2			node istype 'reg';
	S2..S0,D1,D0			node istype 'reg';
	VXOCnt2..VXOCnt0,IDtct		node istype 'reg';

"Set Definitions..
 	VXOCnt = [VXOCnt2..VXOCnt1,VXO_Div4,VXOCnt0];
	EncTmg = EncTmgp;

"Define serial data bit patterns..
	SData  = [D1,D0,EncTmg];
	SGapHi   = [0,0,0];
	FCHi     = [0,0,1];
	FCLo     = [0,1,0];
	SGapFCHi = [0,1,1];
	GapHi    = [1,0,0];
	AllLo    = [1,0,1];

"Define serial data bit patterns.. (negative EncTmg)
"	SData  = [D1,D0,EncTmg];
"	SGapHi   = [1,1,1];
"	FCHi     = [1,1,0];
"	FCLo     = [1,0,1];
"	SGapFCHi = [1,0,0];
"	GapHi    = [0,1,1];
"	AllLo    = [0,1,0];

"State definitions..
	IState = [S2..S0];
	IdleLo = [0,0,0]; "0
	IdleHi = [0,0,1]; "1
	Shft0  = [0,1,0]; "2
	Shft1  = [0,1,1]; "3
	Shft2  = [1,0,0]; "4
	Shft3  = [1,0,1]; "5
	Shft4  = [1,1,0]; "6
	Shft5  = [1,1,1]; "7

Equations

     [Gap.C,SGap.C,FC.C,Clk53MHzOut.C,IState.C,D1.C,D0.C] = Clk106MHz;

"looking at states
      test0 = S0;
      test1 = S1;

"Clocks for phase detector related signals..
      Enc_Div2.C = EncTmg;
      VXOCnt.C = VXO53MHz;

"     [Gap.AR,SGap.AR,FC.AR,Clk53MHzOut.AR,IState.AR,VXOCnt.AR,
"     PS.AR,XCnt.AR,D1.AR,D0.AR,Enc_Div2.AR] = Reset;

"Reset internal clock detect periodically
     IDtct.C = RF_In;
     IDtct := 1;
     IDtct.AR = (VXOCnt == 15);

"Arrange for external clock detect to be a DC level for less EMI
     RF_Dtct.C = RF_In;
     RF_Dtct := 1;
     RF_Dtct.AR = !IDtct & (VXOCnt == 7);

"Use bit 1 of the counter as VXO/4 to get correct frequency for x8 multiplier
     VXOCnt := (VXOCnt + 1);

"Keep clock in phase with encoded clock, or with internal signal generator..
     Clk53MHzOut := ((IState == IdleHi) # (IState == Shft1)
		   # (IState == Shft3)  # (IState == Shft5));

"Divide input by 2 to get 50% duty cycle before phase comparison
     Enc_Div2.T := 1;

"Phase detector is just an XOR..
    PhDet = Enc_Div2 $ VXOCnt0;

" Shift in 2 data bits from Encoded Clock stream
     D0 := EncTmg;
     D1 := D0;

" Once data is shifted in, output transitions depend on the resulting
" 3 bit pattern (D1,D0,Encoded Clock) if in remote mode. In local mode
" outputs are dependent on internal counter values (XCnt)

SGap.T := !SGap & ((IState == Shft2)
		& ((SData == SGapHi) # (SData == SGapFCHi)))
         # SGap & ((IState == Shft2) & (SData == AllLo));

FC.T := !FC & ((IState == Shft2)
		& ((SData == FCHi) # (SData == SGapFCHi)))
        # FC & ((IState == Shft2)
		& ((SData == FCLo) # (SData == AllLo)));

Gap.T := !Gap & ((IState == Shft2) & (SData == GapHi))
         # Gap & ((IState == Shft2) & (SData == AllLo));

State_Diagram IState

"Bounce between IdleLo and IdleHi until EncTmg is high for 2 cycles..
State IdleLo: If EncTmg then IdleHi else IdleLo;
State IdleHi: If !EncTmg then IdleLo else Shft0;

"Go through a total of 8 states before looking for another pattern..
State Shft0: goto Shft1;
State Shft1: goto Shft2;
State Shft2: goto Shft3;
State Shft3: goto Shft4;
State Shft4: goto Shft5;
State Shft5: goto IdleLo;

end tmgdec;