#$ TOOL iSE 3.01
#$ DATE Fri Sep 15 14:09:07 2000
#$ MODULE tmgdec
#$ JEDECFILE tmgdec
#$ PINS 15 Clk106MHz:15 VXO53MHz:18 RF_Inp:37 RF_Inn:39 EncTmgp:42 EncTmgn:43 Gap:28 \
#  SGap:21 FC:33 VXO_Div4:44 Clk53MHzOut:34 PhDet:13 Up:23 Down:19 RF_Dtct:22
#$ NODES 12 Enc_Div2'ud'  S2'ud'  S1'ud'  S0'ud'  D1'ud'  D0'ud'  VXOCnt2'ud'  VXOCnt1'ud'  VXOCnt0'ud'  IDtct'ud'  \
#  PhVXO'ud'  PhEncTmg'ud' 
.model tmgdec
.inputs Clk106MHz.BLIF EncTmgp.BLIF VXO53MHz.BLIF RF_Inp.BLIF VXOCnt0.BLIF \
VXO_Div4.BLIF VXOCnt1.BLIF VXOCnt2.BLIF IDtct.BLIF S0.BLIF S1.BLIF S2.BLIF \
PhVXO.BLIF PhEncTmg.BLIF D0.BLIF SGap.BLIF D1.BLIF FC.BLIF Gap.BLIF S2.FB \
S1.FB S0.FB
.outputs Up Down Gap.C SGap.C FC.C Clk53MHzOut.C S2.C S1.C S0.C D1.C D0.C \
Enc_Div2.C VXOCnt2.C VXOCnt1.C VXO_Div4.C VXOCnt0.C IDtct.C IDtct.REG IDtct.AR \
RF_Dtct.C RF_Dtct.REG RF_Dtct.AR VXOCnt2.REG.X1 VXOCnt2.REG.X2 VXOCnt1.REG.X1 \
VXOCnt1.REG.X2 VXO_Div4.REG.X1 VXO_Div4.REG.X2 VXOCnt0.REG Clk53MHzOut.REG \
PhVXO.C PhVXO.REG PhVXO.AR PhEncTmg.C PhEncTmg.REG PhEncTmg.AR Down.OE Up.OE \
D0.REG D1.REG SGap.T FC.T Gap.T S0.REG S1.REG S2.REG
.names Up
 1
.names Down
.names IDtct.REG
 1
.names VXOCnt0.BLIF VXO_Div4.BLIF VXOCnt1.BLIF VXOCnt2.BLIF IDtct.AR
1111 1
.names RF_Dtct.REG
 1
.names VXOCnt0.BLIF VXO_Div4.BLIF VXOCnt1.BLIF VXOCnt2.BLIF IDtct.BLIF \
RF_Dtct.AR
11100 1
.names VXOCnt0.BLIF VXO_Div4.BLIF VXOCnt1.BLIF VXOCnt2.REG.X2
111 1
.names VXOCnt0.BLIF VXO_Div4.BLIF VXOCnt1.REG.X2
11 1
.names VXOCnt0.BLIF VXOCnt0.REG
0 1
.names PhVXO.REG
 1
.names PhVXO.BLIF PhEncTmg.BLIF PhVXO.AR
-0 1
0- 1
.names PhEncTmg.REG
 1
.names PhVXO.BLIF PhEncTmg.BLIF PhEncTmg.AR
-0 1
0- 1
.names PhVXO.BLIF PhEncTmg.BLIF Down.OE
10 1
.names PhVXO.BLIF PhEncTmg.BLIF Up.OE
01 1
.names EncTmgp.BLIF S0.BLIF S1.BLIF S2.BLIF D0.BLIF SGap.BLIF D1.BLIF SGap.T
1001011 1
0001000 1
1001100 1
.names EncTmgp.BLIF S0.BLIF S1.BLIF S2.BLIF D0.BLIF D1.BLIF FC.BLIF FC.T
0001101 1
1001011 1
1001-00 1
.names EncTmgp.BLIF S0.BLIF S1.BLIF S2.BLIF D0.BLIF D1.BLIF Gap.BLIF Gap.T
0001010 1
1001011 1
.names EncTmgp.BLIF S2.FB S1.FB S0.FB S0.REG
1--0 1
-1-0 1
--10 1
.names EncTmgp.BLIF S2.FB S1.FB S0.FB S1.REG
1-01 1
--10 1
-101 1
.names S2.FB S1.FB S0.FB S2.REG
011 1
1-0 1
10- 1
.names Clk106MHz.BLIF Gap.C
1 1
0 0
.names Clk106MHz.BLIF SGap.C
1 1
0 0
.names Clk106MHz.BLIF FC.C
1 1
0 0
.names Clk106MHz.BLIF Clk53MHzOut.C
1 1
0 0
.names Clk106MHz.BLIF S2.C
1 1
0 0
.names Clk106MHz.BLIF S1.C
1 1
0 0
.names Clk106MHz.BLIF S0.C
1 1
0 0
.names Clk106MHz.BLIF D1.C
1 1
0 0
.names Clk106MHz.BLIF D0.C
1 1
0 0
.names EncTmgp.BLIF Enc_Div2.C
1 1
0 0
.names VXO53MHz.BLIF VXOCnt2.C
1 1
0 0
.names VXO53MHz.BLIF VXOCnt1.C
1 1
0 0
.names VXO53MHz.BLIF VXO_Div4.C
1 1
0 0
.names VXO53MHz.BLIF VXOCnt0.C
1 1
0 0
.names RF_Inp.BLIF IDtct.C
1 1
0 0
.names RF_Inp.BLIF RF_Dtct.C
1 1
0 0
.names VXOCnt2.BLIF VXOCnt2.REG.X1
1 1
0 0
.names VXOCnt1.BLIF VXOCnt1.REG.X1
1 1
0 0
.names VXO_Div4.BLIF VXO_Div4.REG.X1
1 1
0 0
.names VXOCnt0.BLIF VXO_Div4.REG.X2
1 1
0 0
.names S0.BLIF Clk53MHzOut.REG
1 1
0 0
.names VXO53MHz.BLIF PhVXO.C
1 1
0 0
.names EncTmgp.BLIF PhEncTmg.C
1 1
0 0
.names EncTmgp.BLIF D0.REG
1 1
0 0
.names D0.BLIF D1.REG
1 1
0 0
.end