0002 |
0003 |"Sten Hansen 		Fermilab		9-26-98
0004 |
0005 |"Decodes Gap, Sync Gap and FC from 53MHz encoded data when in remote mode.
0006 |"Generates these signals internally when in local mode.
0007 |"Phase detector compares phase of incoming encoded timing with local VXO.
0008 |"Divides 53MHz by 4 for use by ST49C101 x8 frequency multiplier.
0009 |"Generates a status output when 53MHz RF is present
0010 |
0011 |"Inputs..
0012 |	Clk106MHz,VXO53MHz						pin  15,18;
0013 |	RF_Inp,RF_Inn,EncTmgp,EncTmgn			pin  37,39,42,43;
0014 |
0015 |"Outputs..
0016 |	Gap,SGap,FC,VXO_Div4						pin 28,21,33,44		istype 'reg';
0017 |	Clk53MHzOut									pin 34					istype 'reg';
0018 |	PhDet											pin 13					istype 'com';
0019 |	Up, Down										pin 23, 19				istype 'com';
0020 |	RF_Dtct										pin 22					istype 'reg';
0021 |
0022 |"Buried nodes..
0023 |	Enc_Div2										node 						istype 'reg';
0024 |	S2..S0,D1,D0								node 						istype 'reg';
0025 |	VXOCnt2..VXOCnt0,IDtct					node 						istype 'reg';
0026 |	PhVXO, PhEncTmg							node 						istype 'reg';
0027 |					
0028 |
0029 |	"Set Definitions..
0030 | 	VXOCnt = [VXOCnt2..VXOCnt1,VXO_Div4,VXOCnt0];
0031 |	EncTmg = EncTmgp;
0032 |	RF_In = RF_Inp;
0033 |
0034 |"Define serial data bit patterns..
0035 |	SData  = [D1,D0,EncTmg];
0036 |	SGapHi   = [0,0,0];
0037 |	FCHi     = [0,0,1];
0038 |	FCLo     = [0,1,0];
0039 |	SGapFCHi = [0,1,1];
0040 |	GapHi    = [1,0,0];
0041 |	AllLo    = [1,0,1];
0042 |
0043 |"State definitions..
0044 |	IState = [S2..S0];
0045 |	IdleLo = [0,0,0]; "0
0046 |	IdleHi = [0,0,1]; "1
0047 |	Shft0  = [0,1,0]; "2
0048 |	Shft1  = [0,1,1]; "3
0049 |	Shft2  = [1,0,0]; "4
0050 |	Shft3  = [1,0,1]; "5
0051 |	Shft4  = [1,1,0]; "6
0052 |	Shft5  = [1,1,1]; "7
0053 |
0054 |Equations
0055 |
0056 |	[Gap.C,SGap.C,FC.C,Clk53MHzOut.C,IState.C,D1.C,D0.C] = Clk106MHz;
0057 |
0058 |"Clocks for phase detector related signals..
0059 |	Enc_Div2.C = EncTmg;
0060 |	VXOCnt.C = VXO53MHz;
0061 |
0062 |"Reset internal clock detect periodically
0063 |	IDtct.C = RF_In;
0064 |	IDtct := 1;
0065 |	IDtct.AR = (VXOCnt == 15);
0066 |
0067 |"Arrange for external clock detect to be a DC level for less EMI
0068 |	RF_Dtct.C = RF_In;
0069 |	RF_Dtct := 1;
0070 |	RF_Dtct.AR = !IDtct & (VXOCnt == 7);
0071 |
0072 |"Use bit 1 of the counter as VXO/4 to get correct frequency for x8 multiplier
0073 |	VXOCnt := (VXOCnt + 1);
0074 |
0075 |"Keep clock in phase with encoded clock, or with internal signal generator..
0076 |	Clk53MHzOut := ((IState == IdleHi) # (IState == Shft1)
0077 |						# (IState == Shft3)  # (IState == Shft5));
0078 |
0079 |" New PLL circuitry
0080 |	PhVXO.C = VXO53MHz;
0081 |	PhVXO := 1;
0082 |	PhVXO.AR = !(PhVXO & PhEncTmg);
0083 |
0084 |	PhEncTmg.C = EncTmg;
0085 |	PhEncTmg := 1;
0086 |	PhEncTmg.AR = !(PhVXO & PhEncTmg);
0087 |
0088 |	Down = 0;
0089 |	Down.OE = PhVXO & !PhEncTmg;
0090 |
0091 |	Up = 1;
0092 |	Up.OE = !PhVXO & PhEncTmg;
0093 |
0094 |" Shift in 2 data bits from Encoded Clock stream
0095 |	D0 := EncTmg;
0096 |	D1 := D0;
0097 |
0098 |" Once data is shifted in, output transitions depend on the resulting
0099 |" 3 bit pattern (D1,D0,Encoded Clock) if in remote mode. In local mode
0100 |" outputs are dependent on internal counter values (XCnt)
0101 |
0102 |SGap.T := !SGap & ((IState == Shft2)
                ^
Warning 1043: Register type mismatch for output 'SGap'.
                  ^
Warning 1126: Can't use ':=' operator with dot extensions.
0103 |			& ((SData == SGapHi) # (SData == SGapFCHi)))
0104 |         # SGap & ((IState == Shft2) & (SData == AllLo));
0105 |
0106 |FC.T := !FC & ((IState == Shft2)
              ^
Warning 1043: Register type mismatch for output 'FC'.
                ^
Warning 1126: Can't use ':=' operator with dot extensions.
0107 |		& ((SData == FCHi) # (SData == SGapFCHi)))
0108 |        # FC & ((IState == Shft2)
0109 |		& ((SData == FCLo) # (SData == AllLo)));
0110 |
0111 |Gap.T := !Gap & ((IState == Shft2) & (SData == GapHi))
               ^
Warning 1043: Register type mismatch for output 'Gap'.
                 ^
Warning 1126: Can't use ':=' operator with dot extensions.
0112 |         # Gap & ((IState == Shft2) & (SData == AllLo));
0113 |
0114 |State_Diagram IState
0115 |
0116 |"Bounce between IdleLo and IdleHi until EncTmg is high for 2 cycles..
0117 |State IdleLo: If EncTmg then IdleHi else IdleLo;
0118 |State IdleHi: If !EncTmg then IdleLo else Shft0;
0119 |
0120 |"Go through a total of 8 states before looking for another pattern..
0121 |State Shft0: goto Shft1;
0122 |State Shft1: goto Shft2;
0123 |State Shft2: goto Shft3;
0124 |State Shft3: goto Shft4;
0125 |State Shft4: goto Shft5;
0126 |State Shft5: goto IdleLo;
0127 |
0128 |end tmgdec;