"Program: xplafit version 3.21
"tmgdec.ann created on:Jan 18 18:16:00 2001
module tmgdec
Title ' '

"******** 4 Input Pins **********
VXO53MHz                            PIN 	18;
Clk106MHz                           PIN 	15;
EncTmgp                             PIN 	42;
RF_In                               PIN 	37;
"******** 9 Output Pins **********
VXO_Div4                            PIN 	44;
FC                                  PIN 	33;
SGap                                PIN 	21;
Gap                                 PIN 	28;
Clk53MHzOut                         PIN 	34;
PhDet                               PIN 	13;
test1                               PIN 	19;
test0                               PIN 	23;
RF_Dtct                             PIN 	22;
"******** 8 Nodes **********
Enc_Div2                            NODE	48;
D0                                  NODE	51;
D1                                  NODE	52;
S2                                  NODE	54;
IDtct                               NODE	46;
VXOCnt0                             NODE	49;
VXOCnt1                             NODE	45;
VXOCnt2                             NODE	53;


equations

"**********( VXOCnt2 )************
VXOCnt2.clk	=  VXO53MHz;
VXOCnt2.t	=  VXO_Div4.Q &  VXOCnt0.Q &  VXOCnt1.Q ;
"**********( VXOCnt1 )************
VXOCnt1.clk	=  VXO53MHz;
VXOCnt1.t	=  VXO_Div4.Q &  VXOCnt0.Q ;
"**********( VXO_Div4 )************
VXO_Div4.clk	=  VXO53MHz;
VXO_Div4.t	=  VXOCnt0.Q ;
"**********( IDtct )************
IDtct.clk	=  RF_In;
IDtct.ar	=  VXO_Div4.Q &  VXOCnt0.Q &  VXOCnt1.Q &  VXOCnt2.Q ;
IDtct.d	= 1;
"**********( Enc_Div2 )************
Enc_Div2.clk	=  EncTmgp;
Enc_Div2.t	= 1;
"**********( VXOCnt0 )************
VXOCnt0.clk	=  VXO53MHz;
VXOCnt0.t	= 1;
"**********( D0 )************
D0.clk	=  Clk106MHz;
D0.d	=  EncTmgp ;
"**********( D1 )************
D1.clk	=  Clk106MHz;
D1.d	=  D0.Q ;
"**********( S2 )************
S2.clk	=  Clk106MHz;
S2.t	=  test1.Q &  test0.Q ;
"**********( PhDet )************
PhDet	= !Enc_Div2.Q &  VXOCnt0.Q 
		#  Enc_Div2.Q & !VXOCnt0.Q ;
"**********( test1 )************
test1.clk	=  Clk106MHz;
test1.t	= !(!test0.Q 
		# !EncTmgp & !S2.Q & !test1.Q );
"**********( SGap )************
SGap.clk	=  Clk106MHz;
SGap.t	= !D0.Q &  EncTmgp &  SGap.Q &  D1.Q &  S2.Q & !test1.Q 
		& !test0.Q 
		#  D0.Q &  EncTmgp & !SGap.Q & !D1.Q &  S2.Q & !test1.Q 
		& !test0.Q 
		# !D0.Q & !EncTmgp & !SGap.Q & !D1.Q &  S2.Q & !test1.Q 
		& !test0.Q ;
"**********( RF_Dtct )************
RF_Dtct.clk	=  RF_In;
RF_Dtct.ar	=  VXO_Div4.Q &  VXOCnt0.Q & !IDtct.Q &  VXOCnt1.Q & !VXOCnt2.Q ;
RF_Dtct.d	= 1;
"**********( test0 )************
test0.clk	=  Clk106MHz;
test0.t	= !(!EncTmgp & !S2.Q & !test1.Q & !test0.Q );
"**********( Gap )************
Gap.clk	=  Clk106MHz;
Gap.t	=  Gap.Q & !D0.Q &  EncTmgp & !test1.Q &  D1.Q &  S2.Q 
		& !test0.Q 
		# !Gap.Q & !D0.Q & !EncTmgp & !test1.Q &  D1.Q &  S2.Q 
		& !test0.Q ;
"**********( FC )************
FC.clk	=  Clk106MHz;
FC.t	=  FC.Q & !D0.Q &  EncTmgp & !test1.Q &  D1.Q &  S2.Q 
		& !test0.Q 
		#  FC.Q &  D0.Q & !EncTmgp & !test1.Q & !D1.Q &  S2.Q 
		& !test0.Q 
		# !FC.Q &  EncTmgp & !test1.Q & !D1.Q &  S2.Q & !test0.Q ;
"**********( Clk53MHzOut )************
Clk53MHzOut.clk	=  Clk106MHz;
Clk53MHzOut.d	=  test0.Q ;

end