--------------------------------------------------------------------------- -- VHDL Timing Model -- Converted from JEDEC file -- Created by Xilinx, Inc. -- Program: xplafit version 3.40 -- Design Name = tmgdec -- Device Name = xcr5064-7vq44c -- Sep 15 14:09:19 2000 --------------------------------------------------------------------------- package pxa_pkg is constant tpd0 : time := 0 ps; constant tpd1 : time := 6000 ps; constant tpd2 : time := 8000 ps; constant tclk : time := 2000 ps; constant tap2q: time := 4000 ps; constant tar2q: time := 4000 ps; constant trd : time := 2000 ps; constant tbuf : time := 1500 ps; constant toe : time := 4000 ps; end pxa_pkg; --------------------------------------------------------------------------- -- Components Defined Here --------------------------------------------------------------------------- -- Output Buffer library ieee; use ieee.std_logic_1164.all; use work.pxa_pkg.all; entity pxa_bufif1 is Port (O: out std_logic; I, OE : in std_logic); end pxa_bufif1; architecture behavioral of pxa_bufif1 is begin O <= I after tbuf when OE='1' else 'Z' after toe; end behavioral; -- D Flip Flop with Asynchronous Reset library ieee; use ieee.std_logic_1164.all; use work.pxa_pkg.all; entity pxa_dff_ar_p0 is port (Q : Out std_logic; D, CLK, AR : In std_logic); end pxa_dff_ar_p0; architecture behavioral of pxa_dff_ar_p0 is signal Q_local: std_logic := '0'; begin process(CLK, AR) begin if AR = '1' then Q_local <= '0' after tar2q; elsif rising_edge(CLK) then Q_local <= D after trd; end if; end process; Q <= Q_local; end behavioral; -- D flip flop with Asynchronous Preset library ieee; use ieee.std_logic_1164.all; use work.pxa_pkg.all; entity pxa_dff_ap_p0 is port (Q : Out std_logic; D, CLK, AP : In std_logic); end pxa_dff_ap_p0; architecture behavioral of pxa_dff_ap_p0 is signal Q_local: std_logic := '0'; begin process(CLK, AP) begin if AP = '1' then Q_local <= '1' after tap2q; elsif rising_edge(CLK) then Q_local <= D after trd; end if; end process; Q <= Q_local; end behavioral; -- T Flip Flop with Asynchronous Reset library ieee; use ieee.std_logic_1164.all; use work.pxa_pkg.all; entity pxa_tff_ar_p0 is port (Q : out std_logic; T, CLK, AR : in std_logic); end pxa_tff_ar_p0; architecture behavioral of pxa_tff_ar_p0 is signal Q_local: std_logic := '0'; begin process(CLK, AR) begin if AR = '1' then Q_local <= '0' after tar2q; elsif rising_edge(CLK) then if T = '1' then Q_local <= not Q_local after trd ; end if; end if; end process; Q <= Q_local; end behavioral; -- T Flip Flop with Asynchronous Preset library ieee; use ieee.std_logic_1164.all; use work.pxa_pkg.all; entity pxa_tff_ap_p0 is port (Q : out std_logic; T, CLK, AP : in std_logic); end pxa_tff_ap_p0; architecture behavioral of pxa_tff_ap_p0 is signal Q_local: std_logic := '0'; begin process(CLK, AP) begin if AP = '1' then Q_local <= '1' after tap2q; elsif rising_edge(CLK) then if T = '1' then Q_local <= not Q_local after trd ; end if; end if; end process; Q <= Q_local; end behavioral; --------------------------------------------------------------------------- -- Main VHDL Model --------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.pxa_pkg.all; entity tmgdec is port(CLK106MHZ: in std_logic; ENCTMGP: in std_logic; RF_INP: in std_logic; VXO53MHZ: in std_logic; CLK53MHZOUT: out std_logic; DOWN: out std_logic; FC: out std_logic; GAP: out std_logic; RF_DTCT: out std_logic; SGAP: out std_logic; UP: out std_logic; VXO_DIV4: out std_logic); end tmgdec; architecture structure of tmgdec is -- Signal Declaration ------------------------------- signal CLK53MHZOUT_D, CLK53MHZOUT_OE, CLK53MHZOUT_Q, CLK53MHZOUT_C, CLK53MHZOUT_AP, CLK53MHZOUT_AR, DOWN_COM, DOWN_OE, FC_T, FC_OE, FC_Q, FC_C, FC_AP, FC_AR, GAP_T, GAP_OE, GAP_Q, GAP_C, GAP_AP, GAP_AR, RF_DTCT_T, RF_DTCT_OE, RF_DTCT_Q, RF_DTCT_C, RF_DTCT_AP, RF_DTCT_AR, SGAP_T, SGAP_OE, SGAP_Q, SGAP_C, SGAP_AP, SGAP_AR, UP_COM, UP_OE, VXO_DIV4_T, VXO_DIV4_OE, VXO_DIV4_Q, VXO_DIV4_C, VXO_DIV4_AP, VXO_DIV4_AR, B2LINST_10_I_Q, B2LINST_10_I_Q_D, B2LINST_10_I_Q_C, B2LINST_10_I_Q_AP, B2LINST_10_I_Q_AR, B2LINST_11_I_Q, B2LINST_11_I_Q_D, B2LINST_11_I_Q_C, B2LINST_11_I_Q_AP, B2LINST_11_I_Q_AR, B2LINST_12_I_Q, B2LINST_12_I_Q_T, B2LINST_12_I_Q_C, B2LINST_12_I_Q_AP, B2LINST_12_I_Q_AR, B2LINST_13_I_Q, B2LINST_13_I_Q_T, B2LINST_13_I_Q_C, B2LINST_13_I_Q_AP, B2LINST_13_I_Q_AR, B2LINST_14_I_Q, B2LINST_14_I_Q_T, B2LINST_14_I_Q_C, B2LINST_14_I_Q_AP, B2LINST_14_I_Q_AR, B2LINST_15_I_Q, B2LINST_15_I_Q_T, B2LINST_15_I_Q_C, B2LINST_15_I_Q_AP, B2LINST_15_I_Q_AR, B2LINST_16_I_Q, B2LINST_16_I_Q_T, B2LINST_16_I_Q_C, B2LINST_16_I_Q_AP, B2LINST_16_I_Q_AR, B2LINST_17_I_Q, B2LINST_17_I_Q_T, B2LINST_17_I_Q_C, B2LINST_17_I_Q_AP, B2LINST_17_I_Q_AR, B2LINST_7_I_Q, B2LINST_7_I_Q_T, B2LINST_7_I_Q_C, B2LINST_7_I_Q_AP, B2LINST_7_I_Q_AR, B2LINST_8_I_Q, B2LINST_8_I_Q_T, B2LINST_8_I_Q_C, B2LINST_8_I_Q_AP, B2LINST_8_I_Q_AR, B2LINST_9_I_Q, B2LINST_9_I_Q_T, B2LINST_9_I_Q_C, B2LINST_9_I_Q_AP, B2LINST_9_I_Q_AR : std_logic; signal VCC : std_logic; signal GND : std_logic; component pxa_bufif1 Port (O: out std_logic; I, OE : in std_logic); end component; component pxa_dff_ap_p0 port (Q : out std_logic; D, CLK, AP : in std_logic); end component; component pxa_dff_ar_p0 port (Q : out std_logic; D, CLK, AR : in std_logic); end component; component pxa_tff_ap_p0 port (Q : out std_logic; T, CLK, AP : in std_logic); end component; component pxa_tff_ar_p0 port (Q : out std_logic; T, CLK, AR : in std_logic); end component; begin -- Equations: VCC <= '1'; GND <= '0'; ------( CLK53MHZOUT )-------------------------------------------------------- CLK53MHZOUT_D <= ((B2LINST_9_I_Q)) after tpd1; CLK53MHZOUT_OE <= (VCC) after tpd0; CLK53MHZOUT_buf: pxa_bufif1 port map (CLK53MHZOUT, CLK53MHZOUT_Q, CLK53MHZOUT_OE); CLK53MHZOUT_AP <= (GND) after tpd0; CLK53MHZOUT_AR <= (GND) after tpd0; CLK53MHZOUT_C <= (CLK106MHZ) after tclk; CLK53MHZOUT_ff: pxa_dff_ar_p0 port map (CLK53MHZOUT_Q, CLK53MHZOUT_D, CLK53MHZOUT_C, CLK53MHZOUT_AR); ------( DOWN )--------------------------------------------------------------- DOWN_COM <= (GND) after tpd0; DOWN_OE <= (B2LINST_16_I_Q and not B2LINST_17_I_Q) after tpd1; DOWN_buf: pxa_bufif1 port map (DOWN, DOWN_COM, DOWN_OE); ------( FC )----------------------------------------------------------------- FC_T <= ((not B2LINST_9_I_Q and B2LINST_11_I_Q and not ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and not B2LINST_10_I_Q and FC_Q) or (not B2LINST_9_I_Q and not B2LINST_11_I_Q and ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and B2LINST_10_I_Q and FC_Q) or (not B2LINST_9_I_Q and ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and not B2LINST_10_I_Q and not FC_Q)) after tpd1; FC_OE <= (VCC) after tpd0; FC_buf: pxa_bufif1 port map (FC, FC_Q, FC_OE); FC_AP <= (GND) after tpd0; FC_AR <= (GND) after tpd0; FC_C <= (CLK106MHZ) after tclk; FC_ff: pxa_tff_ar_p0 port map(FC_Q, FC_T, FC_C, FC_AR); ------( GAP )---------------------------------------------------------------- GAP_T <= ((GAP_Q and not B2LINST_9_I_Q and not B2LINST_11_I_Q and ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and B2LINST_10_I_Q) or (not GAP_Q and not B2LINST_9_I_Q and not B2LINST_11_I_Q and not ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and B2LINST_10_I_Q)) after tpd1; GAP_OE <= (VCC) after tpd0; GAP_buf: pxa_bufif1 port map (GAP, GAP_Q, GAP_OE); GAP_AP <= (GND) after tpd0; GAP_AR <= (GND) after tpd0; GAP_C <= (CLK106MHZ) after tclk; GAP_ff: pxa_tff_ar_p0 port map(GAP_Q, GAP_T, GAP_C, GAP_AR); ------( RF_DTCT )------------------------------------------------------------ RF_DTCT_T <= ((not RF_DTCT_Q)) after tpd1; RF_DTCT_OE <= (VCC) after tpd0; RF_DTCT_buf: pxa_bufif1 port map (RF_DTCT, RF_DTCT_Q, RF_DTCT_OE); RF_DTCT_AP <= (GND) after tpd0; RF_DTCT_AR <= (VXO_DIV4_Q and not B2LINST_15_I_Q and B2LINST_13_I_Q and B2LINST_14_I_Q and not B2LINST_12_I_Q) after tpd1; RF_DTCT_C <= (RF_INP) after tclk; RF_DTCT_ff: pxa_tff_ar_p0 port map(RF_DTCT_Q, RF_DTCT_T, RF_DTCT_C, RF_DTCT_AR); ------( SGAP )--------------------------------------------------------------- SGAP_T <= ((not B2LINST_9_I_Q and not B2LINST_11_I_Q and ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and SGAP_Q and B2LINST_10_I_Q) or (not B2LINST_9_I_Q and B2LINST_11_I_Q and ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and not SGAP_Q and not B2LINST_10_I_Q) or (not B2LINST_9_I_Q and not B2LINST_11_I_Q and not ENCTMGP and not B2LINST_8_I_Q and B2LINST_7_I_Q and not SGAP_Q and not B2LINST_10_I_Q)) after tpd1; SGAP_OE <= (VCC) after tpd0; SGAP_buf: pxa_bufif1 port map (SGAP, SGAP_Q, SGAP_OE); SGAP_AP <= (GND) after tpd0; SGAP_AR <= (GND) after tpd0; SGAP_C <= (CLK106MHZ) after tclk; SGAP_ff: pxa_tff_ar_p0 port map(SGAP_Q, SGAP_T, SGAP_C, SGAP_AR); ------( UP )----------------------------------------------------------------- UP_COM <= (VCC) after tpd0; UP_OE <= (not B2LINST_16_I_Q and B2LINST_17_I_Q) after tpd1; UP_buf: pxa_bufif1 port map (UP, UP_COM, UP_OE); ------( VXO_DIV4 )----------------------------------------------------------- VXO_DIV4_T <= ((B2LINST_14_I_Q)) after tpd1; VXO_DIV4_OE <= (VCC) after tpd0; VXO_DIV4_buf: pxa_bufif1 port map (VXO_DIV4, VXO_DIV4_Q, VXO_DIV4_OE); VXO_DIV4_AP <= (GND) after tpd0; VXO_DIV4_AR <= (GND) after tpd0; VXO_DIV4_C <= (VXO53MHZ) after tclk; VXO_DIV4_ff: pxa_tff_ar_p0 port map(VXO_DIV4_Q, VXO_DIV4_T, VXO_DIV4_C, VXO_DIV4_AR); ------( B2LINST_10_I_Q )----------------------------------------------------- B2LINST_10_I_Q_D <= ((B2LINST_11_I_Q)) after tpd1; B2LINST_10_I_Q_AP <= (GND) after tpd0; B2LINST_10_I_Q_AR <= (GND) after tpd0; B2LINST_10_I_Q_C <= (CLK106MHZ) after tclk; B2LINST_10_I_Q_ff: pxa_dff_ar_p0 port map(B2LINST_10_I_Q, B2LINST_10_I_Q_D, B2LINST_10_I_Q_C, B2LINST_10_I_Q_AR); ------( B2LINST_11_I_Q )----------------------------------------------------- B2LINST_11_I_Q_D <= ((ENCTMGP)) after tpd1; B2LINST_11_I_Q_AP <= (GND) after tpd0; B2LINST_11_I_Q_AR <= (GND) after tpd0; B2LINST_11_I_Q_C <= (CLK106MHZ) after tclk; B2LINST_11_I_Q_ff: pxa_dff_ar_p0 port map(B2LINST_11_I_Q, B2LINST_11_I_Q_D, B2LINST_11_I_Q_C, B2LINST_11_I_Q_AR); ------( B2LINST_12_I_Q )----------------------------------------------------- B2LINST_12_I_Q_T <= ((VXO_DIV4_Q and B2LINST_13_I_Q and B2LINST_14_I_Q)) after tpd1; B2LINST_12_I_Q_AP <= (GND) after tpd0; B2LINST_12_I_Q_AR <= (GND) after tpd0; B2LINST_12_I_Q_C <= (VXO53MHZ) after tclk; B2LINST_12_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_12_I_Q, B2LINST_12_I_Q_T, B2LINST_12_I_Q_C, B2LINST_12_I_Q_AR); ------( B2LINST_13_I_Q )----------------------------------------------------- B2LINST_13_I_Q_T <= ((VXO_DIV4_Q and B2LINST_14_I_Q)) after tpd1; B2LINST_13_I_Q_AP <= (GND) after tpd0; B2LINST_13_I_Q_AR <= (GND) after tpd0; B2LINST_13_I_Q_C <= (VXO53MHZ) after tclk; B2LINST_13_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_13_I_Q, B2LINST_13_I_Q_T, B2LINST_13_I_Q_C, B2LINST_13_I_Q_AR); ------( B2LINST_14_I_Q )----------------------------------------------------- B2LINST_14_I_Q_T <= (VCC) after tpd0; B2LINST_14_I_Q_AP <= (GND) after tpd0; B2LINST_14_I_Q_AR <= (GND) after tpd0; B2LINST_14_I_Q_C <= (VXO53MHZ) after tclk; B2LINST_14_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_14_I_Q, B2LINST_14_I_Q_T, B2LINST_14_I_Q_C, B2LINST_14_I_Q_AR); ------( B2LINST_15_I_Q )----------------------------------------------------- B2LINST_15_I_Q_T <= ((not B2LINST_15_I_Q)) after tpd1; B2LINST_15_I_Q_AP <= (GND) after tpd0; B2LINST_15_I_Q_AR <= (VXO_DIV4_Q and B2LINST_13_I_Q and B2LINST_14_I_Q and B2LINST_12_I_Q) after tpd1; B2LINST_15_I_Q_C <= (RF_INP) after tclk; B2LINST_15_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_15_I_Q, B2LINST_15_I_Q_T, B2LINST_15_I_Q_C, B2LINST_15_I_Q_AR); ------( B2LINST_16_I_Q )----------------------------------------------------- B2LINST_16_I_Q_T <= ((not B2LINST_16_I_Q)) after tpd1; B2LINST_16_I_Q_AP <= (GND) after tpd0; B2LINST_16_I_Q_AR <= not (B2LINST_16_I_Q and B2LINST_17_I_Q) after tpd1; B2LINST_16_I_Q_C <= (VXO53MHZ) after tclk; B2LINST_16_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_16_I_Q, B2LINST_16_I_Q_T, B2LINST_16_I_Q_C, B2LINST_16_I_Q_AR); ------( B2LINST_17_I_Q )----------------------------------------------------- B2LINST_17_I_Q_T <= ((not B2LINST_17_I_Q)) after tpd1; B2LINST_17_I_Q_AP <= (GND) after tpd0; B2LINST_17_I_Q_AR <= not (B2LINST_16_I_Q and B2LINST_17_I_Q) after tpd1; B2LINST_17_I_Q_C <= (ENCTMGP) after tclk; B2LINST_17_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_17_I_Q, B2LINST_17_I_Q_T, B2LINST_17_I_Q_C, B2LINST_17_I_Q_AR); ------( B2LINST_7_I_Q )------------------------------------------------------ B2LINST_7_I_Q_T <= ((B2LINST_9_I_Q and B2LINST_8_I_Q)) after tpd1; B2LINST_7_I_Q_AP <= (GND) after tpd0; B2LINST_7_I_Q_AR <= (GND) after tpd0; B2LINST_7_I_Q_C <= (CLK106MHZ) after tclk; B2LINST_7_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_7_I_Q, B2LINST_7_I_Q_T, B2LINST_7_I_Q_C, B2LINST_7_I_Q_AR); ------( B2LINST_8_I_Q )------------------------------------------------------ B2LINST_8_I_Q_T <= not((not ENCTMGP and not B2LINST_8_I_Q and not B2LINST_7_I_Q) or (not B2LINST_9_I_Q)) after tpd1; B2LINST_8_I_Q_AP <= (GND) after tpd0; B2LINST_8_I_Q_AR <= (GND) after tpd0; B2LINST_8_I_Q_C <= (CLK106MHZ) after tclk; B2LINST_8_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_8_I_Q, B2LINST_8_I_Q_T, B2LINST_8_I_Q_C, B2LINST_8_I_Q_AR); ------( B2LINST_9_I_Q )------------------------------------------------------ B2LINST_9_I_Q_T <= not((not B2LINST_9_I_Q and not ENCTMGP and not B2LINST_8_I_Q and not B2LINST_7_I_Q)) after tpd1; B2LINST_9_I_Q_AP <= (GND) after tpd0; B2LINST_9_I_Q_AR <= (GND) after tpd0; B2LINST_9_I_Q_C <= (CLK106MHZ) after tclk; B2LINST_9_I_Q_ff: pxa_tff_ar_p0 port map(B2LINST_9_I_Q, B2LINST_9_I_Q_T, B2LINST_9_I_Q_C, B2LINST_9_I_Q_AR); end structure;