---------------------------------------------------------------------------
-- VHDL Timing Model
-- Converted from JEDEC file
-- Created by Philips Semiconductors
-- Program: xplafit version 3.21
-- Design Name = timdec2
-- Device Name = pz5064cs7bc
-- Jul 11 14:31:38 2001
---------------------------------------------------------------------------
package pxa_pkg is
    constant tpd0 : time := 0 ps;
    constant tpd1 : time := 6000 ps;
    constant tpd2 : time := 7500 ps;
    constant tclk : time := 1500 ps;
    constant tap2q: time := 3000 ps;
    constant tar2q: time := 3000 ps;
    constant trd  : time := 2000 ps;
    constant tbuf : time := 1500 ps;
    constant toe  : time := 1500 ps;
end pxa_pkg;
---------------------------------------------------------------------------
-- Components Defined Here
---------------------------------------------------------------------------
-- Output Buffer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_bufif1 is
	Port (O: out std_logic; I, OE : in std_logic);
end pxa_bufif1;
architecture behavioral of pxa_bufif1 is
begin
	O <= I after tbuf when OE='1' else 'Z' after toe;
end behavioral;

-- D Flip Flop with Asynchronous Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_dff_ar_p0 is
	port (Q : Out std_logic; D, CLK, AR : In std_logic);
end pxa_dff_ar_p0;
architecture behavioral of pxa_dff_ar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
	 elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- D flip flop with Asynchronous Preset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_dff_ap_p0 is
	port (Q : Out std_logic; D, CLK, AP : In std_logic);
end pxa_dff_ap_p0;
architecture behavioral of pxa_dff_ap_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP)
  begin
	 if AP = '1' then
	   Q_local <= '1' after tap2q;
	 elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_tff_ar_p0 is
	port (Q : out std_logic; T, CLK, AR : in std_logic);
end pxa_tff_ar_p0;
architecture behavioral of pxa_tff_ar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Preset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;

entity pxa_tff_ap_p0 is
	port (Q : out std_logic; T, CLK, AP : in std_logic);
end pxa_tff_ap_p0;
architecture behavioral of pxa_tff_ap_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP)
  begin
    if AP = '1' then
      Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

---------------------------------------------------------------------------
-- Main VHDL Model 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity timdec2 is
    port(VXO53MHz: in std_logic;
         Clk106MHz: in std_logic;
         EncTmgn: in std_logic;
         RF_Inp: in std_logic;
         Up: inout std_logic;
         Down: inout std_logic;
         VXO_Div4: out std_logic;
         FC: out std_logic;
         SGap: out std_logic;
         Gap: out std_logic;
         Clk53MHzO2: out std_logic;
         Clk53MHzOut: out std_logic;
         RF_Dtct: out std_logic);
end timdec2;

architecture structure of timdec2 is

-- Signal Declaration -------------------------------
signal Up_COM, Up_OE, Down_COM, Down_OE, VXO_Div4_T, VXO_Div4_OE, VXO_Div4_Q,
       VXO_Div4_C, VXO_Div4_AP, VXO_Div4_AR, FC_T, FC_OE, FC_Q, FC_C, FC_AP,
       FC_AR, SGap_T, SGap_OE, SGap_Q, SGap_C, SGap_AP, SGap_AR, Gap_T,
       Gap_OE, Gap_Q, Gap_C, Gap_AP, Gap_AR, Clk53MHzO2_D, Clk53MHzO2_OE,
       Clk53MHzO2_Q, Clk53MHzO2_C, Clk53MHzO2_AP, Clk53MHzO2_AR,
       Clk53MHzOut_D, Clk53MHzOut_OE, Clk53MHzOut_Q, Clk53MHzOut_C,
       Clk53MHzOut_AP, Clk53MHzOut_AR, RF_Dtct_D, RF_Dtct_OE, RF_Dtct_Q,
       RF_Dtct_C, RF_Dtct_AP, RF_Dtct_AR, Enc_Div2, Enc_Div2_T, Enc_Div2_C,
       Enc_Div2_AP, Enc_Div2_AR, D0, D0_D, D0_C, D0_AP, D0_AR, D1, D1_D,
       D1_C, D1_AP, D1_AR, S0, S0_T, S0_C, S0_AP, S0_AR, S1, S1_T, S1_C,
       S1_AP, S1_AR, S2, S2_T, S2_C, S2_AP, S2_AR, IDtct, IDtct_D, IDtct_C,
       IDtct_AP, IDtct_AR, VXOCnt0, VXOCnt0_T, VXOCnt0_C, VXOCnt0_AP,
       VXOCnt0_AR, VXOCnt1, VXOCnt1_T, VXOCnt1_C, VXOCnt1_AP, VXOCnt1_AR,
       VXOCnt2, VXOCnt2_T, VXOCnt2_C, VXOCnt2_AP, VXOCnt2_AR, enctmg_reg,
       enctmg_reg_D, enctmg_reg_C, enctmg_reg_AP, enctmg_reg_AR, vxo53_reg,
       vxo53_reg_D, vxo53_reg_C, vxo53_reg_AP, vxo53_reg_AR : std_logic;
signal VCC : std_logic := '1';
signal GND : std_logic := '0';

component pxa_bufif1
	Port (O: out std_logic; I, OE : in std_logic);
end component;
component pxa_dff_ap_p0
	port (Q : out std_logic; D, CLK, AP : in std_logic);
end component;
component pxa_dff_ar_p0
	port (Q : out std_logic; D, CLK, AR : in std_logic);
end component;
component pxa_tff_ap_p0
	port (Q : out std_logic; T, CLK, AP : in std_logic);
end component;
component pxa_tff_ar_p0
	port (Q : out std_logic; T, CLK, AR : in std_logic);
end component;
begin
-- Equations:

------( Up )-----------------------------------------------------------------
Up_COM <= (VCC) after tpd0;
Up_OE <= (enctmg_reg and not vxo53_reg) after tpd1;
Up_buf: pxa_bufif1 port map (Up, Up_COM, Up_OE);
------( Down )---------------------------------------------------------------
Down_COM <= (GND) after tpd0;
Down_OE <= (not enctmg_reg and vxo53_reg) after tpd1;
Down_buf: pxa_bufif1 port map (Down, Down_COM, Down_OE);
------( VXO_Div4 )-----------------------------------------------------------
VXO_Div4_T <= ((VXOCnt0)) after tpd1;
VXO_Div4_OE <= (VCC) after tpd0;
VXO_Div4_buf: pxa_bufif1 port map (VXO_Div4, VXO_Div4_Q, VXO_Div4_OE);
VXO_Div4_AP <= (GND) after tpd0;
VXO_Div4_AR <= (GND) after tpd0;
VXO_Div4_C <= (VXO53MHz) after tclk;
VXO_Div4_ff: pxa_tff_ar_p0 port map(VXO_Div4_Q, VXO_Div4_T, VXO_Div4_C, VXO_Div4_AR);
------( FC )-----------------------------------------------------------------
FC_T <= ((not S1 and FC_Q and not D0 and S2 and EncTmgn and D1 and not S0)
	or (not S1 and FC_Q and D0 and S2 and not EncTmgn and not D1 and not S0)
	or (not S1 and not FC_Q and S2 and EncTmgn and not D1 and not S0)) after tpd1;
FC_OE <= (VCC) after tpd0;
FC_buf: pxa_bufif1 port map (FC, FC_Q, FC_OE);
FC_AP <= (GND) after tpd0;
FC_AR <= (GND) after tpd0;
FC_C <= (Clk106MHz) after tclk;
FC_ff: pxa_tff_ar_p0 port map(FC_Q, FC_T, FC_C, FC_AR);
------( SGap )---------------------------------------------------------------
SGap_T <= ((not D0 and S2 and EncTmgn and SGap_Q and D1 and not S0 and not S1)
	or (D0 and S2 and EncTmgn and not SGap_Q and not D1 and not S0 and not S1)
	or (not D0 and S2 and not EncTmgn and not SGap_Q and not D1 and not S0 and not S1)) after tpd1;
SGap_OE <= (VCC) after tpd0;
SGap_buf: pxa_bufif1 port map (SGap, SGap_Q, SGap_OE);
SGap_AP <= (GND) after tpd0;
SGap_AR <= (GND) after tpd0;
SGap_C <= (Clk106MHz) after tclk;
SGap_ff: pxa_tff_ar_p0 port map(SGap_Q, SGap_T, SGap_C, SGap_AR);
------( Gap )----------------------------------------------------------------
Gap_T <= ((not S1 and not D0 and S2 and EncTmgn and D1 and not S0 and Gap_Q)
	or (not S1 and not D0 and S2 and not EncTmgn and D1 and not S0 and not Gap_Q)) after tpd1;
Gap_OE <= (VCC) after tpd0;
Gap_buf: pxa_bufif1 port map (Gap, Gap_Q, Gap_OE);
Gap_AP <= (GND) after tpd0;
Gap_AR <= (GND) after tpd0;
Gap_C <= (Clk106MHz) after tclk;
Gap_ff: pxa_tff_ar_p0 port map(Gap_Q, Gap_T, Gap_C, Gap_AR);
------( Clk53MHzO2 )---------------------------------------------------------
Clk53MHzO2_D <= ((S0)) after tpd1;
Clk53MHzO2_OE <= (VCC) after tpd0;
Clk53MHzO2_buf: pxa_bufif1 port map (Clk53MHzO2, Clk53MHzO2_Q, Clk53MHzO2_OE);
Clk53MHzO2_AP <= (GND) after tpd0;
Clk53MHzO2_AR <= (GND) after tpd0;
Clk53MHzO2_C <= (Clk106MHz) after tclk;
Clk53MHzO2_ff: pxa_dff_ar_p0 port map (Clk53MHzO2_Q, Clk53MHzO2_D, Clk53MHzO2_C, Clk53MHzO2_AR);
------( Clk53MHzOut )--------------------------------------------------------
Clk53MHzOut_D <= ((S0)) after tpd1;
Clk53MHzOut_OE <= (VCC) after tpd0;
Clk53MHzOut_buf: pxa_bufif1 port map (Clk53MHzOut, Clk53MHzOut_Q, Clk53MHzOut_OE);
Clk53MHzOut_AP <= (GND) after tpd0;
Clk53MHzOut_AR <= (GND) after tpd0;
Clk53MHzOut_C <= (Clk106MHz) after tclk;
Clk53MHzOut_ff: pxa_dff_ar_p0 port map (Clk53MHzOut_Q, Clk53MHzOut_D, Clk53MHzOut_C, Clk53MHzOut_AR);
------( RF_Dtct )------------------------------------------------------------
RF_Dtct_D <= (VCC) after tpd0;
RF_Dtct_OE <= (VCC) after tpd0;
RF_Dtct_buf: pxa_bufif1 port map (RF_Dtct, RF_Dtct_Q, RF_Dtct_OE);
RF_Dtct_AP <= (GND) after tpd0;
RF_Dtct_AR <= (VXOCnt1 and VXO_Div4_Q and VXOCnt0 and not IDtct and not VXOCnt2) after tpd1;
RF_Dtct_C <= (RF_Inp) after tclk;
RF_Dtct_ff: pxa_dff_ar_p0 port map (RF_Dtct_Q, RF_Dtct_D, RF_Dtct_C, RF_Dtct_AR);
------( Enc_Div2 )-----------------------------------------------------------
Enc_Div2_T <= (VCC) after tpd0;
Enc_Div2_AP <= (GND) after tpd0;
Enc_Div2_AR <= (GND) after tpd0;
Enc_Div2_C <= (EncTmgn) after tpd1;
Enc_Div2_ff: pxa_tff_ar_p0  port map(Enc_Div2, Enc_Div2_T, Enc_Div2_C, Enc_Div2_AR);
------( D0 )-----------------------------------------------------------------
D0_D <= ((EncTmgn)) after tpd1;
D0_AP <= (GND) after tpd0;
D0_AR <= (GND) after tpd0;
D0_C <= (Clk106MHz) after tclk;
D0_ff: pxa_dff_ar_p0 port map(D0, D0_D, D0_C, D0_AR);
------( D1 )-----------------------------------------------------------------
D1_D <= ((D0)) after tpd1;
D1_AP <= (GND) after tpd0;
D1_AR <= (GND) after tpd0;
D1_C <= (Clk106MHz) after tclk;
D1_ff: pxa_dff_ar_p0 port map(D1, D1_D, D1_C, D1_AR);
------( S0 )-----------------------------------------------------------------
S0_T <= not((not S2 and not EncTmgn and not S0 and not S1)) after tpd1;
S0_AP <= (GND) after tpd0;
S0_AR <= (GND) after tpd0;
S0_C <= (Clk106MHz) after tclk;
S0_ff: pxa_tff_ar_p0  port map(S0, S0_T, S0_C, S0_AR);
------( S1 )-----------------------------------------------------------------
S1_T <= not((not S0)
	or (not S2 and not EncTmgn and not S1)) after tpd1;
S1_AP <= (GND) after tpd0;
S1_AR <= (GND) after tpd0;
S1_C <= (Clk106MHz) after tclk;
S1_ff: pxa_tff_ar_p0  port map(S1, S1_T, S1_C, S1_AR);
------( S2 )-----------------------------------------------------------------
S2_T <= ((S0 and S1)) after tpd1;
S2_AP <= (GND) after tpd0;
S2_AR <= (GND) after tpd0;
S2_C <= (Clk106MHz) after tclk;
S2_ff: pxa_tff_ar_p0  port map(S2, S2_T, S2_C, S2_AR);
------( IDtct )--------------------------------------------------------------
IDtct_D <= (VCC) after tpd0;
IDtct_AP <= (GND) after tpd0;
IDtct_AR <= (VXOCnt1 and VXO_Div4_Q and VXOCnt0 and VXOCnt2) after tpd1;
IDtct_C <= (RF_Inp) after tclk;
IDtct_ff: pxa_dff_ar_p0 port map(IDtct, IDtct_D, IDtct_C, IDtct_AR);
------( VXOCnt0 )------------------------------------------------------------
VXOCnt0_T <= (VCC) after tpd0;
VXOCnt0_AP <= (GND) after tpd0;
VXOCnt0_AR <= (GND) after tpd0;
VXOCnt0_C <= (VXO53MHz) after tclk;
VXOCnt0_ff: pxa_tff_ar_p0  port map(VXOCnt0, VXOCnt0_T, VXOCnt0_C, VXOCnt0_AR);
------( VXOCnt1 )------------------------------------------------------------
VXOCnt1_T <= ((VXO_Div4_Q and VXOCnt0)) after tpd1;
VXOCnt1_AP <= (GND) after tpd0;
VXOCnt1_AR <= (GND) after tpd0;
VXOCnt1_C <= (VXO53MHz) after tclk;
VXOCnt1_ff: pxa_tff_ar_p0  port map(VXOCnt1, VXOCnt1_T, VXOCnt1_C, VXOCnt1_AR);
------( VXOCnt2 )------------------------------------------------------------
VXOCnt2_T <= ((VXOCnt1 and VXO_Div4_Q and VXOCnt0)) after tpd1;
VXOCnt2_AP <= (GND) after tpd0;
VXOCnt2_AR <= (GND) after tpd0;
VXOCnt2_C <= (VXO53MHz) after tclk;
VXOCnt2_ff: pxa_tff_ar_p0  port map(VXOCnt2, VXOCnt2_T, VXOCnt2_C, VXOCnt2_AR);
------( enctmg_reg )---------------------------------------------------------
enctmg_reg_D <= (VCC) after tpd0;
enctmg_reg_AP <= (GND) after tpd0;
enctmg_reg_AR <= (enctmg_reg and vxo53_reg) after tpd1;
enctmg_reg_C <= (EncTmgn) after tpd1;
enctmg_reg_ff: pxa_dff_ar_p0 port map(enctmg_reg, enctmg_reg_D, enctmg_reg_C, enctmg_reg_AR);
------( vxo53_reg )----------------------------------------------------------
vxo53_reg_D <= (VCC) after tpd0;
vxo53_reg_AP <= (GND) after tpd0;
vxo53_reg_AR <= (enctmg_reg and vxo53_reg) after tpd1;
vxo53_reg_C <= (VXO53MHz) after tclk;
vxo53_reg_ff: pxa_dff_ar_p0 port map(vxo53_reg, vxo53_reg_D, vxo53_reg_C, vxo53_reg_AR);
end structure;