---------------------------------------------------------------------------
-- Static Timing Analysis
-- Converted from JEDEC file
-- Created by Philips Semiconductors
-- Program: xplafit version 3.21
-- Design Name = timdec2
-- Device Name = pz5064cs7bc
-- Jul 11 14:31:38 2001
---------------------------------------------------------------------------

--------------------------------------
|  D e l a y    D e f i n i t i o n  |
--------------------------------------
Internal : Register feedback to output delay
Tpd      : Input to output delay
Tsu      : Clock setup time
Tco      : Clock to output delay
Tclk     : Additional delay for clocks using logic array
Toe      : Delay for output enable or disable
Trr      : Delay for async register reset
Trp      : Delay for async register preset

-----------------------------------------------------------------------------
|  D a t a   B o o k   V a l u e s   f o r   S e l e c t e d   D e v i c e  |
-----------------------------------------------------------------------------
tpd_pal  : Input to output delay through PAL        =   7.5 ns
tpd_pla  : Input to output delay through PLA        =   9.0 ns
tpdf_pal : Input to feedback node delay through PAL =   6.0 ns
tpdf_pla : Input to feedback node delay through PLA =   7.5 ns
tsu_pal  : PAL setup time (Global clock)            =   4.5 ns
tsu_pla  : PLA setup time (Global clock)            =   6.0 ns
tbuff    : Output buffer delay                      =   1.5 ns
tcf      : Clock to feedback delay                  =   3.5 ns
tco      : Clock to out delay                       =   5.0 ns
tea, ter : Output enable/disable delay              =   7.5 ns
trr      : Input to register reset                  =   9.0 ns
trp      : Input to register preset                 =   9.0 ns

--------------------------------------------------------------------------
|  T s u    D e l a y    S u m m a r y    f o r    E a c h    C l o c k  |
--------------------------------------------------------------------------

--------( Clk106MHz )------------------------------------------------------
Max      Max        Signal
Tsu(nS)  Freq(MHz)
8.0      125.00     Clk53MHzO2, Clk53MHzOut, D1, FC, Gap, S0, S1, S2, SGap
4.5      222.22     D0
--------( VXO53MHz )-------------------------------------------------------
Max      Max        Signal
Tsu(nS)  Freq(MHz)
8.0      125.00     VXOCnt1, VXOCnt2, VXO_Div4
---------------------------------------------------------------------------

--------------------------------------------------
|  D e l a y    f o r    E a c h    S i g n a l  |
--------------------------------------------------
--------( Clk53MHzO2 )-----------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         S0.q
Toe
NA (VCC)

Trr
NA (GND)

Tco(nS)  Equation/Set by
5.0      tco 
--------( Clk53MHzOut )----------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         S0.q
Toe
NA (VCC)

Trr
NA (GND)

Tco(nS)  Equation/Set by
5.0      tco 
--------( D0 )-------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by pin(s)
4.5      tsu_pal 
         EncTmgn
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( D1 )-------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         D0.q
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( Down )-----------------------------------------------------------
Tpd
NA (GND)

Tsu
NA (not a register)

Toe(nS)  Equation/Set by node(s)
11.0     tcf + tea 
         enctmg_reg.q, vxo53_reg.q

Trr/Trp
NA (not a register)

Tco
NA (not a register)
--------( Enc_Div2 )-------------------------------------------------------
Tclk(nS) Equation/Set by
6.0      1 tpdf_pal 
         EncTmgn

Tclk_min = Tclk_max = 6.0 ns

Tpd
NA (not combinatorial)

Tsu
NA (VCC)

Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( FC )-------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         D0.q, D1.q, FC.q, S0.q, S1.q, S2.q

Tsu(nS)  Equation/Set by pin(s)
4.5      tsu_pal 
         EncTmgn
Toe
NA (VCC)

Trr
NA (GND)

Tco(nS)  Equation/Set by
5.0      tco 
--------( Gap )------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         D0.q, D1.q, Gap.q, S0.q, S1.q, S2.q

Tsu(nS)  Equation/Set by pin(s)
4.5      tsu_pal 
         EncTmgn
Toe
NA (VCC)

Trr
NA (GND)

Tco(nS)  Equation/Set by
5.0      tco 
--------( IDtct )----------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu
NA (VCC)

Toe
NA (not a tri-stateable output)

Trr(nS)  Equation/Set by node(s)
12.5     tcf + trr 
         VXOCnt0.q, VXOCnt1.q, VXOCnt2.q, VXO_Div4.q

Tco
NA (does not drive an output pin)
--------( RF_Dtct )--------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu
NA (VCC)

Toe
NA (VCC)

Trr(nS)  Equation/Set by node(s)
12.5     tcf + trr 
         IDtct.q, VXOCnt0.q, VXOCnt1.q, VXOCnt2.q, VXO_Div4.q

Tco(nS)  Equation/Set by
5.0      tco 
--------( S0 )-------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         S0.q, S1.q, S2.q

Tsu(nS)  Equation/Set by pin(s)
4.5      tsu_pal 
         EncTmgn
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( S1 )-------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         S0.q, S1.q, S2.q

Tsu(nS)  Equation/Set by pin(s)
4.5      tsu_pal 
         EncTmgn
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( S2 )-------------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         S0.q, S1.q
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( SGap )-----------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         D0.q, D1.q, S0.q, S1.q, S2.q, SGap.q

Tsu(nS)  Equation/Set by pin(s)
4.5      tsu_pal 
         EncTmgn
Toe
NA (VCC)

Trr
NA (GND)

Tco(nS)  Equation/Set by
5.0      tco 
--------( Up )-------------------------------------------------------------
Tpd
NA (VCC)

Tsu
NA (not a register)

Toe(nS)  Equation/Set by node(s)
11.0     tcf + tea 
         enctmg_reg.q, vxo53_reg.q

Trr/Trp
NA (not a register)

Tco
NA (not a register)
--------( VXOCnt0 )--------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu
NA (VCC)

Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( VXOCnt1 )--------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         VXOCnt0.q, VXO_Div4.q
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( VXOCnt2 )--------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         VXOCnt0.q, VXOCnt1.q, VXO_Div4.q
Toe
NA (not a tri-stateable output)

Trr
NA (GND)

Tco
NA (does not drive an output pin)
--------( VXO_Div4 )-------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu(nS)  Equation/Set by node(s)
8.0      tcf + tsu_pal 
         VXOCnt0.q
Toe
NA (VCC)

Trr
NA (GND)

Tco(nS)  Equation/Set by
5.0      tco 
--------( enctmg_reg )-----------------------------------------------------
Tclk(nS) Equation/Set by
6.0      1 tpdf_pal 
         EncTmgn

Tclk_min = Tclk_max = 6.0 ns

Tpd
NA (not combinatorial)

Tsu
NA (VCC)

Toe
NA (not a tri-stateable output)

Trr(nS)  Equation/Set by node(s)
12.5     tcf + trr 
         enctmg_reg.q, vxo53_reg.q

Tco
NA (does not drive an output pin)
--------( vxo53_reg )------------------------------------------------------
Tpd
NA (not combinatorial)

Tsu
NA (VCC)

Toe
NA (not a tri-stateable output)

Trr(nS)  Equation/Set by node(s)
12.5     tcf + trr 
         enctmg_reg.q, vxo53_reg.q

Tco
NA (does not drive an output pin)
---------------------------------------------------------------------------

---------------
| F a n i n s |
---------------
Clk53MHzO2 : S0
Clk53MHzOut: S0
D0         : EncTmgn
D1         : D0
Down       : 
Enc_Div2   : 
FC         : S1, FC, D0, S2, EncTmgn, D1, S0
Gap        : S1, D0, S2, EncTmgn, D1, S0, Gap
IDtct      : 
RF_Dtct    : 
S0         : S2, EncTmgn, S0, S1
S1         : S2, EncTmgn, S0, S1
S2         : S0, S1
SGap       : D0, S2, EncTmgn, SGap, D1, S0, S1
Up         : 
VXOCnt0    : 
VXOCnt1    : VXO_Div4, VXOCnt0
VXOCnt2    : VXOCnt1, VXO_Div4, VXOCnt0
VXO_Div4   : VXOCnt0
enctmg_reg : 
vxo53_reg  : 

-----------------
| F a n o u t s |
-----------------
Clk53MHzO2 : 
Clk53MHzOut: 
D0         : D1, SGap, Gap, FC
D1         : SGap, Gap, FC
Down       : 
Enc_Div2   : 
FC         : FC
Gap        : Gap
IDtct      : 
RF_Dtct    : 
S0         : S2, S0, S1, SGap, Gap, FC, Clk53MHzOut, Clk53MHzO2
S1         : S2, S0, S1, SGap, Gap, FC
S2         : S0, S1, SGap, Gap, FC
SGap       : SGap
Up         : 
VXOCnt0    : VXOCnt2, VXOCnt1, VXO_Div4
VXOCnt1    : VXOCnt2
VXOCnt2    : 
VXO_Div4   : VXOCnt2, VXOCnt1
enctmg_reg : 
vxo53_reg  :