------------------------------------------ Preassigned signals before partition algorithm 0, iteration0, logic block A ------------------------------------------ EncTmgn, input pin 43 VXO_Div4, pin 44 Total preassigned signals=1 fanin used=1 pla pterm used=0 reset/preset used=0 output enable used=0 ------------------------------------------ Assigned signals after partition ------------------------------------------ EncTmgn, input pin 43 VXO_Div4, pin 44 VXOCnt1, node 0 VXOCnt2, node 0 IDtct, node 0 VXOCnt0, node 0 Enc_Div2, node 0 D0, node 0 enctmg_reg, node 0 vxo53_reg, node 0 S0, node 0 S1, node 0 S2, node 0 D1, node 0 Total assigned signals=13 fanin used=11 pla pterm used=0 reset/preset used=2 output enable used=1 unassigned signals left=0 pclk used=1 ------------------------------------------ Preassigned signals before partition algorithm 0, iteration0, logic block B ------------------------------------------ Clk106MHz, input pin 15 Total preassigned signals=0 fanin used=0 pla pterm used=0 reset/preset used=0 output enable used=0 ------------------------------------------ Assigned signals after partition ------------------------------------------ Clk106MHz, input pin 15 Total assigned signals=0 fanin used=0 pla pterm used=0 reset/preset used=0 output enable used=0 unassigned signals left=0 pclk used=1 ------------------------------------------ Preassigned signals before partition algorithm 0, iteration0, logic block C ------------------------------------------ VXO53MHz, input pin 18 Up, pin 23 Down, pin 19 SGap, pin 21 RF_Dtct, pin 22 Total preassigned signals=4 fanin used=14 pla pterm used=0 reset/preset used=1 output enable used=2 ------------------------------------------ Assigned signals after partition ------------------------------------------ VXO53MHz, input pin 18 Up, pin 23 Down, pin 19 SGap, pin 21 RF_Dtct, pin 22 Total assigned signals=4 fanin used=14 pla pterm used=0 reset/preset used=1 output enable used=2 unassigned signals left=0 pclk used=0 ------------------------------------------ Preassigned signals before partition algorithm 0, iteration0, logic block D ------------------------------------------ FC, pin 33 Gap, pin 28 Clk53MHzO2, pin 35 Clk53MHzOut, pin 34 Total preassigned signals=4 fanin used=8 pla pterm used=0 reset/preset used=0 output enable used=0 ------------------------------------------ Assigned signals after partition ------------------------------------------ FC, pin 33 Gap, pin 28 Clk53MHzO2, pin 35 Clk53MHzOut, pin 34 Total assigned signals=4 fanin used=8 pla pterm used=0 reset/preset used=0 output enable used=0 unassigned signals left=0 pclk used=0 Place and Route passed on algorithm 0, iteration 0