" XPLAOPT Version 3.21
" Created on Wed Jul 11 14:31:32 2001
" 21 Mcells, 0 PLApts, 26 PALpts, 1 Levels
" XPLAOPT -run s -i timdec2.phd -it phd -o timdec2.pla -ot tt2 -dev pz5064cs7bc 
"         -log timdec2.dox -reg -fi 36 -th 21 -effort f -net -rsp xplaopt.rsp 
MODULE tmgdec2

	Up  pin 23 ;  " 1 pt.
 	VXO53MHz  pin 18 ; 
 	Clk106MHz  pin 15 ; 
 	EncTmgn  pin 43 ; 
 	Down  pin 19 ;  " 0 pt.
 	RF_Inp  pin 37 ; 
 	VXO_Div4  pin 44 ;  " 1 pt.
 	FC  pin 33 ;  " 3 pt.
 	SGap  pin 21 ;  " 3 pt.
 	Gap  pin 28 ;  " 2 pt.
 	Clk53MHzO2  pin 35 ;  " 1 pt.
 	Clk53MHzOut  pin 34 ;  " 1 pt.
 	RF_Dtct  pin 22 ;  " 1 pt.
 

	Enc_Div2  node ;  " 1 pt.
 	D0  node ;  " 1 pt.
 	D1  node ;  " 1 pt.
 	S0  node ;  " 1 pt.
 	S1  node ;  " 2 pt.
 	S2  node ;  " 1 pt.
 	IDtct  node ;  " 1 pt.
 	VXOCnt0  node ;  " 1 pt.
 	VXOCnt1  node ;  " 1 pt.
 	VXOCnt2  node ;  " 1 pt.
 	enctmg_reg  node ;  " 1 pt.
 	vxo53_reg  node ;  " 1 pt.
 

EQUATIONS 

 Clk53MHzO2.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 Clk53MHzO2.D = S0.Q;		"--- [PT=1, FI=1, LVL=1] ---
 Clk53MHzOut.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 Clk53MHzOut.D = S0.Q;		"--- [PT=1, FI=1, LVL=1] ---
 D0.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 D0.D = EncTmgn;		"--- [PT=1, FI=1, LVL=1] ---
 D1.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 D1.D = D0.Q;		"--- [PT=1, FI=1, LVL=1] ---
 Down = 0;
 Down.OE = vxo53_reg.Q & !enctmg_reg.Q;		"--- [PT=1, FI=2, LVL=1] ---
 Enc_Div2.CLK = EncTmgn;		"--- [PT=1, FI=1, LVL=1] ---
 Enc_Div2.T = 1;
 FC.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 FC.T = EncTmgn & !S0.Q & !S1.Q & S2.Q & !D1.Q & !FC.Q
      # EncTmgn & !S0.Q & !S1.Q & S2.Q & !D0.Q & D1.Q & FC.Q
      # !EncTmgn & !S0.Q & !S1.Q & S2.Q & D0.Q & !D1.Q & FC.Q
    ;		"--- [PT=3, FI=7, LVL=1] ---
 Gap.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 Gap.T = !EncTmgn & !S0.Q & !S1.Q & S2.Q & !D0.Q & D1.Q & !Gap.Q
      # EncTmgn & !S0.Q & !S1.Q & S2.Q & !D0.Q & D1.Q & Gap.Q
    ;		"--- [PT=2, FI=7, LVL=1] ---
 IDtct.AR = VXOCnt0.Q & VXO_Div4.Q & VXOCnt1.Q & VXOCnt2.Q
    ;		"--- [PT=1, FI=4, LVL=1] ---
 IDtct.CLK = RF_Inp;		"--- [PT=1, FI=1, LVL=1] ---
 IDtct.D = 1;
 RF_Dtct.AR = VXOCnt0.Q & VXO_Div4.Q & VXOCnt1.Q & !VXOCnt2.Q & !IDtct.Q
    ;		"--- [PT=1, FI=5, LVL=1] ---
 RF_Dtct.CLK = RF_Inp;		"--- [PT=1, FI=1, LVL=1] ---
 RF_Dtct.D = 1;
 S0.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
! S0.T = !EncTmgn & !S0.Q & !S1.Q & !S2.Q;		"--- [PT=1, FI=4, LVL=1] ---
 S1.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
! S1.T = !S0.Q
      # !EncTmgn & !S1.Q & !S2.Q;		"--- [PT=2, FI=4, LVL=1] ---
 S2.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 S2.T = S0.Q & S1.Q;		"--- [PT=1, FI=2, LVL=1] ---
 SGap.CLK = Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 SGap.T = !EncTmgn & !S0.Q & !S1.Q & S2.Q & !D0.Q & !SGap.Q & !D1.Q
      # EncTmgn & !S0.Q & !S1.Q & S2.Q & D0.Q & !SGap.Q & !D1.Q
      # EncTmgn & !S0.Q & !S1.Q & S2.Q & !D0.Q & SGap.Q & D1.Q
    ;		"--- [PT=3, FI=7, LVL=1] ---
 Up = 1;
 Up.OE = !vxo53_reg.Q & enctmg_reg.Q;		"--- [PT=1, FI=2, LVL=1] ---
 VXOCnt0.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXOCnt0.T = 1;
 VXOCnt1.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXOCnt1.T = VXOCnt0.Q & VXO_Div4.Q;		"--- [PT=1, FI=2, LVL=1] ---
 VXOCnt2.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXOCnt2.T = VXOCnt0.Q & VXOCnt1.Q & VXO_Div4.Q
    ;		"--- [PT=1, FI=3, LVL=1] ---
 VXO_Div4.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXO_Div4.T = VXOCnt0.Q;		"--- [PT=1, FI=1, LVL=1] ---
 enctmg_reg.AR = vxo53_reg.Q & enctmg_reg.Q;		"--- [PT=1, FI=2, LVL=1] ---
 enctmg_reg.CLK = EncTmgn;		"--- [PT=1, FI=1, LVL=1] ---
 enctmg_reg.D = 1;
 vxo53_reg.AR = vxo53_reg.Q & enctmg_reg.Q;		"--- [PT=1, FI=2, LVL=1] ---
 vxo53_reg.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 vxo53_reg.D = 1;
END