* XPLAOPT Version 3.21
* Created on Wed Jul 11 14:31:32 2001
* By Philips Semiconductors
*
 NETSTART
*
*----( Clk53MHzO2 ) -------------------------------
Clk53MHzO2_D AND I(S0_BUF) O(Clk53MHzO2_D)
Clk53MHzO2_Q DFFSRCE I(Clk53MHzO2_D, Clk53MHzO2_CLK, Clk53MHzO2_AP, Clk53MHzO2_AR, Clk53MHzO2_CE) O(Clk53MHzO2_Q)
Clk53MHzO2_AP AND I(GND) O(Clk53MHzO2_AP)
Clk53MHzO2_AR AND I(GND) O(Clk53MHzO2_AR)
Clk53MHzO2_CLK AND I(Clk106MHz_BUF) O(Clk53MHzO2_CLK)
Clk53MHzO2_CE AND I(VCC) O(Clk53MHzO2_CE)
Clk53MHzO2 TRIBUF I(VCC, Clk53MHzO2_Q) O(Clk53MHzO2)
*----( Clk53MHzOut ) -------------------------------
Clk53MHzOut_D AND I(S0_BUF) O(Clk53MHzOut_D)
Clk53MHzOut_Q DFFSRCE I(Clk53MHzOut_D, Clk53MHzOut_CLK, Clk53MHzOut_AP, Clk53MHzOut_AR, Clk53MHzOut_CE) O(Clk53MHzOut_Q)
Clk53MHzOut_AP AND I(GND) O(Clk53MHzOut_AP)
Clk53MHzOut_AR AND I(GND) O(Clk53MHzOut_AR)
Clk53MHzOut_CLK AND I(Clk106MHz_BUF) O(Clk53MHzOut_CLK)
Clk53MHzOut_CE AND I(VCC) O(Clk53MHzOut_CE)
Clk53MHzOut TRIBUF I(VCC, Clk53MHzOut_Q) O(Clk53MHzOut)
*----( Down ) -------------------------------
Down_D AND I(GND) O(Down_D)
Down TRIBUF I(Down_OE, Down_D) O(Down)
Down_OE AND I(vxo53_reg_BUF, enctmg_reg_BAR) O(Down_OE)
*----( FC ) -------------------------------
FC_D OR I(FC_D_PT0, FC_D_PT1, FC_D_PT2) O(FC_D)
FC_D_PT0 AND I(EncTmgn_BAR, S0_BAR, S1_BAR, S2_BUF, D0_BUF, D1_BAR, FC_Q_BUF) O(FC_D_PT0)
FC_D_PT1 AND I(EncTmgn_BUF, S0_BAR, S1_BAR, S2_BUF, D0_BAR, D1_BUF, FC_Q_BUF) O(FC_D_PT1)
FC_D_PT2 AND I(EncTmgn_BUF, S0_BAR, S1_BAR, S2_BUF, D1_BAR, FC_Q_BAR) O(FC_D_PT2)
FC_Q TFFSR I(FC_D, FC_CLK, FC_AP, FC_AR) O(FC_Q)
FC_AP AND I(GND) O(FC_AP)
FC_AR AND I(GND) O(FC_AR)
FC_CLK AND I(Clk106MHz_BUF) O(FC_CLK)
FC TRIBUF I(VCC, FC_Q) O(FC)
*----( Gap ) -------------------------------
Gap_D OR I(Gap_D_PT0, Gap_D_PT1) O(Gap_D)
Gap_D_PT0 AND I(EncTmgn_BUF, S0_BAR, S1_BAR, S2_BUF, D0_BAR, D1_BUF, 
#               Gap_Q_BUF) O(Gap_D_PT0)
Gap_D_PT1 AND I(EncTmgn_BAR, S0_BAR, S1_BAR, S2_BUF, D0_BAR, D1_BUF, 
#               Gap_Q_BAR) O(Gap_D_PT1)
Gap_Q TFFSR I(Gap_D, Gap_CLK, Gap_AP, Gap_AR) O(Gap_Q)
Gap_AP AND I(GND) O(Gap_AP)
Gap_AR AND I(GND) O(Gap_AR)
Gap_CLK AND I(Clk106MHz_BUF) O(Gap_CLK)
Gap TRIBUF I(VCC, Gap_Q) O(Gap)
*----( RF_Dtct ) -------------------------------
RF_Dtct_D AND I(VCC) O(RF_Dtct_D)
RF_Dtct_Q DFFSRCE I(RF_Dtct_D, RF_Dtct_CLK, RF_Dtct_AP, RF_Dtct_AR, RF_Dtct_CE) O(RF_Dtct_Q)
RF_Dtct_AP AND I(GND) O(RF_Dtct_AP)
RF_Dtct_AR AND I(VXOCnt0_BUF, VXO_Div4_Q_BUF, VXOCnt1_BUF, VXOCnt2_BAR, 
#                IDtct_BAR) O(RF_Dtct_AR)
RF_Dtct_CLK AND I(RF_Inp_BUF) O(RF_Dtct_CLK)
RF_Dtct_CE AND I(VCC) O(RF_Dtct_CE)
RF_Dtct TRIBUF I(VCC, RF_Dtct_Q) O(RF_Dtct)
*----( SGap ) -------------------------------
SGap_D OR I(SGap_D_PT0, SGap_D_PT1, SGap_D_PT2) O(SGap_D)
SGap_D_PT0 AND I(EncTmgn_BUF, S0_BAR, S1_BAR, S2_BUF, D0_BAR, SGap_Q_BUF, 
#                D1_BUF) O(SGap_D_PT0)
SGap_D_PT1 AND I(EncTmgn_BUF, S0_BAR, S1_BAR, S2_BUF, D0_BUF, SGap_Q_BAR, 
#                D1_BAR) O(SGap_D_PT1)
SGap_D_PT2 AND I(EncTmgn_BAR, S0_BAR, S1_BAR, S2_BUF, D0_BAR, SGap_Q_BAR, 
#                D1_BAR) O(SGap_D_PT2)
SGap_Q TFFSR I(SGap_D, SGap_CLK, SGap_AP, SGap_AR) O(SGap_Q)
SGap_AP AND I(GND) O(SGap_AP)
SGap_AR AND I(GND) O(SGap_AR)
SGap_CLK AND I(Clk106MHz_BUF) O(SGap_CLK)
SGap TRIBUF I(VCC, SGap_Q) O(SGap)
*----( Up ) -------------------------------
Up_D AND I(VCC) O(Up_D)
Up TRIBUF I(Up_OE, Up_D) O(Up)
Up_OE AND I(vxo53_reg_BAR, enctmg_reg_BUF) O(Up_OE)
*----( VXO_Div4 ) -------------------------------
VXO_Div4_D AND I(VXOCnt0_BUF) O(VXO_Div4_D)
VXO_Div4_Q TFFSR I(VXO_Div4_D, VXO_Div4_CLK, VXO_Div4_AP, VXO_Div4_AR) O(VXO_Div4_Q)
VXO_Div4_AP AND I(GND) O(VXO_Div4_AP)
VXO_Div4_AR AND I(GND) O(VXO_Div4_AR)
VXO_Div4_CLK AND I(VXO53MHz_BUF) O(VXO_Div4_CLK)
VXO_Div4 TRIBUF I(VCC, VXO_Div4_Q) O(VXO_Div4)
*----( D0 ) -------------------------------
D0_D AND I(EncTmgn_BUF) O(D0_D)
D0 DFFSRCE I(D0_D, D0_CLK, D0_AP, D0_AR, D0_CE) O(D0)
D0_AP AND I(GND) O(D0_AP)
D0_AR AND I(GND) O(D0_AR)
D0_CLK AND I(Clk106MHz_BUF) O(D0_CLK)
D0_CE AND I(VCC) O(D0_CE)
*----( D1 ) -------------------------------
D1_D AND I(D0_BUF) O(D1_D)
D1 DFFSRCE I(D1_D, D1_CLK, D1_AP, D1_AR, D1_CE) O(D1)
D1_AP AND I(GND) O(D1_AP)
D1_AR AND I(GND) O(D1_AR)
D1_CLK AND I(Clk106MHz_BUF) O(D1_CLK)
D1_CE AND I(VCC) O(D1_CE)
*----( Enc_Div2 ) -------------------------------
Enc_Div2_D AND I(VCC) O(Enc_Div2_D)
Enc_Div2 TFFSR I(Enc_Div2_D, Enc_Div2_CLK, Enc_Div2_AP, Enc_Div2_AR) O(Enc_Div2)
Enc_Div2_AP AND I(GND) O(Enc_Div2_AP)
Enc_Div2_AR AND I(GND) O(Enc_Div2_AR)
Enc_Div2_CLK AND I(EncTmgn_BUF) O(Enc_Div2_CLK)
*----( IDtct ) -------------------------------
IDtct_D AND I(VCC) O(IDtct_D)
IDtct DFFSRCE I(IDtct_D, IDtct_CLK, IDtct_AP, IDtct_AR, IDtct_CE) O(IDtct)
IDtct_AP AND I(GND) O(IDtct_AP)
IDtct_AR AND I(VXOCnt0_BUF, VXO_Div4_Q_BUF, VXOCnt1_BUF, VXOCnt2_BUF) O(IDtct_AR)
IDtct_CLK AND I(RF_Inp_BUF) O(IDtct_CLK)
IDtct_CE AND I(VCC) O(IDtct_CE)
*----( S0 ) -------------------------------
S0_D NAND I(EncTmgn_BAR, S0_BAR, S1_BAR, S2_BAR) O(S0_D)
S0 TFFSR I(S0_D, S0_CLK, S0_AP, S0_AR) O(S0)
S0_AP AND I(GND) O(S0_AP)
S0_AR AND I(GND) O(S0_AR)
S0_CLK AND I(Clk106MHz_BUF) O(S0_CLK)
*----( S1 ) -------------------------------
S1_D NOR I(S1_D_PT0, S1_D_PT1) O(S1_D)
S1_D_PT0 AND I(EncTmgn_BAR, S1_BAR, S2_BAR) O(S1_D_PT0)
S1_D_PT1 AND I(S0_BAR) O(S1_D_PT1)
S1 TFFSR I(S1_D, S1_CLK, S1_AP, S1_AR) O(S1)
S1_AP AND I(GND) O(S1_AP)
S1_AR AND I(GND) O(S1_AR)
S1_CLK AND I(Clk106MHz_BUF) O(S1_CLK)
*----( S2 ) -------------------------------
S2_D AND I(S0_BUF, S1_BUF) O(S2_D)
S2 TFFSR I(S2_D, S2_CLK, S2_AP, S2_AR) O(S2)
S2_AP AND I(GND) O(S2_AP)
S2_AR AND I(GND) O(S2_AR)
S2_CLK AND I(Clk106MHz_BUF) O(S2_CLK)
*----( VXOCnt0 ) -------------------------------
VXOCnt0_D AND I(VCC) O(VXOCnt0_D)
VXOCnt0 TFFSR I(VXOCnt0_D, VXOCnt0_CLK, VXOCnt0_AP, VXOCnt0_AR) O(VXOCnt0)
VXOCnt0_AP AND I(GND) O(VXOCnt0_AP)
VXOCnt0_AR AND I(GND) O(VXOCnt0_AR)
VXOCnt0_CLK AND I(VXO53MHz_BUF) O(VXOCnt0_CLK)
*----( VXOCnt1 ) -------------------------------
VXOCnt1_D AND I(VXOCnt0_BUF, VXO_Div4_Q_BUF) O(VXOCnt1_D)
VXOCnt1 TFFSR I(VXOCnt1_D, VXOCnt1_CLK, VXOCnt1_AP, VXOCnt1_AR) O(VXOCnt1)
VXOCnt1_AP AND I(GND) O(VXOCnt1_AP)
VXOCnt1_AR AND I(GND) O(VXOCnt1_AR)
VXOCnt1_CLK AND I(VXO53MHz_BUF) O(VXOCnt1_CLK)
*----( VXOCnt2 ) -------------------------------
VXOCnt2_D AND I(VXOCnt0_BUF, VXOCnt1_BUF, VXO_Div4_Q_BUF) O(VXOCnt2_D)
VXOCnt2 TFFSR I(VXOCnt2_D, VXOCnt2_CLK, VXOCnt2_AP, VXOCnt2_AR) O(VXOCnt2)
VXOCnt2_AP AND I(GND) O(VXOCnt2_AP)
VXOCnt2_AR AND I(GND) O(VXOCnt2_AR)
VXOCnt2_CLK AND I(VXO53MHz_BUF) O(VXOCnt2_CLK)
*----( enctmg_reg ) -------------------------------
enctmg_reg_D AND I(VCC) O(enctmg_reg_D)
enctmg_reg DFFSRCE I(enctmg_reg_D, enctmg_reg_CLK, enctmg_reg_AP, enctmg_reg_AR, enctmg_reg_CE) O(enctmg_reg)
enctmg_reg_AP AND I(GND) O(enctmg_reg_AP)
enctmg_reg_AR AND I(vxo53_reg_BUF, enctmg_reg_BUF) O(enctmg_reg_AR)
enctmg_reg_CLK AND I(EncTmgn_BUF) O(enctmg_reg_CLK)
enctmg_reg_CE AND I(VCC) O(enctmg_reg_CE)
*----( vxo53_reg ) -------------------------------
vxo53_reg_D AND I(VCC) O(vxo53_reg_D)
vxo53_reg DFFSRCE I(vxo53_reg_D, vxo53_reg_CLK, vxo53_reg_AP, vxo53_reg_AR, vxo53_reg_CE) O(vxo53_reg)
vxo53_reg_AP AND I(GND) O(vxo53_reg_AP)
vxo53_reg_AR AND I(vxo53_reg_BUF, enctmg_reg_BUF) O(vxo53_reg_AR)
vxo53_reg_CLK AND I(VXO53MHz_BUF) O(vxo53_reg_CLK)
vxo53_reg_CE AND I(VCC) O(vxo53_reg_CE)
*----( Inverters )-------------------------------
D0_BAR INV I(D0) O(D0_BAR)
D1_BAR INV I(D1) O(D1_BAR)
EncTmgn_BAR INV I(EncTmgn) O(EncTmgn_BAR)
FC_Q_BAR INV I(FC_Q) O(FC_Q_BAR)
Gap_Q_BAR INV I(Gap_Q) O(Gap_Q_BAR)
IDtct_BAR INV I(IDtct) O(IDtct_BAR)
S0_BAR INV I(S0) O(S0_BAR)
S1_BAR INV I(S1) O(S1_BAR)
S2_BAR INV I(S2) O(S2_BAR)
SGap_Q_BAR INV I(SGap_Q) O(SGap_Q_BAR)
VXOCnt2_BAR INV I(VXOCnt2) O(VXOCnt2_BAR)
enctmg_reg_BAR INV I(enctmg_reg) O(enctmg_reg_BAR)
vxo53_reg_BAR INV I(vxo53_reg) O(vxo53_reg_BAR)
*----( Buffers )-------------------------------
Clk106MHz_BUF AND I(Clk106MHz) O(Clk106MHz_BUF)
D0_BUF AND I(D0) O(D0_BUF)
D1_BUF AND I(D1) O(D1_BUF)
EncTmgn_BUF AND I(EncTmgn) O(EncTmgn_BUF)
FC_Q_BUF AND I(FC_Q) O(FC_Q_BUF)
Gap_Q_BUF AND I(Gap_Q) O(Gap_Q_BUF)
RF_Inp_BUF AND I(RF_Inp) O(RF_Inp_BUF)
S0_BUF AND I(S0) O(S0_BUF)
S1_BUF AND I(S1) O(S1_BUF)
S2_BUF AND I(S2) O(S2_BUF)
SGap_Q_BUF AND I(SGap_Q) O(SGap_Q_BUF)
VXO53MHz_BUF AND I(VXO53MHz) O(VXO53MHz_BUF)
VXOCnt0_BUF AND I(VXOCnt0) O(VXOCnt0_BUF)
VXOCnt1_BUF AND I(VXOCnt1) O(VXOCnt1_BUF)
VXOCnt2_BUF AND I(VXOCnt2) O(VXOCnt2_BUF)
VXO_Div4_Q_BUF AND I(VXO_Div4_Q) O(VXO_Div4_Q_BUF)
enctmg_reg_BUF AND I(enctmg_reg) O(enctmg_reg_BUF)
vxo53_reg_BUF AND I(vxo53_reg) O(vxo53_reg_BUF)
*
 NETEND
*
 NETIN  Clk106MHz, EncTmgn, RF_Inp, VXO53MHz, VCC, GND
 NETOUT Clk53MHzO2, Clk53MHzOut, Down, FC, Gap, RF_Dtct, SGap, Up, VXO_Div4