"Program: xplafit version 3.21
"timdec2.ann created on:Jul 11 14:31:38 2001
module tmgdec2
Title ' '

"******** 4 Input Pins **********
VXO53MHz                            PIN 	18;
Clk106MHz                           PIN 	15;
EncTmgn                             PIN 	43;
RF_Inp                              PIN 	37;
"******** 9 Output Pins **********
Up                                  PIN 	23;
Down                                PIN 	19;
VXO_Div4                            PIN 	44;
FC                                  PIN 	33;
SGap                                PIN 	21;
Gap                                 PIN 	28;
Clk53MHzO2                          PIN 	35;
Clk53MHzOut                         PIN 	34;
RF_Dtct                             PIN 	22;
"******** 12 Nodes **********
Enc_Div2                            NODE	49;
D0                                  NODE	51;
D1                                  NODE	60;
S0                                  NODE	55;
S1                                  NODE	59;
S2                                  NODE	45;
IDtct                               NODE	46;
VXOCnt0                             NODE	48;
VXOCnt1                             NODE	47;
VXOCnt2                             NODE	53;
enctmg_reg                          NODE	52;
vxo53_reg                           NODE	54;


equations

"**********( VXOCnt2 )************
VXOCnt2.clk	=  VXO53MHz;
VXOCnt2.t	=  VXOCnt1.Q &  VXO_Div4.Q &  VXOCnt0.Q ;
"**********( D1 )************
D1.clk	=  Clk106MHz;
D1.d	=  D0.Q ;
"**********( S2 )************
S2.clk	=  Clk106MHz;
S2.t	=  S0.Q &  S1.Q ;
"**********( VXOCnt1 )************
VXOCnt1.clk	=  VXO53MHz;
VXOCnt1.t	=  VXO_Div4.Q &  VXOCnt0.Q ;
"**********( VXO_Div4 )************
VXO_Div4.clk	=  VXO53MHz;
VXO_Div4.t	=  VXOCnt0.Q ;
"**********( IDtct )************
IDtct.clk	=  RF_Inp;
IDtct.ar	=  VXOCnt1.Q &  VXO_Div4.Q &  VXOCnt0.Q &  VXOCnt2.Q ;
IDtct.d	= 1;
"**********( VXOCnt0 )************
VXOCnt0.clk	=  VXO53MHz;
VXOCnt0.t	= 1;
"**********( Enc_Div2 )************
Enc_Div2.clk	=   EncTmgn ;
Enc_Div2.t	= 1;
"**********( D0 )************
D0.clk	=  Clk106MHz;
D0.d	=  EncTmgn ;
"**********( enctmg_reg )************
enctmg_reg.clk	=   EncTmgn ;
enctmg_reg.ar	=  enctmg_reg.Q &  vxo53_reg.Q ;
enctmg_reg.d	= 1;
"**********( vxo53_reg )************
vxo53_reg.clk	=  VXO53MHz;
vxo53_reg.ar	=  enctmg_reg.Q &  vxo53_reg.Q ;
vxo53_reg.d	= 1;
"**********( S0 )************
S0.clk	=  Clk106MHz;
S0.t	= !(!S2.Q & !EncTmgn & !S0.Q & !S1.Q );
"**********( S1 )************
S1.clk	=  Clk106MHz;
S1.t	= !(!S0.Q 
		# !S2.Q & !EncTmgn & !S1.Q );
"**********( Down )************
Down.oe	= !enctmg_reg.Q &  vxo53_reg.Q ;
Down	= 0;
"**********( SGap )************
SGap.clk	=  Clk106MHz;
SGap.t	= !D0.Q &  S2.Q &  EncTmgn &  SGap.Q &  D1.Q & !S0.Q 
		& !S1.Q 
		#  D0.Q &  S2.Q &  EncTmgn & !SGap.Q & !D1.Q & !S0.Q 
		& !S1.Q 
		# !D0.Q &  S2.Q & !EncTmgn & !SGap.Q & !D1.Q & !S0.Q 
		& !S1.Q ;
"**********( RF_Dtct )************
RF_Dtct.clk	=  RF_Inp;
RF_Dtct.ar	=  VXOCnt1.Q &  VXO_Div4.Q &  VXOCnt0.Q & !IDtct.Q & !VXOCnt2.Q ;
RF_Dtct.d	= 1;
"**********( Up )************
Up.oe	=  enctmg_reg.Q & !vxo53_reg.Q ;
Up	= 1;
"**********( Gap )************
Gap.clk	=  Clk106MHz;
Gap.t	= !S1.Q & !D0.Q &  S2.Q &  EncTmgn &  D1.Q & !S0.Q 
		&  Gap.Q 
		# !S1.Q & !D0.Q &  S2.Q & !EncTmgn &  D1.Q & !S0.Q 
		& !Gap.Q ;
"**********( FC )************
FC.clk	=  Clk106MHz;
FC.t	= !S1.Q &  FC.Q & !D0.Q &  S2.Q &  EncTmgn &  D1.Q 
		& !S0.Q 
		# !S1.Q &  FC.Q &  D0.Q &  S2.Q & !EncTmgn & !D1.Q 
		& !S0.Q 
		# !S1.Q & !FC.Q &  S2.Q &  EncTmgn & !D1.Q & !S0.Q ;
"**********( Clk53MHzOut )************
Clk53MHzOut.clk	=  Clk106MHz;
Clk53MHzOut.d	=  S0.Q ;
"**********( Clk53MHzO2 )************
Clk53MHzO2.clk	=  Clk106MHz;
Clk53MHzO2.d	=  S0.Q ;

end