"Modgen version 3.21
"div4dec.phj created on:Wed Jul 11 14:48:59 2001
Module div4dec
Title ' '

Declarations

Clk106MHz      	 PIN 15;
VXO53MHz       	 PIN 18;
DN             	 PIN 19;
SGap           	 PIN 21;
RF_Dtct        	 PIN 22;
UP             	 PIN 23;
Gap            	 PIN 28;
FC             	 PIN 33;
Clk53MHzOut    	 PIN 34;
Clk53MHzO2     	 PIN 35;
RF_In          	 PIN 37;
nEncTmg        	 PIN 43;
VXO_Div4       	 PIN 44;


"Nodelist

VXOCnt2        	NODE 53;
D1             	NODE 60;
S2             	NODE 45;
VXOCnt1        	NODE 47;
IDtct          	NODE 46;
Mult_Div2      	NODE 48;
VXOCnt0        	NODE 49;
D0             	NODE 51;
Enc_FF         	NODE 52;
VXO_FF         	NODE 54;
S0             	NODE 55;
S1             	NODE 59;


Equations

VXOCnt2.clk	=  VXO53MHz;
VXOCnt2.t	=  VXOCnt1.Q &  VXO_Div4.Q &  VXOCnt0.Q ;
D1.clk	= !Clk106MHz;
D1.d	=  D0.Q ;
S2.clk	= !Clk106MHz;
S2.t	=  S0.Q &  S1.Q ;
VXOCnt1.clk	=  VXO53MHz;
VXOCnt1.t	=  VXO_Div4.Q &  VXOCnt0.Q ;
VXO_Div4.clk	=  VXO53MHz;
VXO_Div4.t	=  VXOCnt0.Q ;
IDtct.clk	=  RF_In;
IDtct.ar	=  VXOCnt1.Q &  VXO_Div4.Q &  VXOCnt0.Q &  VXOCnt2.Q ;
IDtct.d	= 1;
Mult_Div2.clk	= !Clk106MHz;
Mult_Div2.t	= 1;
VXOCnt0.clk	=  VXO53MHz;
VXOCnt0.t	= 1;
D0.clk	= !Clk106MHz;
D0.d	=  nEncTmg ;
Enc_FF.clk	= !( nEncTmg );
Enc_FF.ar	=  Enc_FF.Q &  VXO_FF.Q ;
Enc_FF.d	= 1;
VXO_FF.clk	=  Mult_Div2.Q ;
VXO_FF.ar	=  Enc_FF.Q &  VXO_FF.Q ;
VXO_FF.d	= 1;
S0.clk	= !Clk106MHz;
S0.t	= !(!S2.Q & !nEncTmg & !S0.Q & !S1.Q );
S1.clk	= !Clk106MHz;
S1.t	= !(!S0.Q 
		# !S2.Q & !nEncTmg & !S1.Q );
DN.oe	= !Enc_FF.Q &  VXO_FF.Q ;
DN	= 0;
SGap.clk	= !Clk106MHz;
SGap.t	= !D0.Q &  S2.Q &  nEncTmg &  SGap.Q &  D1.Q & !S0.Q 
		& !S1.Q 
		#  D0.Q &  S2.Q &  nEncTmg & !SGap.Q & !D1.Q & !S0.Q 
		& !S1.Q 
		# !D0.Q &  S2.Q & !nEncTmg & !SGap.Q & !D1.Q & !S0.Q 
		& !S1.Q ;
RF_Dtct.clk	=  RF_In;
RF_Dtct.ar	=  VXOCnt1.Q &  VXO_Div4.Q &  VXOCnt0.Q & !IDtct.Q & !VXOCnt2.Q ;
RF_Dtct.d	= 1;
UP.oe	=  Enc_FF.Q & !VXO_FF.Q ;
UP	= 1;
Gap.clk	= !Clk106MHz;
Gap.t	= !S1.Q & !D0.Q &  S2.Q &  nEncTmg &  D1.Q & !S0.Q 
		&  Gap.Q 
		# !S1.Q & !D0.Q &  S2.Q & !nEncTmg &  D1.Q & !S0.Q 
		& !Gap.Q ;
FC.clk	= !Clk106MHz;
FC.t	= !S1.Q &  FC.Q & !D0.Q &  S2.Q &  nEncTmg &  D1.Q 
		& !S0.Q 
		# !S1.Q &  FC.Q &  D0.Q &  S2.Q & !nEncTmg & !D1.Q 
		& !S0.Q 
		# !S1.Q & !FC.Q &  S2.Q &  nEncTmg & !D1.Q & !S0.Q ;
Clk53MHzOut.clk	= !Clk106MHz;
Clk53MHzOut.t	= 1;
Clk53MHzO2.clk	= !Clk106MHz;
Clk53MHzO2.t	= 1;


End;