module tmgdec;

"Sten Hansen 		Fermilab		10-19-00

"Decodes Gap, Sync Gap and FC from 53MHz encoded data when in remote mode.
"Generates these signals internally when in local mode.
"Phase detector compares phase of incoming encoded timing with local VXO.
"Divides 53MHz by 4 for use by ST49C101 x8 frequency multiplier.
"Generates a status output when 53MHz RF is present
"Generates 2.9 us reference pulse from FC for CBDelay chip.

"EM - Modified 1/23/01 to adapt to our realities

"Inputs..
        Clk106MHz,VXO53MHz		pin  15,18;
        RF_In,RF_Inn,EncTmg,nEncTmg	pin  37,39,42,43;

"Outputs..
	Gap,SGap,FC,VXO_Div4		pin 28,21,33,44		istype 'reg';
	Clk53MHzOut				pin 34			istype 'reg';
	UP,DN					pin 23,19			istype 'com';
	RF_Dtct				pin 22			istype 'reg';

"Buried nodes..
	XCnt7..XCnt0,PSTC,XCTC		node istype 'reg';
	PS3..PS0,Mult_Div2		node istype 'reg';
	S2..S0,D1,D0			node istype 'reg';
	VXOCnt2..VXOCnt0,IDtct		node istype 'reg';
	Enc_FF,VXO_FF			node istype 'reg';

"Set Definitions..
	VXOCnt = [VXOCnt2,VXOCnt1,VXO_Div4,VXOCnt0];
	PS = [PS3..PS0];
	XCnt = [XCnt7..XCnt0];

"Define serial data bit patterns..
	SData  = [D1,D0,nEncTmg];
	SGapHi   = [0,0,0];
	FCHi     = [0,0,1];
	FCLo     = [0,1,0];
	SGapFCHi = [0,1,1];
	GapHi    = [1,0,0];
	AllLo    = [1,0,1];

"State definitions..
	IState = [S2..S0];
	IdleLo = [0,0,0]; "0
	IdleHi = [0,0,1]; "1
	Shft0  = [0,1,0]; "2
	Shft1  = [0,1,1]; "3
	Shft2  = [1,0,0]; "4
	Shft3  = [1,0,1]; "5
	Shft4  = [1,1,0]; "6
	Shft5  = [1,1,1]; "7

Equations

     [Gap.C,SGap.C,FC.C,Clk53MHzOut.C,IState.C,D1.C,D0.C] = !Clk106MHz;

"Clocks for phase detector related signals..
      [VXOCnt.C] = VXO53MHz;
      Mult_Div2.C = !Clk106MHz;

	Mult_Div2.t := 1;

	VXO_FF := 1;
	VXO_FF.AR = VXO_FF & Enc_FF;
	VXO_FF.C = Mult_Div2;

	Enc_FF := 1; "Rem_Loc;
	Enc_FF.AR = VXO_FF & Enc_FF;
      Enc_FF.C = !nEncTmg;

"In Remote mode enable UP and DN according to Phase Detector FFs
"In Local mode, produce a 50% duty cycle square wave on DN, tri-state
"UP off to supply ~1.8V to the tuning pin of the VXO

	UP = 1;
	UP.OE = !VXO_FF & Enc_FF;

	DN = 0; "VXOCnt1 & !Rem_Loc;
	DN.OE = VXO_FF & !Enc_FF;

"Reset internal clock detect periodically
	IDtct.C = RF_In;
	IDtct := 1;
	IDtct.AR = (VXOCnt == 15);

"Arrange for external clock detect to be a DC level for less EMI
	RF_Dtct.C = RF_In;
	RF_Dtct := 1;
	RF_Dtct.AR = !IDtct & (VXOCnt == 7);

"Use bit 1 of the counter as VXO/4 to get correct frequency for x8 multiplier
	VXOCnt := (VXOCnt + 1);

"Keep clock in phase with encoded clock, or with internal signal generator..
	Clk53MHzOut := !Clk53MHzOut;" # (IState == Shft1);

" Shift in 2 data bits from Encoded Clock stream
	D0 := nEncTmg;
	D1 := D0;

" Once data is shifted in, output transitions depend on the resulting
" 3 bit pattern (D1,D0,Encoded Clock) if in remote mode. In local mode
" outputs are dependent on internal counter values (XCnt)

SGap.T := (!SGap & ((IState == Shft2)
		& ((SData == SGapHi) # (SData == SGapFCHi))))
         # (SGap & ((IState == Shft2) & (SData == AllLo)));

FC.T := (!FC & ((IState == Shft2)
		& ((SData == FCHi) # (SData == SGapFCHi))))
       # (FC & ((IState == Shft2)
		& ((SData == FCLo) # (SData == AllLo))));

Gap.T := (!Gap & ((IState == Shft2) & (SData == GapHi)))
        # (Gap & ((IState == Shft2) & (SData == AllLo)));

State_Diagram IState

"Bounce between IdleLo and IdleHi until EncTmg is high for 2 cycles..
State IdleLo: If  nEncTmg then IdleHi else IdleLo;
State IdleHi: If !nEncTmg then IdleLo else Shft0;

"Go through a total of 8 states before looking for another pattern..
State Shft0: goto Shft1;
State Shft1: goto Shft2;
State Shft2: goto Shft3;
State Shft3: goto Shft4;
State Shft4: goto Shft5;
State Shft5: goto IdleLo;

end tmggen;