" XPLAOPT Version 3.21
" Created on Wed Jul 11 14:48:57 2001
" 25 Mcells, 0 PLApts, 34 PALpts, 2 Levels
" XPLAOPT -run s -i div4dec.phd -it phd -o div4dec.pla -ot tt2 -dev pz5064cs7bc 
"         -log div4dec.dox -reg -fi 36 -th 21 -effort f -net -rsp xplaopt.rsp 
MODULE tmgdec

	VXO53MHz  pin 18 ; 
 	Clk106MHz  pin 15 ; 
 	nEncTmg  pin 43 ; 
 	RF_In  pin 37 ; 
 	VXO_Div4  pin 44 ;  " 1 pt.
 	FC  pin 33 ;  " 3 pt.
 	SGap  pin 21 ;  " 3 pt.
 	Gap  pin 28 ;  " 2 pt.
 	Clk53MHzO2  pin 35 ;  " 0 pt.
 	Clk53MHzOut  pin 34 ;  " 0 pt.
 	DN  pin 19 ;  " 0 pt.
 	UP  pin 23 ;  " 1 pt.
 	RF_Dtct  pin 22 ;  " 1 pt.
 

	Mult_Div2  node ;  " 1 pt.
 	D0  node ;  " 1 pt.
 	D1  node ;  " 1 pt.
 	S0  node ;  " 1 pt.
 	S1  node ;  " 2 pt.
 	S2  node ;  " 1 pt.
 	IDtct  node ;  " 1 pt.
 	VXOCnt0  node ;  " 1 pt.
 	VXOCnt1  node ;  " 1 pt.
 	VXOCnt2  node ;  " 1 pt.
 	VXO_FF  node ;  " 1 pt.
 	Enc_FF  node ;  " 1 pt.
 	N_PZ_0  node istype 'collapse';  " 1 pt.
 	N_PZ_1  node istype 'collapse';  " 2 pt.
 	N_PZ_2  node istype 'collapse';  " 3 pt.
 	N_PZ_3  node istype 'collapse';  " 4 pt.
 

EQUATIONS 

 Clk53MHzO2.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
! Clk53MHzO2.T = 0;
 Clk53MHzOut.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
! Clk53MHzOut.T = 0;
 D0.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 D0.D = nEncTmg;		"--- [PT=1, FI=1, LVL=1] ---
 D1.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 D1.D = D0.Q;		"--- [PT=1, FI=1, LVL=1] ---
 DN = 0;
 DN.OE = VXO_FF.Q & !Enc_FF.Q;		"--- [PT=1, FI=2, LVL=1] ---
 Enc_FF.AR = VXO_FF.Q & Enc_FF.Q;		"--- [PT=1, FI=2, LVL=1] ---
 Enc_FF.CLK = !nEncTmg;		"--- [PT=1, FI=1, LVL=1] ---
 Enc_FF.D = 1;
 FC.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 FC.T = nEncTmg & !S0.Q & !S1.Q & S2.Q & !D1.Q & !FC.Q
      # nEncTmg & !S0.Q & !S1.Q & S2.Q & !D0.Q & D1.Q & FC.Q
      # !nEncTmg & !S0.Q & !S1.Q & S2.Q & D0.Q & !D1.Q & FC.Q
    ;		"--- [PT=3, FI=7, LVL=1] ---
 Gap.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 Gap.T = !nEncTmg & !D0.Q & !S0.Q & !S1.Q & S2.Q & D1.Q & !Gap.Q
      # nEncTmg & !D0.Q & !S0.Q & !S1.Q & S2.Q & D1.Q & Gap.Q
    ;		"--- [PT=2, FI=7, LVL=1] ---
 IDtct.AR = VXOCnt0.Q & VXO_Div4.Q & VXOCnt1.Q & VXOCnt2.Q
    ;		"--- [PT=1, FI=4, LVL=1] ---
 IDtct.CLK = RF_In;		"--- [PT=1, FI=1, LVL=1] ---
 IDtct.D = 1;
 Mult_Div2.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 Mult_Div2.D = !Mult_Div2.Q;		"--- [PT=1, FI=1, LVL=1] ---
 N_PZ_0 = !VXOCnt0.Q;		"--- [PT=1, FI=1, LVL=1] ---
 N_PZ_1 = VXOCnt0.Q & !VXO_Div4.Q
      # !VXOCnt0.Q & VXO_Div4.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_2 = VXOCnt0.Q & VXO_Div4.Q & !VXOCnt1.Q
      # !VXO_Div4.Q & VXOCnt1.Q
      # !VXOCnt0.Q & VXOCnt1.Q;		"--- [PT=3, FI=3, LVL=1] ---
 N_PZ_3 = VXOCnt0.Q & VXO_Div4.Q & VXOCnt1.Q & !VXOCnt2.Q
      # !VXOCnt1.Q & VXOCnt2.Q
      # !VXO_Div4.Q & VXOCnt2.Q
      # !VXOCnt0.Q & VXOCnt2.Q;		"--- [PT=4, FI=4, LVL=1] ---
 RF_Dtct.AR = VXOCnt0.Q & VXO_Div4.Q & VXOCnt1.Q & !VXOCnt2.Q & !IDtct.Q
    ;		"--- [PT=1, FI=5, LVL=1] ---
 RF_Dtct.CLK = RF_In;		"--- [PT=1, FI=1, LVL=1] ---
 RF_Dtct.D = 1;
 S0.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
! S0.T = !nEncTmg & !S0.Q & !S1.Q & !S2.Q;		"--- [PT=1, FI=4, LVL=1] ---
 S1.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
! S1.T = !S0.Q
      # !nEncTmg & !S1.Q & !S2.Q;		"--- [PT=2, FI=4, LVL=1] ---
 S2.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 S2.T = S0.Q & S1.Q;		"--- [PT=1, FI=2, LVL=1] ---
 SGap.CLK = !Clk106MHz;		"--- [PT=1, FI=1, LVL=1] ---
 SGap.T = !nEncTmg & !D0.Q & !SGap.Q & !S0.Q & !S1.Q & S2.Q & !D1.Q
      # nEncTmg & D0.Q & !SGap.Q & !S0.Q & !S1.Q & S2.Q & !D1.Q
      # nEncTmg & !D0.Q & SGap.Q & !S0.Q & !S1.Q & S2.Q & D1.Q
    ;		"--- [PT=3, FI=7, LVL=1] ---
 UP = 1;
 UP.OE = !VXO_FF.Q & Enc_FF.Q;		"--- [PT=1, FI=2, LVL=1] ---
 VXOCnt0.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXOCnt0.D = N_PZ_0;		"--- [PT=1, FI=1, LVL=2] ---
 VXOCnt1.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXOCnt1.D = N_PZ_2;		"--- [PT=1, FI=1, LVL=2] ---
 VXOCnt2.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXOCnt2.D = N_PZ_3;		"--- [PT=1, FI=1, LVL=2] ---
 VXO_Div4.CLK = VXO53MHz;		"--- [PT=1, FI=1, LVL=1] ---
 VXO_Div4.D = N_PZ_1;		"--- [PT=1, FI=1, LVL=2] ---
 VXO_FF.AR = VXO_FF.Q & Enc_FF.Q;		"--- [PT=1, FI=2, LVL=1] ---
 VXO_FF.CLK = Mult_Div2.Q;		"--- [PT=1, FI=1, LVL=1] ---
 VXO_FF.D = 1;
END